From patchwork Sat Apr 29 01:23:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 678045 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2DFBBC77B7C for ; Sat, 29 Apr 2023 01:24:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347247AbjD2BYB (ORCPT ); Fri, 28 Apr 2023 21:24:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39058 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347255AbjD2BX7 (ORCPT ); Fri, 28 Apr 2023 21:23:59 -0400 Received: from mail-wm1-x336.google.com (mail-wm1-x336.google.com [IPv6:2a00:1450:4864:20::336]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 114EF49D5 for ; Fri, 28 Apr 2023 18:23:57 -0700 (PDT) Received: by mail-wm1-x336.google.com with SMTP id 5b1f17b1804b1-3f19a7f9424so2957705e9.2 for ; Fri, 28 Apr 2023 18:23:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1682731435; x=1685323435; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PNbKXAJZnG963Qvmlqli7aoanXGiQrPfW1G90ARIb60=; b=yPGnXFFbAjQOwFWaHLJeOZ7hkHwjKyZNd4MSWSLp+oG2AAaXBfwYvcZT47a1CAGV29 3bHp7AbO7xF+bxe1vHkQvkgfqa+mUK1aqAVg+fDiwfBoqcEPa6/xBgbEyDefToha+xrc MNPD2TuZPU+Nwf6mWvZi3/TQHfwGBpyKPT/1X+GQmHYcTUFn5SOljOx8SYPr4Hpjv1K0 ZpeA4//bo7AhGrrFXHUArxXl5oRjs33YdtIQm5bhW7GW+wwlnxAC5uaAk/3lxs6h1lo/ ZfWuQ6G+A7COIfXMIcJAxcr/LXrnksHu2gwNJ+cGh3jHUtTPS+3BGcsZlI9QPww0b7dB V3Mw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682731435; x=1685323435; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PNbKXAJZnG963Qvmlqli7aoanXGiQrPfW1G90ARIb60=; b=ePoCi5Pn71BNwXs8kofCeo+N/PFjpnzXVsreXJ0ZT04sPvqBHK6G9wa1+RGMVYA/2Z VRKaSyGzaYx23Vdg93P1CtOWrhaNGVSJFbi2X+ebMjrYTJSoMTdTePhhzXROFDn2pzN1 e3CL9wTJ/Qtzy7GfG0LfJ0OjEcffznv8KK20nlYKktUAF9RK2JqG8MaLfBewnRpYocSX RXH2C5hTFugKKdag4Pi3GT8qZaJ/UyRncl5EUmAjfCYMGtz+5jqmwuhOxy/IOnlMbw02 rfql+Semc3lkAzJBs7vWhwoXgtjODFc2sydG+98vcls87UwbTC0YDjiOY6MxiO08rhil ukeA== X-Gm-Message-State: AC+VfDzmQ7FCTMJt53H98BNIJ7HKiKKdLRTSfkI1nUV2KDNJ2quf+/zM zWBe4ioJph5/OK2jO7f+hvrTeg== X-Google-Smtp-Source: ACHHUZ4dG3btYCarxewSOb6da1ADGj91pkJ9V3oEeMHCo57XO3mKSjyGhsemPU1wBI8j16e/DD3Cdg== X-Received: by 2002:a5d:6748:0:b0:2ce:a34b:2b0b with SMTP id l8-20020a5d6748000000b002cea34b2b0bmr5026997wrw.28.1682731435491; Fri, 28 Apr 2023 18:23:55 -0700 (PDT) Received: from eriador.lumag.spb.ru ([212.140.138.218]) by smtp.gmail.com with ESMTPSA id p10-20020a5d48ca000000b003047dc162f7sm12983554wrs.67.2023.04.28.18.23.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Apr 2023 18:23:55 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Abhinav Kumar Cc: Stephen Boyd , David Airlie , Daniel Vetter , Bjorn Andersson , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH v2 1/3] drm/msm/dpu: drop SSPP's SRC subblock Date: Sat, 29 Apr 2023 04:23:51 +0300 Message-Id: <20230429012353.2569481-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230429012353.2569481-1-dmitry.baryshkov@linaro.org> References: <20230429012353.2569481-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The src_blk declares a lame copy of main SSPP register space. It's offset is always 0. It's length has been fixed to 0x150, while SSPP's length is now correct. Drop the src_blk and access SSPP registers without additional subblock lookup. Signed-off-by: Dmitry Baryshkov Reviewed-by: Marijn Suijten --- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 14 +- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 14 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 128 ++++++++---------- 3 files changed, 58 insertions(+), 98 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index 03f162af1a50..c3b0db1fdeb2 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -13,7 +13,7 @@ #include "dpu_kms.h" #define VIG_BASE_MASK \ - (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) |\ + (BIT(DPU_SSPP_QOS) |\ BIT(DPU_SSPP_CDP) |\ BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_EXCL_RECT)) @@ -39,7 +39,7 @@ #define VIG_QCM2290_MASK (VIG_BASE_MASK | BIT(DPU_SSPP_QOS_8LVL)) #define DMA_MSM8998_MASK \ - (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) |\ + (BIT(DPU_SSPP_QOS) |\ BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\ BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_EXCL_RECT)) @@ -50,7 +50,7 @@ (VIG_SC7280_MASK | BIT(DPU_SSPP_SMART_DMA_V2)) #define DMA_SDM845_MASK \ - (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_QOS_8LVL) |\ + (BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_QOS_8LVL) |\ BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\ BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_EXCL_RECT)) @@ -252,8 +252,6 @@ static const uint32_t wb2_formats[] = { .maxdwnscale = MAX_DOWNSCALE_RATIO, \ .maxupscale = MAX_UPSCALE_RATIO, \ .smart_dma_priority = sdma_pri, \ - .src_blk = {.name = STRCAT("sspp_src_", num), \ - .id = DPU_SSPP_SRC, .base = 0x00, .len = 0x150,}, \ .scaler_blk = {.name = STRCAT("sspp_scaler", num), \ .id = qseed_ver, \ .base = 0xa00, .len = 0xa0,}, \ @@ -272,8 +270,6 @@ static const uint32_t wb2_formats[] = { .maxdwnscale = MAX_DOWNSCALE_RATIO, \ .maxupscale = MAX_UPSCALE_RATIO, \ .smart_dma_priority = sdma_pri, \ - .src_blk = {.name = STRCAT("sspp_src_", num), \ - .id = DPU_SSPP_SRC, .base = 0x00, .len = 0x150,}, \ .scaler_blk = {.name = STRCAT("sspp_scaler", num), \ .id = qseed_ver, \ .base = 0xa00, .len = 0xa0,}, \ @@ -292,8 +288,6 @@ static const uint32_t wb2_formats[] = { .maxdwnscale = SSPP_UNITY_SCALE, \ .maxupscale = SSPP_UNITY_SCALE, \ .smart_dma_priority = sdma_pri, \ - .src_blk = {.name = STRCAT("sspp_src_", num), \ - .id = DPU_SSPP_SRC, .base = 0x00, .len = 0x150,}, \ .format_list = plane_formats, \ .num_formats = ARRAY_SIZE(plane_formats), \ .virt_format_list = plane_formats, \ @@ -375,8 +369,6 @@ static const struct dpu_sspp_sub_blks sm8550_dma_sblk_5 = _DMA_SBLK("13", 6); .maxdwnscale = SSPP_UNITY_SCALE, \ .maxupscale = SSPP_UNITY_SCALE, \ .smart_dma_priority = sdma_pri, \ - .src_blk = {.name = STRCAT("sspp_src_", num), \ - .id = DPU_SSPP_SRC, .base = 0x00, .len = 0x150,}, \ .format_list = plane_formats_yuv, \ .num_formats = ARRAY_SIZE(plane_formats_yuv), \ .virt_format_list = plane_formats, \ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index 71584cd56fd7..3e92c2c66716 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -64,7 +64,6 @@ enum { /** * SSPP sub-blocks/features - * @DPU_SSPP_SRC Src and fetch part of the pipes, * @DPU_SSPP_SCALER_QSEED2, QSEED2 algorithm support * @DPU_SSPP_SCALER_QSEED3, QSEED3 alogorithm support * @DPU_SSPP_SCALER_QSEED3LITE, QSEED3 Lite alogorithm support @@ -85,8 +84,7 @@ enum { * @DPU_SSPP_MAX maximum value */ enum { - DPU_SSPP_SRC = 0x1, - DPU_SSPP_SCALER_QSEED2, + DPU_SSPP_SCALER_QSEED2 = 0x1, DPU_SSPP_SCALER_QSEED3, DPU_SSPP_SCALER_QSEED3LITE, DPU_SSPP_SCALER_QSEED4, @@ -278,14 +276,6 @@ enum { u32 base; \ u32 len -/** - * struct dpu_src_blk: SSPP part of the source pipes - * @info: HW register and features supported by this sub-blk - */ -struct dpu_src_blk { - DPU_HW_SUBBLK_INFO; -}; - /** * struct dpu_scaler_blk: Scaler information * @info: HW register and features supported by this sub-blk @@ -392,7 +382,6 @@ struct dpu_caps { * @smart_dma_priority: hw priority of rect1 of multirect pipe * @max_per_pipe_bw: maximum allowable bandwidth of this pipe in kBps * @qseed_ver: qseed version - * @src_blk: * @scaler_blk: * @csc_blk: * @hsic: @@ -413,7 +402,6 @@ struct dpu_sspp_sub_blks { u32 smart_dma_priority; u32 max_per_pipe_bw; u32 qseed_ver; - struct dpu_src_blk src_blk; struct dpu_scaler_blk scaler_blk; struct dpu_pp_blk csc_blk; struct dpu_pp_blk hsic_blk; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c index cf70a9bd1034..83a091f978e2 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c @@ -12,7 +12,7 @@ #define DPU_FETCH_CONFIG_RESET_VALUE 0x00000087 -/* DPU_SSPP_SRC */ +/* SSPP registers */ #define SSPP_SRC_SIZE 0x00 #define SSPP_SRC_XY 0x08 #define SSPP_OUT_SIZE 0x0c @@ -149,9 +149,6 @@ static int _sspp_subblk_offset(struct dpu_hw_sspp *ctx, sblk = ctx->cap->sblk; switch (s_id) { - case DPU_SSPP_SRC: - *idx = sblk->src_blk.base; - break; case DPU_SSPP_SCALER_QSEED2: case DPU_SSPP_SCALER_QSEED3: case DPU_SSPP_SCALER_RGB: @@ -172,9 +169,8 @@ static void dpu_hw_sspp_setup_multirect(struct dpu_sw_pipe *pipe) { struct dpu_hw_sspp *ctx = pipe->sspp; u32 mode_mask; - u32 idx; - if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx)) + if (!ctx) return; if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) { @@ -185,7 +181,7 @@ static void dpu_hw_sspp_setup_multirect(struct dpu_sw_pipe *pipe) */ mode_mask = 0; } else { - mode_mask = DPU_REG_READ(&ctx->hw, SSPP_MULTIRECT_OPMODE + idx); + mode_mask = DPU_REG_READ(&ctx->hw, SSPP_MULTIRECT_OPMODE); mode_mask |= pipe->multirect_index; if (pipe->multirect_mode == DPU_SSPP_MULTIRECT_TIME_MX) mode_mask |= BIT(2); @@ -193,7 +189,7 @@ static void dpu_hw_sspp_setup_multirect(struct dpu_sw_pipe *pipe) mode_mask &= ~BIT(2); } - DPU_REG_WRITE(&ctx->hw, SSPP_MULTIRECT_OPMODE + idx, mode_mask); + DPU_REG_WRITE(&ctx->hw, SSPP_MULTIRECT_OPMODE, mode_mask); } static void _sspp_setup_opmode(struct dpu_hw_sspp *ctx, @@ -247,9 +243,8 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe, u32 opmode = 0; u32 fast_clear = 0; u32 op_mode_off, unpack_pat_off, format_off; - u32 idx; - if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx) || !fmt) + if (!ctx || !fmt) return; if (pipe->multirect_index == DPU_SSPP_RECT_SOLO || @@ -264,7 +259,7 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe, } c = &ctx->hw; - opmode = DPU_REG_READ(c, op_mode_off + idx); + opmode = DPU_REG_READ(c, op_mode_off); opmode &= ~(MDSS_MDP_OP_FLIP_LR | MDSS_MDP_OP_FLIP_UD | MDSS_MDP_OP_BWC_EN | MDSS_MDP_OP_PE_OVERRIDE); @@ -352,12 +347,12 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe, VIG_CSC_10_EN | VIG_CSC_10_SRC_DATAFMT, DPU_FORMAT_IS_YUV(fmt)); - DPU_REG_WRITE(c, format_off + idx, src_format); - DPU_REG_WRITE(c, unpack_pat_off + idx, unpack); - DPU_REG_WRITE(c, op_mode_off + idx, opmode); + DPU_REG_WRITE(c, format_off, src_format); + DPU_REG_WRITE(c, unpack_pat_off, unpack); + DPU_REG_WRITE(c, op_mode_off, opmode); /* clear previous UBWC error */ - DPU_REG_WRITE(c, SSPP_UBWC_ERROR_STATUS + idx, BIT(31)); + DPU_REG_WRITE(c, SSPP_UBWC_ERROR_STATUS, BIT(31)); } static void dpu_hw_sspp_setup_pe_config(struct dpu_hw_sspp *ctx, @@ -368,9 +363,8 @@ static void dpu_hw_sspp_setup_pe_config(struct dpu_hw_sspp *ctx, u32 lr_pe[4], tb_pe[4], tot_req_pixels[4]; const u32 bytemask = 0xff; const u32 shortmask = 0xffff; - u32 idx; - if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx) || !pe_ext) + if (!ctx || !pe_ext) return; c = &ctx->hw; @@ -400,21 +394,21 @@ static void dpu_hw_sspp_setup_pe_config(struct dpu_hw_sspp *ctx, } /* color 0 */ - DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C0_LR + idx, lr_pe[0]); - DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C0_TB + idx, tb_pe[0]); - DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C0_REQ_PIXELS + idx, + DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C0_LR, lr_pe[0]); + DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C0_TB, tb_pe[0]); + DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C0_REQ_PIXELS, tot_req_pixels[0]); /* color 1 and color 2 */ - DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C1C2_LR + idx, lr_pe[1]); - DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C1C2_TB + idx, tb_pe[1]); - DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C1C2_REQ_PIXELS + idx, + DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C1C2_LR, lr_pe[1]); + DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C1C2_TB, tb_pe[1]); + DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C1C2_REQ_PIXELS, tot_req_pixels[1]); /* color 3 */ - DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C3_LR + idx, lr_pe[3]); - DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C3_TB + idx, lr_pe[3]); - DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C3_REQ_PIXELS + idx, + DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C3_LR, lr_pe[3]); + DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C3_TB, lr_pe[3]); + DPU_REG_WRITE(c, SSPP_SW_PIX_EXT_C3_REQ_PIXELS, tot_req_pixels[3]); } @@ -453,9 +447,8 @@ static void dpu_hw_sspp_setup_rects(struct dpu_sw_pipe *pipe, struct dpu_hw_blk_reg_map *c; u32 src_size, src_xy, dst_size, dst_xy; u32 src_size_off, src_xy_off, out_size_off, out_xy_off; - u32 idx; - if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx) || !cfg) + if (!ctx || !cfg) return; c = &ctx->hw; @@ -483,10 +476,10 @@ static void dpu_hw_sspp_setup_rects(struct dpu_sw_pipe *pipe, drm_rect_width(&cfg->dst_rect); /* rectangle register programming */ - DPU_REG_WRITE(c, src_size_off + idx, src_size); - DPU_REG_WRITE(c, src_xy_off + idx, src_xy); - DPU_REG_WRITE(c, out_size_off + idx, dst_size); - DPU_REG_WRITE(c, out_xy_off + idx, dst_xy); + DPU_REG_WRITE(c, src_size_off, src_size); + DPU_REG_WRITE(c, src_xy_off, src_xy); + DPU_REG_WRITE(c, out_size_off, dst_size); + DPU_REG_WRITE(c, out_xy_off, dst_xy); } static void dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe *pipe, @@ -495,24 +488,23 @@ static void dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe *pipe, struct dpu_hw_sspp *ctx = pipe->sspp; u32 ystride0, ystride1; int i; - u32 idx; - if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx)) + if (!ctx) return; if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) { for (i = 0; i < ARRAY_SIZE(layout->plane_addr); i++) - DPU_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR + idx + i * 0x4, + DPU_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR + i * 0x4, layout->plane_addr[i]); } else if (pipe->multirect_index == DPU_SSPP_RECT_0) { - DPU_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR + idx, + DPU_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR, layout->plane_addr[0]); - DPU_REG_WRITE(&ctx->hw, SSPP_SRC2_ADDR + idx, + DPU_REG_WRITE(&ctx->hw, SSPP_SRC2_ADDR, layout->plane_addr[2]); } else { - DPU_REG_WRITE(&ctx->hw, SSPP_SRC1_ADDR + idx, + DPU_REG_WRITE(&ctx->hw, SSPP_SRC1_ADDR, layout->plane_addr[0]); - DPU_REG_WRITE(&ctx->hw, SSPP_SRC3_ADDR + idx, + DPU_REG_WRITE(&ctx->hw, SSPP_SRC3_ADDR, layout->plane_addr[2]); } @@ -522,8 +514,8 @@ static void dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe *pipe, ystride1 = (layout->plane_pitch[2]) | (layout->plane_pitch[3] << 16); } else { - ystride0 = DPU_REG_READ(&ctx->hw, SSPP_SRC_YSTRIDE0 + idx); - ystride1 = DPU_REG_READ(&ctx->hw, SSPP_SRC_YSTRIDE1 + idx); + ystride0 = DPU_REG_READ(&ctx->hw, SSPP_SRC_YSTRIDE0); + ystride1 = DPU_REG_READ(&ctx->hw, SSPP_SRC_YSTRIDE1); if (pipe->multirect_index == DPU_SSPP_RECT_0) { ystride0 = (ystride0 & 0xFFFF0000) | @@ -540,8 +532,8 @@ static void dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe *pipe, } } - DPU_REG_WRITE(&ctx->hw, SSPP_SRC_YSTRIDE0 + idx, ystride0); - DPU_REG_WRITE(&ctx->hw, SSPP_SRC_YSTRIDE1 + idx, ystride1); + DPU_REG_WRITE(&ctx->hw, SSPP_SRC_YSTRIDE0, ystride0); + DPU_REG_WRITE(&ctx->hw, SSPP_SRC_YSTRIDE1, ystride1); } static void dpu_hw_sspp_setup_csc(struct dpu_hw_sspp *ctx, @@ -565,9 +557,8 @@ static void dpu_hw_sspp_setup_solidfill(struct dpu_sw_pipe *pipe, u32 color) { struct dpu_hw_sspp *ctx = pipe->sspp; struct dpu_hw_fmt_layout cfg; - u32 idx; - if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx)) + if (!ctx) return; /* cleanup source addresses */ @@ -576,9 +567,9 @@ static void dpu_hw_sspp_setup_solidfill(struct dpu_sw_pipe *pipe, u32 color) if (pipe->multirect_index == DPU_SSPP_RECT_SOLO || pipe->multirect_index == DPU_SSPP_RECT_0) - DPU_REG_WRITE(&ctx->hw, SSPP_SRC_CONSTANT_COLOR + idx, color); + DPU_REG_WRITE(&ctx->hw, SSPP_SRC_CONSTANT_COLOR, color); else - DPU_REG_WRITE(&ctx->hw, SSPP_SRC_CONSTANT_COLOR_REC1 + idx, + DPU_REG_WRITE(&ctx->hw, SSPP_SRC_CONSTANT_COLOR_REC1, color); } @@ -586,39 +577,34 @@ static void dpu_hw_sspp_setup_danger_safe_lut(struct dpu_hw_sspp *ctx, u32 danger_lut, u32 safe_lut) { - u32 idx; - - if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx)) + if (!ctx) return; - DPU_REG_WRITE(&ctx->hw, SSPP_DANGER_LUT + idx, danger_lut); - DPU_REG_WRITE(&ctx->hw, SSPP_SAFE_LUT + idx, safe_lut); + DPU_REG_WRITE(&ctx->hw, SSPP_DANGER_LUT, danger_lut); + DPU_REG_WRITE(&ctx->hw, SSPP_SAFE_LUT, safe_lut); } static void dpu_hw_sspp_setup_creq_lut(struct dpu_hw_sspp *ctx, u64 creq_lut) { - u32 idx; - - if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx)) + if (!ctx) return; if (ctx->cap && test_bit(DPU_SSPP_QOS_8LVL, &ctx->cap->features)) { - DPU_REG_WRITE(&ctx->hw, SSPP_CREQ_LUT_0 + idx, creq_lut); - DPU_REG_WRITE(&ctx->hw, SSPP_CREQ_LUT_1 + idx, + DPU_REG_WRITE(&ctx->hw, SSPP_CREQ_LUT_0, creq_lut); + DPU_REG_WRITE(&ctx->hw, SSPP_CREQ_LUT_1, creq_lut >> 32); } else { - DPU_REG_WRITE(&ctx->hw, SSPP_CREQ_LUT + idx, creq_lut); + DPU_REG_WRITE(&ctx->hw, SSPP_CREQ_LUT, creq_lut); } } static void dpu_hw_sspp_setup_qos_ctrl(struct dpu_hw_sspp *ctx, struct dpu_hw_pipe_qos_cfg *cfg) { - u32 idx; u32 qos_ctrl = 0; - if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx)) + if (!ctx) return; if (cfg->vblank_en) { @@ -634,23 +620,19 @@ static void dpu_hw_sspp_setup_qos_ctrl(struct dpu_hw_sspp *ctx, if (cfg->danger_safe_en) qos_ctrl |= SSPP_QOS_CTRL_DANGER_SAFE_EN; - DPU_REG_WRITE(&ctx->hw, SSPP_QOS_CTRL + idx, qos_ctrl); + DPU_REG_WRITE(&ctx->hw, SSPP_QOS_CTRL, qos_ctrl); } static void dpu_hw_sspp_setup_cdp(struct dpu_sw_pipe *pipe, struct dpu_hw_cdp_cfg *cfg) { struct dpu_hw_sspp *ctx = pipe->sspp; - u32 idx; u32 cdp_cntl = 0; u32 cdp_cntl_offset = 0; if (!ctx || !cfg) return; - if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx)) - return; - if (pipe->multirect_index == DPU_SSPP_RECT_SOLO || pipe->multirect_index == DPU_SSPP_RECT_0) cdp_cntl_offset = SSPP_CDP_CNTL; @@ -672,13 +654,11 @@ static void dpu_hw_sspp_setup_cdp(struct dpu_sw_pipe *pipe, static void _setup_layer_ops(struct dpu_hw_sspp *c, unsigned long features) { - if (test_bit(DPU_SSPP_SRC, &features)) { - c->ops.setup_format = dpu_hw_sspp_setup_format; - c->ops.setup_rects = dpu_hw_sspp_setup_rects; - c->ops.setup_sourceaddress = dpu_hw_sspp_setup_sourceaddress; - c->ops.setup_solidfill = dpu_hw_sspp_setup_solidfill; - c->ops.setup_pe = dpu_hw_sspp_setup_pe_config; - } + c->ops.setup_format = dpu_hw_sspp_setup_format; + c->ops.setup_rects = dpu_hw_sspp_setup_rects; + c->ops.setup_sourceaddress = dpu_hw_sspp_setup_sourceaddress; + c->ops.setup_solidfill = dpu_hw_sspp_setup_solidfill; + c->ops.setup_pe = dpu_hw_sspp_setup_pe_config; if (test_bit(DPU_SSPP_QOS, &features)) { c->ops.setup_danger_safe_lut = @@ -728,8 +708,8 @@ int _dpu_hw_sspp_init_debugfs(struct dpu_hw_sspp *hw_pipe, struct dpu_kms *kms, /* add register dump support */ dpu_debugfs_create_regset32("src_blk", 0400, debugfs_root, - sblk->src_blk.base + cfg->base, - sblk->src_blk.len, + cfg->base, + cfg->len, kms); if (cfg->features & BIT(DPU_SSPP_SCALER_QSEED3) || From patchwork Sat Apr 29 01:23:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 677896 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 59112C77B61 for ; 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Fri, 28 Apr 2023 18:23:56 -0700 (PDT) Received: from eriador.lumag.spb.ru ([212.140.138.218]) by smtp.gmail.com with ESMTPSA id p10-20020a5d48ca000000b003047dc162f7sm12983554wrs.67.2023.04.28.18.23.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Apr 2023 18:23:55 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Abhinav Kumar Cc: Stephen Boyd , David Airlie , Daniel Vetter , Bjorn Andersson , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Jeykumar Sankaran Subject: [PATCH v2 2/3] drm/msm/dpu: access QSEED registers directly Date: Sat, 29 Apr 2023 04:23:52 +0300 Message-Id: <20230429012353.2569481-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230429012353.2569481-1-dmitry.baryshkov@linaro.org> References: <20230429012353.2569481-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Stop using _sspp_subblk_offset() to get offset of the scaler_blk. Inline this function and use ctx->cap->sblk->scaler_blk.base directly. Reviewed-by: Jeykumar Sankaran Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 27 +++++++-------------- 1 file changed, 9 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c index 83a091f978e2..37cd5f4396c6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c @@ -149,11 +149,6 @@ static int _sspp_subblk_offset(struct dpu_hw_sspp *ctx, sblk = ctx->cap->sblk; switch (s_id) { - case DPU_SSPP_SCALER_QSEED2: - case DPU_SSPP_SCALER_QSEED3: - case DPU_SSPP_SCALER_RGB: - *idx = sblk->scaler_blk.base; - break; case DPU_SSPP_CSC: case DPU_SSPP_CSC_10BIT: *idx = sblk->csc_blk.base; @@ -195,22 +190,21 @@ static void dpu_hw_sspp_setup_multirect(struct dpu_sw_pipe *pipe) static void _sspp_setup_opmode(struct dpu_hw_sspp *ctx, u32 mask, u8 en) { - u32 idx; + const struct dpu_sspp_sub_blks *sblk = ctx->cap->sblk; u32 opmode; if (!test_bit(DPU_SSPP_SCALER_QSEED2, &ctx->cap->features) || - _sspp_subblk_offset(ctx, DPU_SSPP_SCALER_QSEED2, &idx) || !test_bit(DPU_SSPP_CSC, &ctx->cap->features)) return; - opmode = DPU_REG_READ(&ctx->hw, SSPP_VIG_OP_MODE + idx); + opmode = DPU_REG_READ(&ctx->hw, sblk->scaler_blk.base + SSPP_VIG_OP_MODE); if (en) opmode |= mask; else opmode &= ~mask; - DPU_REG_WRITE(&ctx->hw, SSPP_VIG_OP_MODE + idx, opmode); + DPU_REG_WRITE(&ctx->hw, sblk->scaler_blk.base + SSPP_VIG_OP_MODE, opmode); } static void _sspp_setup_csc10_opmode(struct dpu_hw_sspp *ctx, @@ -416,25 +410,22 @@ static void _dpu_hw_sspp_setup_scaler3(struct dpu_hw_sspp *ctx, struct dpu_hw_scaler3_cfg *scaler3_cfg, const struct dpu_format *format) { - u32 idx; - - if (_sspp_subblk_offset(ctx, DPU_SSPP_SCALER_QSEED3, &idx) - || !scaler3_cfg) + if (!ctx || !scaler3_cfg) return; - dpu_hw_setup_scaler3(&ctx->hw, scaler3_cfg, idx, + dpu_hw_setup_scaler3(&ctx->hw, scaler3_cfg, + ctx->cap->sblk->scaler_blk.base, ctx->cap->sblk->scaler_blk.version, format); } static u32 _dpu_hw_sspp_get_scaler3_ver(struct dpu_hw_sspp *ctx) { - u32 idx; - - if (!ctx || _sspp_subblk_offset(ctx, DPU_SSPP_SCALER_QSEED3, &idx)) + if (!ctx) return 0; - return dpu_hw_get_scaler3_ver(&ctx->hw, idx); + return dpu_hw_get_scaler3_ver(&ctx->hw, + ctx->cap->sblk->scaler_blk.base); } /* From patchwork Sat Apr 29 01:23:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 677895 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 79FF6C7EE23 for ; Sat, 29 Apr 2023 01:24:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347161AbjD2BYD (ORCPT ); Fri, 28 Apr 2023 21:24:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39042 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347257AbjD2BYA (ORCPT ); Fri, 28 Apr 2023 21:24:00 -0400 Received: from mail-wm1-x329.google.com (mail-wm1-x329.google.com [IPv6:2a00:1450:4864:20::329]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C9B0540F0 for ; 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Inline this function and use ctx->cap->sblk->csc_blk.base directly. As this was the last user, drop _sspp_subblk_offset() too. Reviewed-by: Jeykumar Sankaran Signed-off-by: Dmitry Baryshkov Reviewed-by: Marijn Suijten --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 43 +++++---------------- 1 file changed, 9 insertions(+), 34 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c index 37cd5f4396c6..fd9714659293 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c @@ -136,30 +136,6 @@ #define TS_CLK 19200000 -static int _sspp_subblk_offset(struct dpu_hw_sspp *ctx, - int s_id, - u32 *idx) -{ - int rc = 0; - const struct dpu_sspp_sub_blks *sblk; - - if (!ctx || !ctx->cap || !ctx->cap->sblk) - return -EINVAL; - - sblk = ctx->cap->sblk; - - switch (s_id) { - case DPU_SSPP_CSC: - case DPU_SSPP_CSC_10BIT: - *idx = sblk->csc_blk.base; - break; - default: - rc = -EINVAL; - } - - return rc; -} - static void dpu_hw_sspp_setup_multirect(struct dpu_sw_pipe *pipe) { struct dpu_hw_sspp *ctx = pipe->sspp; @@ -210,19 +186,16 @@ static void _sspp_setup_opmode(struct dpu_hw_sspp *ctx, static void _sspp_setup_csc10_opmode(struct dpu_hw_sspp *ctx, u32 mask, u8 en) { - u32 idx; + const struct dpu_sspp_sub_blks *sblk = ctx->cap->sblk; u32 opmode; - if (_sspp_subblk_offset(ctx, DPU_SSPP_CSC_10BIT, &idx)) - return; - - opmode = DPU_REG_READ(&ctx->hw, SSPP_VIG_CSC_10_OP_MODE + idx); + opmode = DPU_REG_READ(&ctx->hw, sblk->csc_blk.base + SSPP_VIG_CSC_10_OP_MODE); if (en) opmode |= mask; else opmode &= ~mask; - DPU_REG_WRITE(&ctx->hw, SSPP_VIG_CSC_10_OP_MODE + idx, opmode); + DPU_REG_WRITE(&ctx->hw, sblk->csc_blk.base + SSPP_VIG_CSC_10_OP_MODE, opmode); } /* @@ -530,18 +503,20 @@ static void dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe *pipe, static void dpu_hw_sspp_setup_csc(struct dpu_hw_sspp *ctx, const struct dpu_csc_cfg *data) { - u32 idx; + u32 offset; bool csc10 = false; - if (_sspp_subblk_offset(ctx, DPU_SSPP_CSC, &idx) || !data) + if (!ctx || !data) return; + offset = ctx->cap->sblk->csc_blk.base; + if (test_bit(DPU_SSPP_CSC_10BIT, &ctx->cap->features)) { - idx += CSC_10BIT_OFFSET; + offset += CSC_10BIT_OFFSET; csc10 = true; } - dpu_hw_csc_setup(&ctx->hw, idx, data, csc10); + dpu_hw_csc_setup(&ctx->hw, offset, data, csc10); } static void dpu_hw_sspp_setup_solidfill(struct dpu_sw_pipe *pipe, u32 color)