From patchwork Mon Apr 24 09:38:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bhavya Kapoor X-Patchwork-Id: 677362 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9EB56C77B61 for ; Mon, 24 Apr 2023 09:38:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230430AbjDXJit (ORCPT ); Mon, 24 Apr 2023 05:38:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36768 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230072AbjDXJis (ORCPT ); Mon, 24 Apr 2023 05:38:48 -0400 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0E6661729; Mon, 24 Apr 2023 02:38:41 -0700 (PDT) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 33O9cTsN058073; Mon, 24 Apr 2023 04:38:29 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1682329109; bh=ITVPUVnnfgkGMB3knFuO7Z6qcBUOl6T8Xv3HE/MDZC8=; h=From:To:CC:Subject:Date; b=rm1SUf/Uc57XAQaYZkLO4dg9yyUMKGOj4OIMftizY0eQ3/Dfd/7d2G1m6/V5fOZEq 43jLkgA/wu9/9JLW6IwJHYhAYI9vw2wR7iJY82MnnwMSiToX8Nwb6Uu4pgWPyyoNar w6jH/zCCatCFYkg/RlzpkEuHAXGgcSQRhrK09Was= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 33O9cTYO023889 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 24 Apr 2023 04:38:29 -0500 Received: from DFLE104.ent.ti.com (10.64.6.25) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Mon, 24 Apr 2023 04:38:28 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Mon, 24 Apr 2023 04:38:28 -0500 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 33O9cROk023312; Mon, 24 Apr 2023 04:38:28 -0500 From: Bhavya Kapoor To: , CC: , , , , , , Subject: [PATCH] arm64: dts: ti: k3-j721e-main: Update delay select values for MMC subsystems Date: Mon, 24 Apr 2023 15:08:27 +0530 Message-ID: <20230424093827.1378602-1-b-kapoor@ti.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Update the delay values for various speed modes supported, based on the revised august 2021 J721E Datasheet. [1] - Table 7-77. MMC0 DLL Delay Mapping for All Timing Modes and Table 7-86. MMC1/2 DLL Delay Mapping for All Timing Modes, in https://www.ti.com/lit/ds/symlink/tda4vm.pdf, (SPRSP36J – FEBRUARY 2019 – REVISED AUGUST 2021) Signed-off-by: Bhavya Kapoor --- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index 10c8a5fb4ee2..c249cc3d1fba 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -1287,8 +1287,8 @@ main_sdhci0: mmc@4f80000 { bus-width = <8>; mmc-hs200-1_8v; mmc-ddr-1_8v; - ti,otap-del-sel-legacy = <0xf>; - ti,otap-del-sel-mmc-hs = <0xf>; + ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-mmc-hs = <0x0>; ti,otap-del-sel-ddr52 = <0x5>; ti,otap-del-sel-hs200 = <0x6>; ti,otap-del-sel-hs400 = <0x0>; @@ -1309,11 +1309,12 @@ main_sdhci1: mmc@4fb0000 { assigned-clocks = <&k3_clks 92 0>; assigned-clock-parents = <&k3_clks 92 1>; ti,otap-del-sel-legacy = <0x0>; - ti,otap-del-sel-sd-hs = <0xf>; + ti,otap-del-sel-sd-hs = <0x0>; ti,otap-del-sel-sdr12 = <0xf>; ti,otap-del-sel-sdr25 = <0xf>; ti,otap-del-sel-sdr50 = <0xc>; ti,otap-del-sel-ddr50 = <0xc>; + ti,otap-del-sel-sdr104 = <0x5>; ti,itap-del-sel-legacy = <0x0>; ti,itap-del-sel-sd-hs = <0x0>; ti,itap-del-sel-sdr12 = <0x0>; @@ -1335,11 +1336,12 @@ main_sdhci2: mmc@4f98000 { assigned-clocks = <&k3_clks 93 0>; assigned-clock-parents = <&k3_clks 93 1>; ti,otap-del-sel-legacy = <0x0>; - ti,otap-del-sel-sd-hs = <0xf>; + ti,otap-del-sel-sd-hs = <0x0>; ti,otap-del-sel-sdr12 = <0xf>; ti,otap-del-sel-sdr25 = <0xf>; ti,otap-del-sel-sdr50 = <0xc>; ti,otap-del-sel-ddr50 = <0xc>; + ti,otap-del-sel-sdr104 = <0x5>; ti,itap-del-sel-legacy = <0x0>; ti,itap-del-sel-sd-hs = <0x0>; ti,itap-del-sel-sdr12 = <0x0>;