From patchwork Mon Apr 24 16:10:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 677317 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 870DCC7618E for ; Mon, 24 Apr 2023 16:10:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231415AbjDXQKu (ORCPT ); Mon, 24 Apr 2023 12:10:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38670 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232176AbjDXQKr (ORCPT ); Mon, 24 Apr 2023 12:10:47 -0400 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id D9BAC76BC; Mon, 24 Apr 2023 09:10:43 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.99,223,1677510000"; d="scan'208";a="160553205" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 25 Apr 2023 01:10:43 +0900 Received: from localhost.localdomain (unknown [10.226.92.191]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id B24244007F5A; Tue, 25 Apr 2023 01:10:39 +0900 (JST) From: Biju Das To: David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski Cc: Biju Das , Laurent Pinchart , dri-devel@lists.freedesktop.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, Geert Uytterhoeven , Fabrizio Castro , Prabhakar Mahadev Lad , Rob Herring Subject: [PATCH v8 2/5] dt-bindings: display: Document Renesas RZ/G2L DU bindings Date: Mon, 24 Apr 2023 17:10:21 +0100 Message-Id: <20230424161024.136316-3-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230424161024.136316-1-biju.das.jz@bp.renesas.com> References: <20230424161024.136316-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The RZ/G2L LCD controller is composed of Frame Compression Processor (FCPVD), Video Signal Processor (VSPD), and Display Unit (DU). The DU module supports the following hardware features − Display Parallel Interface (DPI) and MIPI LINK Video Interface − Display timing master − Generates video timings − Selecting the polarity of output DCLK, HSYNC, VSYNC, and DE − Supports Progressive − Input data format (from VSPD): RGB888, RGB666 − Output data format: same as Input data format − Supporting Full HD (1920 pixels x 1080 lines) for MIPI-DSI Output − Supporting WXGA (1280 pixels x 800 lines) for Parallel Output This patch document DU module found on RZ/G2L LCDC. Signed-off-by: Biju Das Reviewed-by: Rob Herring --- v7->v8: * No change v6->v7: * No change v5->v6: * No change. v4->v5: * Added Rb tag from Rob. v3->v4: * Changed compatible name from renesas,du-r9a07g044->renesas,r9a07g044-du * started using same compatible for RZ/G2{L,LC} v3: New patch --- .../bindings/display/renesas,rzg2l-du.yaml | 124 ++++++++++++++++++ 1 file changed, 124 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml diff --git a/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml new file mode 100644 index 000000000000..ab99e7d57a7d --- /dev/null +++ b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml @@ -0,0 +1,124 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/renesas,rzg2l-du.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/G2L Display Unit (DU) + +maintainers: + - Biju Das + - Laurent Pinchart + +description: | + These DT bindings describe the Display Unit embedded in the Renesas RZ/G2L + and RZ/V2L SoCs. + +properties: + compatible: + enum: + - renesas,r9a07g044-du # RZ/G2{L,LC} + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: Main clock + - description: Register access clock + - description: Video clock + + clock-names: + items: + - const: aclk + - const: pclk + - const: vclk + + resets: + maxItems: 1 + + power-domains: + maxItems: 1 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + description: | + The connections to the DU output video ports are modeled using the OF + graph bindings specified in Documentation/devicetree/bindings/graph.txt. + The number of ports and their assignment are model-dependent. Each port + shall have a single endpoint. + + patternProperties: + "^port@[0-1]$": + $ref: /schemas/graph.yaml#/properties/port + unevaluatedProperties: false + + required: + - port@0 + + unevaluatedProperties: false + + renesas,vsps: + $ref: "/schemas/types.yaml#/definitions/phandle-array" + items: + items: + - description: phandle to VSP instance that serves the DU channel + - description: Channel index identifying the LIF instance in that VSP + description: + A list of phandle and channel index tuples to the VSPs that handle the + memory interfaces for the DU channels. + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - resets + - power-domains + - ports + - renesas,vsps + +additionalProperties: false + +examples: + # RZ/G2L DU + - | + #include + #include + + display@10890000 { + compatible = "renesas,r9a07g044-du"; + reg = <0x10890000 0x10000>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G044_LCDC_CLK_A>, + <&cpg CPG_MOD R9A07G044_LCDC_CLK_P>, + <&cpg CPG_MOD R9A07G044_LCDC_CLK_D>; + clock-names = "aclk", "pclk", "vclk"; + resets = <&cpg R9A07G044_LCDC_RESET_N>; + power-domains = <&cpg>; + + renesas,vsps = <&vspd0 0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + port@1 { + reg = <1>; + endpoint { + }; + }; + }; + }; + +... From patchwork Mon Apr 24 16:10:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 676666 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A95EEC77B78 for ; Mon, 24 Apr 2023 16:10:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230462AbjDXQKx (ORCPT ); Mon, 24 Apr 2023 12:10:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38754 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231799AbjDXQKw (ORCPT ); Mon, 24 Apr 2023 12:10:52 -0400 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 8C15A7ED7; Mon, 24 Apr 2023 09:10:48 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.99,223,1677510000"; d="scan'208";a="160553213" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 25 Apr 2023 01:10:47 +0900 Received: from localhost.localdomain (unknown [10.226.92.191]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 278FE4007F5A; Tue, 25 Apr 2023 01:10:43 +0900 (JST) From: Biju Das To: David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski Cc: Biju Das , Laurent Pinchart , dri-devel@lists.freedesktop.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, Geert Uytterhoeven , Fabrizio Castro , Prabhakar Mahadev Lad , Rob Herring Subject: [PATCH v8 3/5] dt-bindings: display: renesas,rzg2l-du: Document RZ/V2L DU bindings Date: Mon, 24 Apr 2023 17:10:22 +0100 Message-Id: <20230424161024.136316-4-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230424161024.136316-1-biju.das.jz@bp.renesas.com> References: <20230424161024.136316-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Document DU found in RZ/V2L SoC. The DU block is identical to RZ/G2L SoC and therefore use RZ/G2L fallback to avoid any driver changes. Signed-off-by: Biju Das Reviewed-by: Rob Herring Reviewed-by: Geert Uytterhoeven --- v7->v8: * Fixed the typo vsp2->du * Added Rb tag from Rob as the change is trivial. v7: * New patch. --- .../devicetree/bindings/display/renesas,rzg2l-du.yaml | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml index ab99e7d57a7d..98686ea84d53 100644 --- a/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml +++ b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml @@ -16,8 +16,13 @@ description: | properties: compatible: - enum: - - renesas,r9a07g044-du # RZ/G2{L,LC} + oneOf: + - enum: + - renesas,r9a07g044-du # RZ/G2{L,LC} + - items: + - enum: + - renesas,r9a07g054-du # RZ/V2L + - const: renesas,r9a07g044-du # RZ/G2L fallback reg: maxItems: 1