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[92.34.216.5]) by smtp.gmail.com with ESMTPSA id x14-20020a19f60e000000b004edd3b34e78sm1552225lfe.147.2023.04.24.00.38.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Apr 2023 00:38:40 -0700 (PDT) From: Linus Walleij To: u-boot@lists.denx.de, Tom Rini , Michael Nazzareno Trimarchi , William Zhang , Heinrich Schuchardt Cc: Anand Gore , Kursad Oney , Joel Peshkin , Philippe Reynes , =?utf-8?b?UmFmYcWCIE1p?= =?utf-8?b?xYJlY2tp?= , Linus Walleij Subject: [PATCH v5 1/3] arm: dts: Import device tree for Broadcom Northstar Date: Mon, 24 Apr 2023 09:38:28 +0200 Message-Id: <20230424073830.234710-2-linus.walleij@linaro.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230424073830.234710-1-linus.walleij@linaro.org> References: <20230424073830.234710-1-linus.walleij@linaro.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean This brings in the main SoC device tree used by the Broadcom Northstar chipset, i.e. BCM4709x and BCM5301x. This is taken from the v6.3 Linux kernel. Cc: Rafał Miłecki Signed-off-by: Linus Walleij --- ChangeLog v4->v5: - Rebase on the U-Boot master branch ChangeLog v3->v4: - No changes ChangeLog v1->v3: - Bundle with the iproc nand and algo select patches --- arch/arm/dts/bcm5301x.dtsi | 581 ++++++++++++++++++++++++++++ include/dt-bindings/clock/bcm-nsp.h | 51 +++ 2 files changed, 632 insertions(+) create mode 100644 arch/arm/dts/bcm5301x.dtsi create mode 100644 include/dt-bindings/clock/bcm-nsp.h diff --git a/arch/arm/dts/bcm5301x.dtsi b/arch/arm/dts/bcm5301x.dtsi new file mode 100644 index 000000000000..5fc1b847f4aa --- /dev/null +++ b/arch/arm/dts/bcm5301x.dtsi @@ -0,0 +1,581 @@ +/* + * Broadcom BCM470X / BCM5301X ARM platform code. + * Generic DTS part for all BCM53010, BCM53011, BCM53012, BCM53014, BCM53015, + * BCM53016, BCM53017, BCM53018, BCM4707, BCM4708 and BCM4709 SoCs + * + * Copyright 2013-2014 Hauke Mehrtens + * + * Licensed under the GNU/GPL. See COPYING for details. + */ + +#include +#include +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + + chipcommon-a-bus@18000000 { + compatible = "simple-bus"; + ranges = <0x00000000 0x18000000 0x00001000>; + #address-cells = <1>; + #size-cells = <1>; + + uart0: serial@300 { + compatible = "ns16550"; + reg = <0x0300 0x100>; + interrupts = ; + clocks = <&iprocslow>; + status = "disabled"; + }; + + uart1: serial@400 { + compatible = "ns16550"; + reg = <0x0400 0x100>; + interrupts = ; + clocks = <&iprocslow>; + pinctrl-names = "default"; + pinctrl-0 = <&pinmux_uart1>; + status = "disabled"; + }; + }; + + mpcore-bus@19000000 { + compatible = "simple-bus"; + ranges = <0x00000000 0x19000000 0x00023000>; + #address-cells = <1>; + #size-cells = <1>; + + a9pll: arm_clk@0 { + #clock-cells = <0>; + compatible = "brcm,nsp-armpll"; + clocks = <&osc>; + reg = <0x00000 0x1000>; + }; + + scu@20000 { + compatible = "arm,cortex-a9-scu"; + reg = <0x20000 0x100>; + }; + + timer@20200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0x20200 0x100>; + interrupts = ; + clocks = <&periph_clk>; + }; + + timer@20600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x20600 0x20>; + interrupts = ; + clocks = <&periph_clk>; + }; + + watchdog@20620 { + compatible = "arm,cortex-a9-twd-wdt"; + reg = <0x20620 0x20>; + interrupts = ; + clocks = <&periph_clk>; + }; + + gic: interrupt-controller@21000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x21000 0x1000>, + <0x20100 0x100>; + }; + + L2: cache-controller@22000 { + compatible = "arm,pl310-cache"; + reg = <0x22000 0x1000>; + cache-unified; + arm,shared-override; + prefetch-data = <1>; + prefetch-instr = <1>; + cache-level = <2>; + }; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = + , + ; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + osc: oscillator { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + }; + + iprocmed: iprocmed { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>; + clock-div = <2>; + clock-mult = <1>; + }; + + iprocslow: iprocslow { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>; + clock-div = <4>; + clock-mult = <1>; + }; + + periph_clk: periph_clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&a9pll>; + clock-div = <2>; + clock-mult = <1>; + }; + }; + + axi@18000000 { + compatible = "brcm,bus-axi"; + reg = <0x18000000 0x1000>; + ranges = <0x00000000 0x18000000 0x00100000>; + #address-cells = <1>; + #size-cells = <1>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0x000fffff 0xffff>; + interrupt-map = + /* ChipCommon */ + <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, + + /* Switch Register Access Block */ + <0x00007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 4 &gic GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 5 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 6 &gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 7 &gic GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 8 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 9 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 10 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 11 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 12 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, + + /* PCIe Controller 0 */ + <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, + <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, + <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, + <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + + /* PCIe Controller 1 */ + <0x00013000 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, + <0x00013000 1 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, + <0x00013000 2 &gic GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, + <0x00013000 3 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <0x00013000 4 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <0x00013000 5 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, + + /* PCIe Controller 2 */ + <0x00014000 0 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <0x00014000 1 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <0x00014000 2 &gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, + <0x00014000 3 &gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, + <0x00014000 4 &gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <0x00014000 5 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, + + /* USB 2.0 Controller */ + <0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, + + /* USB 3.0 Controller */ + <0x00023000 0 &gic GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, + + /* Ethernet Controller 0 */ + <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + + /* Ethernet Controller 1 */ + <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + + /* Ethernet Controller 2 */ + <0x00026000 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + + /* Ethernet Controller 3 */ + <0x00027000 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + + /* NAND Controller */ + <0x00028000 0 &gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, + <0x00028000 1 &gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, + <0x00028000 2 &gic GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, + <0x00028000 3 &gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, + <0x00028000 4 &gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, + <0x00028000 5 &gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, + <0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, + <0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + + chipcommon: chipcommon@0 { + reg = <0x00000000 0x1000>; + + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pcie0: pcie@12000 { + reg = <0x00012000 0x1000>; + }; + + pcie1: pcie@13000 { + reg = <0x00013000 0x1000>; + }; + + pcie2: pcie@14000 { + reg = <0x00014000 0x1000>; + }; + + usb2: usb2@21000 { + reg = <0x00021000 0x1000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + interrupt-parent = <&gic>; + + ehci: usb@21000 { + #usb-cells = <0>; + + compatible = "generic-ehci"; + reg = <0x00021000 0x1000>; + interrupts = ; + phys = <&usb2_phy>; + + #address-cells = <1>; + #size-cells = <0>; + + ehci_port1: port@1 { + reg = <1>; + #trigger-source-cells = <0>; + }; + + ehci_port2: port@2 { + reg = <2>; + #trigger-source-cells = <0>; + }; + }; + + ohci: usb@22000 { + #usb-cells = <0>; + + compatible = "generic-ohci"; + reg = <0x00022000 0x1000>; + interrupts = ; + + #address-cells = <1>; + #size-cells = <0>; + + ohci_port1: port@1 { + reg = <1>; + #trigger-source-cells = <0>; + }; + + ohci_port2: port@2 { + reg = <2>; + #trigger-source-cells = <0>; + }; + }; + }; + + usb3: usb3@23000 { + reg = <0x00023000 0x1000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + interrupt-parent = <&gic>; + + xhci: usb@23000 { + #usb-cells = <0>; + + compatible = "generic-xhci"; + reg = <0x00023000 0x1000>; + interrupts = ; + phys = <&usb3_phy>; + phy-names = "usb"; + + #address-cells = <1>; + #size-cells = <0>; + + xhci_port1: port@1 { + reg = <1>; + #trigger-source-cells = <0>; + }; + }; + }; + + gmac0: ethernet@24000 { + reg = <0x24000 0x800>; + }; + + gmac1: ethernet@25000 { + reg = <0x25000 0x800>; + }; + + gmac2: ethernet@26000 { + reg = <0x26000 0x800>; + }; + + gmac3: ethernet@27000 { + reg = <0x27000 0x800>; + }; + }; + + pwm: pwm@18002000 { + compatible = "brcm,iproc-pwm"; + reg = <0x18002000 0x28>; + clocks = <&osc>; + #pwm-cells = <3>; + status = "disabled"; + }; + + mdio: mdio@18003000 { + compatible = "brcm,iproc-mdio"; + reg = <0x18003000 0x8>; + #size-cells = <0>; + #address-cells = <1>; + }; + + mdio-mux@18003000 { + compatible = "mdio-mux-mmioreg", "mdio-mux"; + mdio-parent-bus = <&mdio>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x18003000 0x4>; + mux-mask = <0x200>; + + mdio@0 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + + usb3_phy: usb3-phy@10 { + compatible = "brcm,ns-ax-usb3-phy"; + reg = <0x10>; + usb3-dmp-syscon = <&usb3_dmp>; + #phy-cells = <0>; + status = "disabled"; + }; + }; + }; + + usb3_dmp: syscon@18105000 { + reg = <0x18105000 0x1000>; + }; + + uart2: serial@18008000 { + compatible = "ns16550a"; + reg = <0x18008000 0x20>; + clocks = <&iprocslow>; + interrupts = ; + reg-shift = <2>; + status = "disabled"; + }; + + i2c0: i2c@18009000 { + compatible = "brcm,iproc-i2c"; + reg = <0x18009000 0x50>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + status = "disabled"; + }; + + dmu-bus@1800c000 { + compatible = "simple-bus"; + ranges = <0 0x1800c000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + cru-bus@100 { + compatible = "brcm,ns-cru", "simple-mfd"; + reg = <0x100 0x1a4>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + + lcpll0: clock-controller@100 { + #clock-cells = <1>; + compatible = "brcm,nsp-lcpll0"; + reg = <0x100 0x14>; + clocks = <&osc>; + clock-output-names = "lcpll0", "pcie_phy", + "sdio", "ddr_phy"; + }; + + genpll: clock-controller@140 { + #clock-cells = <1>; + compatible = "brcm,nsp-genpll"; + reg = <0x140 0x24>; + clocks = <&osc>; + clock-output-names = "genpll", "phy", + "ethernetclk", + "usbclk", "iprocfast", + "sata1", "sata2"; + }; + + usb2_phy: phy@164 { + compatible = "brcm,ns-usb2-phy"; + reg = <0x164 0x4>; + brcm,syscon-clkset = <&cru_clkset>; + clocks = <&genpll BCM_NSP_GENPLL_USB_PHY_REF_CLK>; + clock-names = "phy-ref-clk"; + #phy-cells = <0>; + }; + + cru_clkset: syscon@180 { + compatible = "brcm,cru-clkset", "syscon"; + reg = <0x180 0x4>; + }; + + pinctrl: pinctrl@1c0 { + compatible = "brcm,bcm4708-pinmux"; + reg = <0x1c0 0x24>; + reg-names = "cru_gpio_control"; + + spi-pins { + groups = "spi_grp"; + function = "spi"; + }; + + pinmux_i2c: i2c-pins { + groups = "i2c_grp"; + function = "i2c"; + }; + + pinmux_pwm: pwm-pins { + groups = "pwm0_grp", "pwm1_grp", + "pwm2_grp", "pwm3_grp"; + function = "pwm"; + }; + + pinmux_uart1: uart1-pins { + groups = "uart1_grp"; + function = "uart1"; + }; + }; + + thermal: thermal@2c0 { + compatible = "brcm,ns-thermal"; + reg = <0x2c0 0x10>; + #thermal-sensor-cells = <0>; + }; + }; + }; + + srab: ethernet-switch@18007000 { + compatible = "brcm,bcm53011-srab", "brcm,bcm5301x-srab"; + reg = <0x18007000 0x1000>; + + status = "disabled"; + + /* ports are defined in board DTS */ + ports { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + rng: rng@18004000 { + compatible = "brcm,bcm5301x-rng"; + reg = <0x18004000 0x14>; + }; + + nand_controller: nand-controller@18028000 { + compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand"; + reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>; + reg-names = "nand", "iproc-idm", "iproc-ext"; + interrupts = ; + + #address-cells = <1>; + #size-cells = <0>; + + brcm,nand-has-wp; + }; + + spi@18029200 { + compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi"; + reg = <0x18029200 0x184>, + <0x18029000 0x124>, + <0x1811b408 0x004>, + <0x180293a0 0x01c>; + reg-names = "mspi", "bspi", "intr_regs", "intr_status_reg"; + interrupts = , + , + , + , + , + , + ; + interrupt-names = "mspi_done", + "mspi_halted", + "spi_lr_fullness_reached", + "spi_lr_session_aborted", + "spi_lr_impatient", + "spi_lr_session_done", + "spi_lr_overread"; + clocks = <&iprocmed>; + clock-names = "iprocmed"; + num-cs = <2>; + #address-cells = <1>; + #size-cells = <0>; + + spi_nor: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <20000000>; + status = "disabled"; + + partitions { + compatible = "brcm,bcm947xx-cfe-partitions"; + }; + }; + }; + + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <0>; + polling-delay = <1000>; + coefficients = <(-556) 418000>; + thermal-sensors = <&thermal>; + + trips { + cpu-crit { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + }; + }; + }; +}; diff --git a/include/dt-bindings/clock/bcm-nsp.h b/include/dt-bindings/clock/bcm-nsp.h new file mode 100644 index 000000000000..ad5827cde782 --- /dev/null +++ b/include/dt-bindings/clock/bcm-nsp.h @@ -0,0 +1,51 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2015 Broadcom Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Broadcom Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _CLOCK_BCM_NSP_H +#define _CLOCK_BCM_NSP_H + +/* GENPLL clock channel ID */ +#define BCM_NSP_GENPLL 0 +#define BCM_NSP_GENPLL_PHY_CLK 1 +#define BCM_NSP_GENPLL_ENET_SW_CLK 2 +#define BCM_NSP_GENPLL_USB_PHY_REF_CLK 3 +#define BCM_NSP_GENPLL_IPROCFAST_CLK 4 +#define BCM_NSP_GENPLL_SATA1_CLK 5 +#define BCM_NSP_GENPLL_SATA2_CLK 6 + +/* LCPLL0 clock channel ID */ +#define BCM_NSP_LCPLL0 0 +#define BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK 1 +#define BCM_NSP_LCPLL0_SDIO_CLK 2 +#define BCM_NSP_LCPLL0_DDR_PHY_CLK 3 + +#endif /* _CLOCK_BCM_NSP_H */ From patchwork Mon Apr 24 07:38:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 676550 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a41:0:0:0:0:0 with SMTP id v1csp2020010wrs; Mon, 24 Apr 2023 00:39:18 -0700 (PDT) X-Google-Smtp-Source: AKy350ZUhuagujT8Uw+wUsqi3qCg4DoyFJ6c13+DaGJQ9ufH4svtWSLBoKU4x6SZlVTPD3Fc9sfX X-Received: by 2002:a17:902:ce8f:b0:1a6:4fbd:d5c0 with SMTP id f15-20020a170902ce8f00b001a64fbdd5c0mr15773030plg.53.1682321957936; Mon, 24 Apr 2023 00:39:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1682321957; cv=none; d=google.com; s=arc-20160816; b=uvIa/GQd/B2EHJ7l4W0O/LROUBerFVlo7pfNAhUZb5+Ac/QEEhltzEq2WERKT490WP 4t/IWdk59sK4nd0A9E3QgtDuvMIJgZaNjbvNOm154KbkMrYC/zcVUrPwMOBnmya7EazD tMhlawHkArvzAwYFU5/k4tRhHwQwe3q+Wlho3anIAgJ0HWvZXHRFS5e4YsOrH5yG4Fry agPNcUHeD6JBfKMk6UeD5JpQEaNPIQHLgZx2EzcgmJq6v8E6Xb3632a+hqINOLyBx3Lm KO6MONnaV7YUmSLglmsAmUI9RWNB9GUZaE82xyRNvgZ4guW1qw3v7fOBmX7kZqDmeBrE F0+Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=rk8Umds742x5iJgm/g/7zDfbMEmCCrG4qBDVTRUofE0=; b=XEucH/f9ogmkD+r8pnwByFZwKhbT5iDWhVmc45WU6XSrc8wuejODX2lruBMNVZdog3 fmS3TWXvx/Id1kQwdY4H0W5DcD8yqokX7CzO1X3+sAy4vI9qCQWCTW8HBuLzGNGIiVt5 cpj3gW618D7ZBux0rAct+rHctwEhjiaHLb36vxnQsMTXGMMAchFpHV31n8cNdKhDvesN acNSuauDhDpa93wjuzdpOfNGJ++t3Lp0lzUfveUqqRWTNW+y6gdgrZ4US5AKI/60eD6h ENK2+frGpMLzL9U2hM8FpoiF0V8iFpmQHZZJOSp6qH8AlFnV+PVWg6IU4NXZXWQsaF9L 4M6A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="QG/EMzk3"; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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[92.34.216.5]) by smtp.gmail.com with ESMTPSA id x14-20020a19f60e000000b004edd3b34e78sm1552225lfe.147.2023.04.24.00.38.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Apr 2023 00:38:41 -0700 (PDT) From: Linus Walleij To: u-boot@lists.denx.de, Tom Rini , Michael Nazzareno Trimarchi , William Zhang , Heinrich Schuchardt Cc: Anand Gore , Kursad Oney , Joel Peshkin , Philippe Reynes , =?utf-8?b?UmFmYcWCIE1p?= =?utf-8?b?xYJlY2tp?= , Linus Walleij Subject: [PATCH v5 2/3] arm: Add support for the Broadcom Northstar SoCs Date: Mon, 24 Apr 2023 09:38:29 +0200 Message-Id: <20230424073830.234710-3-linus.walleij@linaro.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230424073830.234710-1-linus.walleij@linaro.org> References: <20230424073830.234710-1-linus.walleij@linaro.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean The original Northstar is an ARM SoC series that comprise BCM4709x and BCM5301x and uses a dual-core Cortex A9, the global timer and a few other things. This series should not be confused with North Star Plus (NSP) which is partly supported by U-Boot already. The SoC is well supported by the Linux kernel and OpenWrt as it is used in many routers. Since we currently don't need any chip-specific quirks and can get the system up from just the device tree, a mach-* directory doesn't even need to be added, just some small Kconfig fragments. Cc: Rafał Miłecki Signed-off-by: Linus Walleij --- ChangeLog v4->v5: - Rebase on the U-Boot master branch ChangeLog v3->v4: - No changes ChangeLog v1->v3: - Bundle with the iproc nand and algo select patches --- arch/arm/Kconfig | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f0118e225419..098f654e4bdd 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -357,7 +357,7 @@ config SYS_ARM_ARCH choice prompt "Select the ARM data write cache policy" - default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || RZA1 + default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || TARGET_BCMNS || RZA1 default SYS_ARM_CACHE_WRITEBACK config SYS_ARM_CACHE_WRITEBACK @@ -671,6 +671,25 @@ config TARGET_BCMCYGNUS imply HASH_VERIFY imply NETDEVICES +config TARGET_BCMNS + bool "Support Broadcom Northstar" + select CPU_V7A + select DM + select DM_GPIO + select DM_SERIAL + select OF_CONTROL + select TIMER + select SYS_NS16550 + select ARM_GLOBAL_TIMER + imply SYS_THUMB_BUILD + imply MTD_RAW_NAND + imply NAND_BRCMNAND + imply NAND_BRCMNAND_IPROC + help + Support for Broadcom Northstar SoCs. NS is a dual-core 32-bit + ARMv7 Cortex-A9 SoC family including BCM4708, BCM47094, + BCM5301x etc. + config TARGET_BCMNS2 bool "Support Broadcom Northstar2" select ARM64 From patchwork Mon Apr 24 07:38:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 676551 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a41:0:0:0:0:0 with SMTP id v1csp2020087wrs; Mon, 24 Apr 2023 00:39:31 -0700 (PDT) X-Google-Smtp-Source: AKy350b5s96GJwN9EsvDhjpKauj9nZ4wkLOYPXKnBYECPw1rMn2WGxb69/IbJXZE02V44CWeWN8E X-Received: by 2002:a05:6a00:21ce:b0:633:c311:c70d with SMTP id t14-20020a056a0021ce00b00633c311c70dmr15728422pfj.14.1682321970972; Mon, 24 Apr 2023 00:39:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1682321970; cv=none; d=google.com; s=arc-20160816; b=C3iXzh9/Bko7mGpNBJXsWGcRP56NNSeoeiV9LHNfU9GaIP6TyBXxtMD8DwX+ONssRR s7TZk3kbjzfhGy16RJ+/ADX4+rp1bF30dQHHOGSBgLJ2iER3XHJKrRnficlLd+6U08HS HNwp3P56ZYQ89F7EnbEEXbtJL1u/hgDwL8DM/HFPMKO3qv2PCUKGtg4Ke6IVelkjfBbw ectPGq72aGaEH1mOzy0jghPVLXIbHjJ8IhNMbDhh83pUtSsTgqVa/ucKOPmg2mxGVJLY i/dwvbQm1Ot3FOdxxoyYmyzPkfyyEB2UefSkAO9Lr9HeXmnXRKoOMWHOONyg/X2eJCQb gA1Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=S08ol7rj1Lesi46hwy7PehK7yRPiS7ztljYHXS4AHUk=; b=qOCNq5xJFJL5+LdMyaFs+m0ib/qeTFIKQCxZsk2/hNpUw8GTxsw7orYU251wOJBolr So/gP8gDWCebiKPzauBud3wBwq42WHzESSdPTa9e5YbbwF6wZtFjfaKkg2uLjNKD409j ooVEY35NU6sR+hs1EPpJdoJcCB/D/XeFgdsQmR2oUF1f+mvAKvonS8vjgdBE3C0xqx1l 0pYtfmn8LeemLPYrOCtP6vuH2FtMYOFSbtLzMZuL38J/Wnm9aJeJ3nuEp93pukyDoJrA Gyc1JjCKkjZcVPFYYWhWGS+ufLa8iYMDfw8cs6UzoJsLi2JyYqKdXaj4lfz7BQAHOfBv 0eKA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=LcJ+Fdbb; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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[92.34.216.5]) by smtp.gmail.com with ESMTPSA id x14-20020a19f60e000000b004edd3b34e78sm1552225lfe.147.2023.04.24.00.38.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Apr 2023 00:38:43 -0700 (PDT) From: Linus Walleij To: u-boot@lists.denx.de, Tom Rini , Michael Nazzareno Trimarchi , William Zhang , Heinrich Schuchardt Cc: Anand Gore , Kursad Oney , Joel Peshkin , Philippe Reynes , =?utf-8?b?UmFmYcWCIE1p?= =?utf-8?b?xYJlY2tp?= , Linus Walleij Subject: [PATCH v5 3/3] board: Add new Broadcom Northstar board Date: Mon, 24 Apr 2023 09:38:30 +0200 Message-Id: <20230424073830.234710-4-linus.walleij@linaro.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230424073830.234710-1-linus.walleij@linaro.org> References: <20230424073830.234710-1-linus.walleij@linaro.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean This adds a simple Northstar "BRCMNS" board to be used with the BCM4708x and BCM5301x chips. The main intention is to use this with the D-Link DIR-890L and DIR-885L routers for loading the kernel into RAM from NAND memory using the BCH-1 ECC and using the separately submitted SEAMA load command, so we are currently not adding support for things such as networking. The DTS file is a multiplatform NorthStar board, designed to be usable with several NorthStar designs by avoiding any particulars not related to the operation of U-Boot. If other board need other ECC for example, they need to create a separate DTS file and augment the code, but I don't know if any other users will turn up. Cc: Rafał Miłecki Signed-off-by: Linus Walleij --- ChangeLog v4->v5: - Rebase on the U-Boot master branch - Add some documentation ChangeLog v3->v4: - No changes ChangeLog v1->v3: - Bundle with the iproc nand and algo select patches --- arch/arm/Kconfig | 1 + arch/arm/dts/Makefile | 2 ++ arch/arm/dts/ns-board.dts | 57 ++++++++++++++++++++++++++++++ board/broadcom/bcmns/Kconfig | 12 +++++++ board/broadcom/bcmns/MAINTAINERS | 6 ++++ board/broadcom/bcmns/Makefile | 2 ++ board/broadcom/bcmns/ns.c | 60 ++++++++++++++++++++++++++++++++ configs/bcmns_defconfig | 41 ++++++++++++++++++++++ doc/board/broadcom/index.rst | 1 + doc/board/broadcom/northstar.rst | 44 +++++++++++++++++++++++ include/configs/bcmns.h | 49 ++++++++++++++++++++++++++ 11 files changed, 275 insertions(+) create mode 100644 arch/arm/dts/ns-board.dts create mode 100644 board/broadcom/bcmns/Kconfig create mode 100644 board/broadcom/bcmns/MAINTAINERS create mode 100644 board/broadcom/bcmns/Makefile create mode 100644 board/broadcom/bcmns/ns.c create mode 100644 configs/bcmns_defconfig create mode 100644 doc/board/broadcom/northstar.rst create mode 100644 include/configs/bcmns.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 098f654e4bdd..3f4c708c1a57 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -2287,6 +2287,7 @@ source "board/Marvell/octeontx2/Kconfig" source "board/armltd/vexpress/Kconfig" source "board/armltd/vexpress64/Kconfig" source "board/cortina/presidio-asic/Kconfig" +source "board/broadcom/bcmns/Kconfig" source "board/broadcom/bcmns3/Kconfig" source "board/cavium/thunderx/Kconfig" source "board/eets/pdu001/Kconfig" diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 3385948d22cd..ca03a96156c6 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1200,6 +1200,8 @@ dtb-$(CONFIG_ARCH_BCM283X) += \ bcm2837-rpi-cm3-io3.dtb \ bcm2711-rpi-4-b.dtb +dtb-$(CONFIG_TARGET_BCMNS) += ns-board.dtb + dtb-$(CONFIG_TARGET_BCMNS3) += ns3-board.dtb dtb-$(CONFIG_ARCH_BCMSTB) += bcm7xxx.dtb diff --git a/arch/arm/dts/ns-board.dts b/arch/arm/dts/ns-board.dts new file mode 100644 index 000000000000..bc2a0dd1c961 --- /dev/null +++ b/arch/arm/dts/ns-board.dts @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/dts-v1/; + +#include "bcm5301x.dtsi" + +/ { + /* + * The Northstar does not have a proper fallback compatible, but + * these basic chips will suffice. + */ + model = "Northstar model"; + compatible = "brcm,bcm47094", "brcm,bcm4708"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + + memory { + device_type = "memory"; + reg = <0x00000000 0x08000000>, + <0x88000000 0x08000000>; + }; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + nand-controller@18028000 { + nandcs: nand@0 { + compatible = "brcm,nandcs"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + + /* + * Same as using the bcm5301x-nand-cs0-bch1.dtsi + * include from the Linux kernel. + */ + nand-ecc-algo = "bch"; + nand-ecc-strength = <1>; + nand-ecc-step-size = <512>; + + partitions { + compatible = "brcm,bcm947xx-cfe-partitions"; + }; + }; + }; +}; + +&uart0 { + clock-frequency = <125000000>; + status = "okay"; +}; diff --git a/board/broadcom/bcmns/Kconfig b/board/broadcom/bcmns/Kconfig new file mode 100644 index 000000000000..82f4709e2d2d --- /dev/null +++ b/board/broadcom/bcmns/Kconfig @@ -0,0 +1,12 @@ +if TARGET_BCMNS + +config SYS_BOARD + default "bcmns" + +config SYS_VENDOR + default "broadcom" + +config SYS_CONFIG_NAME + default "bcmns" + +endif diff --git a/board/broadcom/bcmns/MAINTAINERS b/board/broadcom/bcmns/MAINTAINERS new file mode 100644 index 000000000000..fd37c334a5b1 --- /dev/null +++ b/board/broadcom/bcmns/MAINTAINERS @@ -0,0 +1,6 @@ +BCMNS BOARD +M: Linus Walleij +S: Maintained +F: board/broadcom/bcmnsp/ +F: configs/bcmnsp_defconfig +F: include/configs/bcmnsp.h diff --git a/board/broadcom/bcmns/Makefile b/board/broadcom/bcmns/Makefile new file mode 100644 index 000000000000..8a6a8543a90b --- /dev/null +++ b/board/broadcom/bcmns/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +obj-y := ns.o diff --git a/board/broadcom/bcmns/ns.c b/board/broadcom/bcmns/ns.c new file mode 100644 index 000000000000..1249e45af036 --- /dev/null +++ b/board/broadcom/bcmns/ns.c @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Broadcom Northstar generic board set-up code + * Copyright (C) 2023 Linus Walleij + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + return fdtdec_setup_mem_size_base(); +} + +int dram_init_banksize(void) +{ + return fdtdec_setup_memory_banksize(); +} + +int board_late_init(void) +{ + /* LEDs etc can be initialized here */ + return 0; +} + +int board_init(void) +{ + return 0; +} + +void reset_cpu(void) +{ +} + +int print_cpuinfo(void) +{ + printf("BCMNS Northstar SoC\n"); + return 0; +} + +int misc_init_r(void) +{ + return 0; +} + +int ft_board_setup(void *fdt, struct bd_info *bd) +{ + printf("Northstar board setup: DTB at 0x%08lx\n", (ulong)fdt); + return 0; +} + diff --git a/configs/bcmns_defconfig b/configs/bcmns_defconfig new file mode 100644 index 000000000000..02e2fbe3db28 --- /dev/null +++ b/configs/bcmns_defconfig @@ -0,0 +1,41 @@ +CONFIG_ARM=y +CONFIG_TARGET_BCMNS=y +CONFIG_TEXT_BASE=0x00008000 +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_DEFAULT_DEVICE_TREE="ns-board" +CONFIG_IDENT_STRING="Broadcom Northstar" +CONFIG_SYS_LOAD_ADDR=0x00008000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x00100000 +# CONFIG_BOOTSTD is not set +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_PROMPT="Boot Northstar system in %d seconds\n" +CONFIG_BOOTDELAY=1 +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="run bootcmd_dlink_dir8xxl" +CONFIG_SYS_PROMPT="northstar> " +CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=64 +CONFIG_CMD_SEAMA=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_CACHE=y +CONFIG_OF_EMBED=y +CONFIG_USE_HOSTNAME=y +CONFIG_HOSTNAME="NS" +CONFIG_CLK=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_NAND_BRCMNAND=y +CONFIG_SYS_NAND_ONFI_DETECTION=y +CONFIG_CMD_NAND=y +CONFIG_DM_SERIAL=y +CONFIG_SYS_NS16550=y +# CONFIG_NET is not set +# CONFIG_EFI_LOADER is not set diff --git a/doc/board/broadcom/index.rst b/doc/board/broadcom/index.rst index a56bd1f0692a..ca34afc82be4 100644 --- a/doc/board/broadcom/index.rst +++ b/doc/board/broadcom/index.rst @@ -9,3 +9,4 @@ Broadcom bcm7xxx raspberrypi + northstar diff --git a/doc/board/broadcom/northstar.rst b/doc/board/broadcom/northstar.rst new file mode 100644 index 000000000000..f4bc0acd0101 --- /dev/null +++ b/doc/board/broadcom/northstar.rst @@ -0,0 +1,44 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. Copyright (C) 2023 Linus Walleij + +Broadcom Northstar Boards +========================= + +This document describes how to use U-Boot on the Broadcom Northstar +boards, comprised of the Cortex A9 ARM-based BCM470x and BCM5301x SoCs. These +were introduced in 2012-2013 and some of them are also called StrataGX. + +Northstar is part of the iProc SoC family. + +A good overview of these boards can be found in Jon Mason's presentation +"Enabling New Hardware in U-Boot" where the difference between Northstar +and Northstar Plus and Northstar 2 (Aarch64) is addressed. + +The ROM in the Northstar SoC will typically look into NOR flash memory +for a boot loader, and the way this works is undocumented. It should be +possible to execute U-Boot as the first binary from the NOR flash but +this usage path is unexplored. Please add information if you know more. + +D-Link Boards +------------- + +When we use U-Boot with D-Link routers, the NOR flash has a boot loader +and web server that can re-flash the bigger NAND flash memory for object +code in the SEAMA format, so on these platforms U-Boot is converted into +a SEAMA binary and installed in the SoC using the flash tool resident in +the NOR flash. Details can be found in the OpenWrt project codebase. + +Configure +--------- + +.. code-block:: console + + $ make CROSS_COMPILE=${CROSS_COMPILE} bcmns_defconfig + +Build +----- + +.. code-block:: console + + $ make CROSS_COMPILE=${CROSS_COMPILE} + $ ${CROSS_COMPILE}strip u-boot diff --git a/include/configs/bcmns.h b/include/configs/bcmns.h new file mode 100644 index 000000000000..6f5f2b7ccf23 --- /dev/null +++ b/include/configs/bcmns.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __BCM_NS_H +#define __BCM_NS_H + +#include + +/* Physical Memory Map */ +#define V2M_BASE 0x00000000 +#define PHYS_SDRAM_1 V2M_BASE + +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 + +/* Called "periph_clk" in Linux, used by the global timer */ +#define CFG_SYS_HZ_CLOCK 500000000 + +/* Called "iprocslow" in Linux */ +#define CFG_SYS_NS16550_CLK 125000000 + +/* console configuration */ +#define CONSOLE_ARGS "console_args=console=ttyS0,115200n8\0" +#define MAX_CPUS "max_cpus=maxcpus=2\0" +#define EXTRA_ARGS "extra_args=earlycon=uart8250,mmio32,0x18000300\0" + +#define BASE_ARGS "${console_args} ${extra_args} ${pcie_args}" \ + " ${max_cpus} ${log_level} ${reserved_mem}" +#define SETBOOTARGS "setbootargs=setenv bootargs " BASE_ARGS "\0" + +#define KERNEL_LOADADDR_CFG \ + "loadaddr=0x01000000\0" \ + "dtb_loadaddr=0x02000000\0" + +/* + * Hardcoded for the only boards we support, if you add more + * boards, add a more clever bootcmd! + */ +#define NS_BOOTCMD "bootcmd_dlink_dir8xxl=seama 0x00fe0000; go 0x01000000" + +#define ARCH_ENV_SETTINGS \ + CONSOLE_ARGS \ + MAX_CPUS \ + EXTRA_ARGS \ + KERNEL_LOADADDR_CFG \ + NS_BOOTCMD + +#define CFG_EXTRA_ENV_SETTINGS \ + ARCH_ENV_SETTINGS + +#endif /* __BCM_NS_H */