From patchwork Sun Jun 2 10:26:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 165578 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp3184442ili; Sun, 2 Jun 2019 03:28:07 -0700 (PDT) X-Google-Smtp-Source: APXvYqy8nPioaKTOgBXgEAYB2FlRS5lL+z2lQJoo+/sSimk4O+A9w7HE9jC2oFOqezfSoZ8HnkCY X-Received: by 2002:a5e:a710:: with SMTP id b16mr12684684iod.38.1559471287671; Sun, 02 Jun 2019 03:28:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1559471287; cv=none; d=google.com; s=arc-20160816; b=txomM9kXvEc4xhNT8wDnnq2zZ5n5w2CAt+5MJoQ9rNPLzGzp6QU69OSdlphsz/m6ZD KUHLlBvKNXKH9EfAh5kpiVs+n3u4D6cR+q9Vj3nESBrLSGaIUsOPgoHYHDmcOd2UmqXC KVWOzgZFaKE32BsF+ygNfBV6XyqwntW2ZB0WVkib5cY6y4r4Lh42BAwr4dq/80VCb6JJ x6uiiK/4AHEjbWTzTqh6di2fZQLQ/b1G1GZwy6ThYX7x8Q2XtSVmG3xWBkw6+mItiiOX iAdbTtmDKvzru9VP4EzK1hKE7tpjRkHLTNlY0dEapMUzL1x0aWtds6jSA0F0nIpK0sBm bAKA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:message-id:date:to:from; bh=g7NBlk9d0GVm9Z42UiE19jOaeZ7IurtWu2R7RQi0eeE=; b=ZfqQ5QJkUPfGJuS2QWYBFuP+yJ3lQSJWgvsE6N4D+OZ4tr/w+4YCAtHX2el4XquTgy cst52vnRD+nWqHAG26OGfPl1ORHRI/kXRByzPLJzoGnptSN+1GKdU6uLb7uC+Y3PU77b 0Z2umteykDceEm+ZWHnTRpfntUa4FZ/dv294Y7zvHHhsE5hXJHX+ZBFhFGTe6zMZq2lF HfHfJPnr2BPeHVrgCtGQNBSebgOBVVpNnt11XYlHp+A4Thlpu9vUFMPk4kPAsAPaZDEk lgjDyW3bMYdFD5BIMaGz3hpEpJIWoSBKbwZHKnweYrH6CFRhDInz3IE4pTWfFGHv+Qw/ YhEA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id o125si7459009iof.115.2019.06.02.03.28.07 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 02 Jun 2019 03:28:07 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hXNh1-00015j-5o; Sun, 02 Jun 2019 10:26:23 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hXNgz-00015e-KL for xen-devel@lists.xenproject.org; Sun, 02 Jun 2019 10:26:21 +0000 X-Inumbo-ID: dcae1dce-8520-11e9-8980-bc764e045a96 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id dcae1dce-8520-11e9-8980-bc764e045a96; Sun, 02 Jun 2019 10:26:20 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B59AE374; Sun, 2 Jun 2019 03:26:19 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A50733F5AF; Sun, 2 Jun 2019 03:26:18 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Sun, 2 Jun 2019 11:26:14 +0100 Message-Id: <20190602102614.22640-1-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 Subject: [Xen-devel] [PATCH v2] xen/arm: irq: Don't use _IRQ_PENDING when handling host interrupt X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: andre.przywara@arm.com, Julien Grall , sstabellini@kernel.org, andrii_anisov@epam.com MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" While SPIs are shared between CPU, it is not possible to receive the same interrupts on a different CPU while the interrupt is in active state. For host interrupt (i.e routed to Xen), the deactivation of the interrupt is done at the end of the handling. This can alternatively be done outside of the handler by calling gic_set_active_state(). At the moment, gic_set_active_state() is only called by the vGIC for interrupt routed to the guest. It is hard to find a reason for Xen to directly play with the active state for interrupt routed to Xen. To simplify the handling of host interrupt, gic_set_activate_state() is now restricted to interrupts routed to guest. This means the _IRQ_PENDING logic is now unecessary on Arm as a same interrupt can never come up while in the loop and nobody should play with the flag behind our back. Signed-off-by: Julien Grall Reviewed-by: Andrii Anisov Reviewed-by: Stefano Stabellini --- Changes in v2: - gic_set_active_state should only be called on interrupt routed to guest. - Update the commit message --- xen/arch/arm/irq.c | 32 ++++++++++---------------------- xen/include/asm-arm/gic.h | 4 ++++ 2 files changed, 14 insertions(+), 22 deletions(-) diff --git a/xen/arch/arm/irq.c b/xen/arch/arm/irq.c index c51cf333ce..3877657a52 100644 --- a/xen/arch/arm/irq.c +++ b/xen/arch/arm/irq.c @@ -199,6 +199,7 @@ int request_irq(unsigned int irq, unsigned int irqflags, void do_IRQ(struct cpu_user_regs *regs, unsigned int irq, int is_fiq) { struct irq_desc *desc = irq_to_desc(irq); + struct irqaction *action; perfc_incr(irqs); @@ -242,35 +243,22 @@ void do_IRQ(struct cpu_user_regs *regs, unsigned int irq, int is_fiq) goto out_no_end; } - set_bit(_IRQ_PENDING, &desc->status); - - /* - * Since we set PENDING, if another processor is handling a different - * instance of this same irq, the other processor will take care of it. - */ - if ( test_bit(_IRQ_DISABLED, &desc->status) || - test_bit(_IRQ_INPROGRESS, &desc->status) ) + if ( test_bit(_IRQ_DISABLED, &desc->status) ) goto out; set_bit(_IRQ_INPROGRESS, &desc->status); - while ( test_bit(_IRQ_PENDING, &desc->status) ) - { - struct irqaction *action; + action = desc->action; - clear_bit(_IRQ_PENDING, &desc->status); - action = desc->action; + spin_unlock_irq(&desc->lock); - spin_unlock_irq(&desc->lock); - - do - { - action->handler(irq, action->dev_id, regs); - action = action->next; - } while ( action ); + do + { + action->handler(irq, action->dev_id, regs); + action = action->next; + } while ( action ); - spin_lock_irq(&desc->lock); - } + spin_lock_irq(&desc->lock); clear_bit(_IRQ_INPROGRESS, &desc->status); diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index fab02f19f7..876727c144 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -400,9 +400,13 @@ static inline unsigned int gic_get_nr_lrs(void) * Set the active state of an IRQ. This should be used with care, as this * directly forces the active bit, without considering the GIC state machine. * For private IRQs this only works for those of the current CPU. + * + * This should only be called with interrupt routed to guest. The flow + * of interrupt routed to Xen any software change of the state. */ static inline void gic_set_active_state(struct irq_desc *irqd, bool state) { + ASSERT(test_bit(_IRQ_GUEST, &irqd->status)); gic_hw_ops->set_active_state(irqd, state); }