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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id o2-20020a5d58c2000000b002fe522117fdsm1556388wrf.36.2023.04.20.03.04.59 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Apr 2023 03:04:59 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/21] hw/arm: Fix some typos in comments (most found by codespell) Date: Thu, 20 Apr 2023 11:04:36 +0100 Message-Id: <20230420100456.944969-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230420100456.944969-1-peter.maydell@linaro.org> References: <20230420100456.944969-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Stefan Weil Signed-off-by: Stefan Weil Reviewed-by: Philippe Mathieu-Daudé Message-id: 20230409200526.1156456-1-sw@weilnetz.de Signed-off-by: Peter Maydell --- hw/arm/exynos4210.c | 4 ++-- hw/arm/musicpal.c | 2 +- hw/arm/omap1.c | 2 +- hw/arm/omap2.c | 2 +- hw/arm/virt-acpi-build.c | 2 +- hw/arm/virt.c | 2 +- hw/arm/xlnx-versal-virt.c | 2 +- hw/arm/Kconfig | 2 +- 8 files changed, 9 insertions(+), 9 deletions(-) diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c index 6f2dda13f63..de39fb0ece8 100644 --- a/hw/arm/exynos4210.c +++ b/hw/arm/exynos4210.c @@ -326,7 +326,7 @@ static int mapline_size(const int *mapline) /* * Initialize board IRQs. - * These IRQs contain splitted Int/External Combiner and External Gic IRQs. + * These IRQs contain split Int/External Combiner and External Gic IRQs. */ static void exynos4210_init_board_irqs(Exynos4210State *s) { @@ -744,7 +744,7 @@ static void exynos4210_realize(DeviceState *socdev, Error **errp) * - SDMA * - ADMA2 * - * As this part of the Exynos4210 is not publically available, + * As this part of the Exynos4210 is not publicly available, * we used the "HS-MMC Controller S3C2416X RISC Microprocessor" * public datasheet which is very similar (implementing * MMC Specification Version 4.0 being the only difference noted) diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c index c9010b2ffbb..58f3d30c9b1 100644 --- a/hw/arm/musicpal.c +++ b/hw/arm/musicpal.c @@ -100,7 +100,7 @@ #define MP_LCD_SPI_CMD 0x00104011 #define MP_LCD_SPI_INVALID 0x00000000 -/* Commmands */ +/* Commands */ #define MP_LCD_INST_SETPAGE0 0xB0 /* ... */ #define MP_LCD_INST_SETPAGE7 0xB7 diff --git a/hw/arm/omap1.c b/hw/arm/omap1.c index 559c066ce90..d5438156ee9 100644 --- a/hw/arm/omap1.c +++ b/hw/arm/omap1.c @@ -4057,7 +4057,7 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *dram, s->led[1] = omap_lpg_init(system_memory, 0xfffbd800, omap_findclk(s, "clk32-kHz")); - /* Register mappings not currenlty implemented: + /* Register mappings not currently implemented: * MCSI2 Comm fffb2000 - fffb27ff (not mapped on OMAP310) * MCSI1 Bluetooth fffb2800 - fffb2fff (not mapped on OMAP310) * USB W2FC fffb4000 - fffb47ff diff --git a/hw/arm/omap2.c b/hw/arm/omap2.c index 366d6af1b66..d5a2ae7af6e 100644 --- a/hw/arm/omap2.c +++ b/hw/arm/omap2.c @@ -2523,7 +2523,7 @@ struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sdram, omap_findclk(s, "func_96m_clk"), omap_findclk(s, "core_l4_iclk")); - /* All register mappings (includin those not currenlty implemented): + /* All register mappings (including those not currently implemented): * SystemControlMod 48000000 - 48000fff * SystemControlL4 48001000 - 48001fff * 32kHz Timer Mod 48004000 - 48004fff diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 4156111d49f..4af0de8b241 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -694,7 +694,7 @@ static void build_append_gicr(GArray *table_data, uint64_t base, uint32_t size) build_append_int_noprefix(table_data, 0xE, 1); /* Type */ build_append_int_noprefix(table_data, 16, 1); /* Length */ build_append_int_noprefix(table_data, 0, 2); /* Reserved */ - /* Discovery Range Base Addres */ + /* Discovery Range Base Address */ build_append_int_noprefix(table_data, base, 8); build_append_int_noprefix(table_data, size, 4); /* Discovery Range Length */ } diff --git a/hw/arm/virt.c b/hw/arm/virt.c index ac626b3bef7..4983f5fc93a 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -2052,7 +2052,7 @@ static void machvirt_init(MachineState *machine) int pa_bits; /* - * Instanciate a temporary CPU object to find out about what + * Instantiate a temporary CPU object to find out about what * we are about to deal with. Once this is done, get rid of * the object. */ diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c index 37fc9b919c0..668a9d65a43 100644 --- a/hw/arm/xlnx-versal-virt.c +++ b/hw/arm/xlnx-versal-virt.c @@ -659,7 +659,7 @@ static void versal_virt_init(MachineState *machine) fdt_add_clk_node(s, "/clk25", 25000000, s->phandle.clk_25Mhz); /* Make the APU cpu address space visible to virtio and other - * modules unaware of muliple address-spaces. */ + * modules unaware of multiple address-spaces. */ memory_region_add_subregion_overlap(get_system_memory(), 0, &s->soc.fpd.apu.mr, 0); diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index b5aed4aff56..db1105c7175 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -126,7 +126,7 @@ config OLIMEX_STM32_H405 config NSERIES bool select OMAP - select TMP105 # tempature sensor + select TMP105 # temperature sensor select BLIZZARD # LCD/TV controller select ONENAND select TSC210X # touchscreen/sensors/audio From patchwork Thu Apr 20 10:04:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 675606 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a41:0:0:0:0:0 with SMTP id v1csp221765wrs; Thu, 20 Apr 2023 03:08:35 -0700 (PDT) X-Google-Smtp-Source: AKy350a2HaDWjH3qcbjwfX23umUMmcKxxAvvIprDX5UdL6jjiDBtasZK+tvx/hD8JhQSfVrBHOyM X-Received: by 2002:a05:622a:1982:b0:3ef:2a5:ee7b with SMTP id u2-20020a05622a198200b003ef02a5ee7bmr747646qtc.58.1681985315432; Thu, 20 Apr 2023 03:08:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681985315; cv=none; d=google.com; s=arc-20160816; b=Gy2D1n4DMwavtOwLB0RO++0wNWFQ9lzSHtC0OYDdLKlZMoF0R523k71I2HJ240QaJu 9mcdPTNstWhqIAl8AS4Xf561hc854Q47zWeXz0qnbBc1qYauyKSykd+klENW+TDTdrj6 v4bqOZSykaJ9awo/flaPxOLOzDyl9hvXrch9AEVifm7BHd4CGcC+WxzDDjt2sLl3Xu7X sRn7WwFe6kGCpct4w6MWtyei32OIJiDkBZMnG3oqfLj0AEJjR1vJlZ/E6yT3QXozIhkO /JjX8QhSKCi6jtVKeEmWfklLAzxbgeKOdxp/30IB3SHT/DPS2YoiCCtTYGrdOjUch+Zf 3FYg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=oMEpsYca7tx1v9ldNloh95tUqbg4QvdTa03d2PGTKsg=; b=Ro6abckLscnoVw67LrYBdIkSC6Rpns/+4d9fVAABZKrUNIQlefepmOl2xBSJ7Pd0o5 Y91fUsCh2lHrqvWqXGwYEl38F/iKvdOwuWghEzourlDend1hda0jIPMEd0Glifj8/dcE vIMmLns/uVF7qWDBcdGYd+FM5YUdLBDHE7tq/Pya1T6arB4QgdkPhoNMA3de50rbG7yG ZAd5aFJrcownpEe8zdhfP4kpI7o4+J1FbaObmeUgFadbdhSdQHPgkW6t+tqUmURzKjIh ZL9Dp1O6jevzzLXvuqs5YTgLzPJenkUg0Y9bj8awKVPN3We1lG12wDR82Uk9uihBkKmN atJw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZfhykoFe; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id o2-20020a5d58c2000000b002fe522117fdsm1556388wrf.36.2023.04.20.03.05.00 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Apr 2023 03:05:00 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/21] exynos: Fix out-of-bounds access in exynos4210_gcomp_find debug printf Date: Thu, 20 Apr 2023 11:04:37 +0100 Message-Id: <20230420100456.944969-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230420100456.944969-1-peter.maydell@linaro.org> References: <20230420100456.944969-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Feng Jiang One of the debug printfs in exynos4210_gcomp_find() will access outside the 's->g_timer.reg.comp[]' array if there was no active comparator and 'res' is -1. Add a conditional to avoid this. This doesn't happen in normal use because the debug printfs are by default not compiled in. Signed-off-by: Feng Jiang Message-id: 20230404074506.112615-1-jiangfeng@kylinos.cn Reviewed-by: Peter Maydell [PMM: Adjusted commit message to clarify that the overrun only happens if you've enabled debug printfs] Signed-off-by: Peter Maydell --- hw/timer/exynos4210_mct.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c index c17b247da34..446bbd2b96c 100644 --- a/hw/timer/exynos4210_mct.c +++ b/hw/timer/exynos4210_mct.c @@ -480,11 +480,14 @@ static int32_t exynos4210_gcomp_find(Exynos4210MCTState *s) res = min_comp_i; } - DPRINTF("found comparator %d: comp 0x%llx distance 0x%llx, gfrc 0x%llx\n", - res, - s->g_timer.reg.comp[res], - distance_min, - gfrc); + if (res >= 0) { + DPRINTF("found comparator %d: " + "comp 0x%llx distance 0x%llx, gfrc 0x%llx\n", + res, + s->g_timer.reg.comp[res], + distance_min, + gfrc); + } return res; } From patchwork Thu Apr 20 10:04:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 675599 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a41:0:0:0:0:0 with SMTP id v1csp221267wrs; Thu, 20 Apr 2023 03:07:30 -0700 (PDT) X-Google-Smtp-Source: AKy350b+/VC92LR2Utr717olnv7rCkFiVMrXrwYWGxHgmqCyEr50+Cf661dU6/MEOUsSm5vZK3hO X-Received: by 2002:a05:622a:144c:b0:3ef:397b:9a5 with SMTP id v12-20020a05622a144c00b003ef397b09a5mr902404qtx.67.1681985250752; Thu, 20 Apr 2023 03:07:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681985250; cv=none; d=google.com; s=arc-20160816; b=VxyHevLiRoO6EmvCbDVl+afozYGv0+0FbkjGtT4M1DjQJ2xa0GlLslTCmOQwL5zW2V 5ppNIqQC4+o0SiMU4LAI7c1N9UEhrm/Ld34UVB7FmVOE+K6EYyoeRd25fQkwhJc1aOIF XvYHvYGhw3jliR/Tic/bElvXHIzN7gaH9/VTjGGGFcPIxG2VrUtoADMSAjiondVob5hZ /S5Ww1U5qnQDXwCnyf2IrNYuY5GmN+W+O5Uk38TPyCy7HRgXd4zea+I7WQ/toZMD5J2K UAK6HGGUm6P1x+k7roDMKdc74z5w6WMMgVmOpuxHw17ZYwzu4d0He3O/wdQ10HEcSMaY JApQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=L7nlUevNqyMVdqq24J8aX19ltWH+K+rS+TXuZnL1vZQ=; b=x2IFf2c9dlnaSGHLH0ol0qNoff1wzvSQ4z6vDHuQGxMs6PgXfpuUH6tx8s9aUB7rqb sD0s30loBKmZ/HgldIGYUQ9WRUJO1X12EjoKyKCxEmgy8WrvAyxpgwNQxLoPZH0t6qHu wthp9dln/Z2qcIqMwkg6In8f5hebzVrRZCmO29rJh6qRMHd/Ww6V7EmYOrqaYwPWGYrc iJtq93OJnjN5X9uvSmQQpZPjBFzAaSo0EyIQ5Jp6BlaCzue3dN7flDny5GZbOYiT94mj yIYjHLSCSGaY1ASSmpRwLqSYaofS38QSARCunsIZxHRgYTmdzSAR/9S4/TO74aq8WU0G 2iEg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=DS7OlppC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id o2-20020a5d58c2000000b002fe522117fdsm1556388wrf.36.2023.04.20.03.05.00 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Apr 2023 03:05:00 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/21] hw/watchdog: Allwinner WDT emulation for system reset Date: Thu, 20 Apr 2023 11:04:38 +0100 Message-Id: <20230420100456.944969-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230420100456.944969-1-peter.maydell@linaro.org> References: <20230420100456.944969-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Strahinja Jankovic This patch adds basic support for Allwinner WDT. Both sun4i and sun6i variants are supported. However, interrupt generation is not supported, so WDT can be used only to trigger system reset. Signed-off-by: Strahinja Jankovic Reviewed-by: Niek Linnenbank Tested-by: Niek Linnenbank Message-id: 20230326202256.22980-2-strahinja.p.jankovic@gmail.com Signed-off-by: Peter Maydell --- include/hw/watchdog/allwinner-wdt.h | 123 ++++++++ hw/watchdog/allwinner-wdt.c | 416 ++++++++++++++++++++++++++++ hw/watchdog/Kconfig | 4 + hw/watchdog/meson.build | 1 + hw/watchdog/trace-events | 7 + 5 files changed, 551 insertions(+) create mode 100644 include/hw/watchdog/allwinner-wdt.h create mode 100644 hw/watchdog/allwinner-wdt.c diff --git a/include/hw/watchdog/allwinner-wdt.h b/include/hw/watchdog/allwinner-wdt.h new file mode 100644 index 00000000000..7fe41e20f2e --- /dev/null +++ b/include/hw/watchdog/allwinner-wdt.h @@ -0,0 +1,123 @@ +/* + * Allwinner Watchdog emulation + * + * Copyright (C) 2023 Strahinja Jankovic + * + * This file is derived from Allwinner RTC, + * by Niek Linnenbank. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef HW_WATCHDOG_ALLWINNER_WDT_H +#define HW_WATCHDOG_ALLWINNER_WDT_H + +#include "qom/object.h" +#include "hw/ptimer.h" +#include "hw/sysbus.h" + +/* + * This is a model of the Allwinner watchdog. + * Since watchdog registers belong to the timer module (and are shared with the + * RTC module), the interrupt line from watchdog is not handled right now. + * In QEMU, we just wire up the watchdog reset to watchdog_perform_action(), + * at least for the moment. + */ + +#define TYPE_AW_WDT "allwinner-wdt" + +/** Allwinner WDT sun4i family (A10, A12), also sun7i (A20) */ +#define TYPE_AW_WDT_SUN4I TYPE_AW_WDT "-sun4i" + +/** Allwinner WDT sun6i family and newer (A31, H2+, H3, etc) */ +#define TYPE_AW_WDT_SUN6I TYPE_AW_WDT "-sun6i" + +/** Number of WDT registers */ +#define AW_WDT_REGS_NUM (5) + +OBJECT_DECLARE_TYPE(AwWdtState, AwWdtClass, AW_WDT) + +/** + * Allwinner WDT object instance state. + */ +struct AwWdtState { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + MemoryRegion iomem; + struct ptimer_state *timer; + + uint32_t regs[AW_WDT_REGS_NUM]; +}; + +/** + * Allwinner WDT class-level struct. + * + * This struct is filled by each sunxi device specific code + * such that the generic code can use this struct to support + * all devices. + */ +struct AwWdtClass { + /*< private >*/ + SysBusDeviceClass parent_class; + /*< public >*/ + + /** Defines device specific register map */ + const uint8_t *regmap; + + /** Size of the regmap in bytes */ + size_t regmap_size; + + /** + * Read device specific register + * + * @offset: register offset to read + * @return true if register read successful, false otherwise + */ + bool (*read)(AwWdtState *s, uint32_t offset); + + /** + * Write device specific register + * + * @offset: register offset to write + * @data: value to set in register + * @return true if register write successful, false otherwise + */ + bool (*write)(AwWdtState *s, uint32_t offset, uint32_t data); + + /** + * Check if watchdog can generate system reset + * + * @return true if watchdog can generate system reset + */ + bool (*can_reset_system)(AwWdtState *s); + + /** + * Check if provided key is valid + * + * @value: value written to register + * @return true if key is valid, false otherwise + */ + bool (*is_key_valid)(AwWdtState *s, uint32_t val); + + /** + * Get current INTV_VALUE setting + * + * @return current INTV_VALUE (0-15) + */ + uint8_t (*get_intv_value)(AwWdtState *s); +}; + +#endif /* HW_WATCHDOG_ALLWINNER_WDT_H */ diff --git a/hw/watchdog/allwinner-wdt.c b/hw/watchdog/allwinner-wdt.c new file mode 100644 index 00000000000..6205765efec --- /dev/null +++ b/hw/watchdog/allwinner-wdt.c @@ -0,0 +1,416 @@ +/* + * Allwinner Watchdog emulation + * + * Copyright (C) 2023 Strahinja Jankovic + * + * This file is derived from Allwinner RTC, + * by Niek Linnenbank. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qemu/units.h" +#include "qemu/module.h" +#include "trace.h" +#include "hw/sysbus.h" +#include "hw/registerfields.h" +#include "hw/watchdog/allwinner-wdt.h" +#include "sysemu/watchdog.h" +#include "migration/vmstate.h" + +/* WDT registers */ +enum { + REG_IRQ_EN = 0, /* Watchdog interrupt enable */ + REG_IRQ_STA, /* Watchdog interrupt status */ + REG_CTRL, /* Watchdog control register */ + REG_CFG, /* Watchdog configuration register */ + REG_MODE, /* Watchdog mode register */ +}; + +/* Universal WDT register flags */ +#define WDT_RESTART_MASK (1 << 0) +#define WDT_EN_MASK (1 << 0) + +/* sun4i specific WDT register flags */ +#define RST_EN_SUN4I_MASK (1 << 1) +#define INTV_VALUE_SUN4I_SHIFT (3) +#define INTV_VALUE_SUN4I_MASK (0xfu << INTV_VALUE_SUN4I_SHIFT) + +/* sun6i specific WDT register flags */ +#define RST_EN_SUN6I_MASK (1 << 0) +#define KEY_FIELD_SUN6I_SHIFT (1) +#define KEY_FIELD_SUN6I_MASK (0xfffu << KEY_FIELD_SUN6I_SHIFT) +#define KEY_FIELD_SUN6I (0xA57u) +#define INTV_VALUE_SUN6I_SHIFT (4) +#define INTV_VALUE_SUN6I_MASK (0xfu << INTV_VALUE_SUN6I_SHIFT) + +/* Map of INTV_VALUE to 0.5s units. */ +static const uint8_t allwinner_wdt_count_map[] = { + 1, + 2, + 4, + 6, + 8, + 10, + 12, + 16, + 20, + 24, + 28, + 32 +}; + +/* WDT sun4i register map (offset to name) */ +const uint8_t allwinner_wdt_sun4i_regmap[] = { + [0x0000] = REG_CTRL, + [0x0004] = REG_MODE, +}; + +/* WDT sun6i register map (offset to name) */ +const uint8_t allwinner_wdt_sun6i_regmap[] = { + [0x0000] = REG_IRQ_EN, + [0x0004] = REG_IRQ_STA, + [0x0010] = REG_CTRL, + [0x0014] = REG_CFG, + [0x0018] = REG_MODE, +}; + +static bool allwinner_wdt_sun4i_read(AwWdtState *s, uint32_t offset) +{ + /* no sun4i specific registers currently implemented */ + return false; +} + +static bool allwinner_wdt_sun4i_write(AwWdtState *s, uint32_t offset, + uint32_t data) +{ + /* no sun4i specific registers currently implemented */ + return false; +} + +static bool allwinner_wdt_sun4i_can_reset_system(AwWdtState *s) +{ + if (s->regs[REG_MODE] & RST_EN_SUN4I_MASK) { + return true; + } else { + return false; + } +} + +static bool allwinner_wdt_sun4i_is_key_valid(AwWdtState *s, uint32_t val) +{ + /* sun4i has no key */ + return true; +} + +static uint8_t allwinner_wdt_sun4i_get_intv_value(AwWdtState *s) +{ + return ((s->regs[REG_MODE] & INTV_VALUE_SUN4I_MASK) >> + INTV_VALUE_SUN4I_SHIFT); +} + +static bool allwinner_wdt_sun6i_read(AwWdtState *s, uint32_t offset) +{ + const AwWdtClass *c = AW_WDT_GET_CLASS(s); + + switch (c->regmap[offset]) { + case REG_IRQ_EN: + case REG_IRQ_STA: + case REG_CFG: + return true; + default: + break; + } + return false; +} + +static bool allwinner_wdt_sun6i_write(AwWdtState *s, uint32_t offset, + uint32_t data) +{ + const AwWdtClass *c = AW_WDT_GET_CLASS(s); + + switch (c->regmap[offset]) { + case REG_IRQ_EN: + case REG_IRQ_STA: + case REG_CFG: + return true; + default: + break; + } + return false; +} + +static bool allwinner_wdt_sun6i_can_reset_system(AwWdtState *s) +{ + if (s->regs[REG_CFG] & RST_EN_SUN6I_MASK) { + return true; + } else { + return false; + } +} + +static bool allwinner_wdt_sun6i_is_key_valid(AwWdtState *s, uint32_t val) +{ + uint16_t key = (val & KEY_FIELD_SUN6I_MASK) >> KEY_FIELD_SUN6I_SHIFT; + return (key == KEY_FIELD_SUN6I); +} + +static uint8_t allwinner_wdt_sun6i_get_intv_value(AwWdtState *s) +{ + return ((s->regs[REG_MODE] & INTV_VALUE_SUN6I_MASK) >> + INTV_VALUE_SUN6I_SHIFT); +} + +static void allwinner_wdt_update_timer(AwWdtState *s) +{ + const AwWdtClass *c = AW_WDT_GET_CLASS(s); + uint8_t count = c->get_intv_value(s); + + ptimer_transaction_begin(s->timer); + ptimer_stop(s->timer); + + /* Use map to convert. */ + if (count < sizeof(allwinner_wdt_count_map)) { + ptimer_set_count(s->timer, allwinner_wdt_count_map[count]); + } else { + qemu_log_mask(LOG_GUEST_ERROR, "%s: incorrect INTV_VALUE 0x%02x\n", + __func__, count); + } + + ptimer_run(s->timer, 1); + ptimer_transaction_commit(s->timer); + + trace_allwinner_wdt_update_timer(count); +} + +static uint64_t allwinner_wdt_read(void *opaque, hwaddr offset, + unsigned size) +{ + AwWdtState *s = AW_WDT(opaque); + const AwWdtClass *c = AW_WDT_GET_CLASS(s); + uint64_t r; + + if (offset >= c->regmap_size) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n", + __func__, (uint32_t)offset); + return 0; + } + + switch (c->regmap[offset]) { + case REG_CTRL: + case REG_MODE: + r = s->regs[c->regmap[offset]]; + break; + default: + if (!c->read(s, offset)) { + qemu_log_mask(LOG_UNIMP, "%s: unimplemented register 0x%04x\n", + __func__, (uint32_t)offset); + return 0; + } + r = s->regs[c->regmap[offset]]; + break; + } + + trace_allwinner_wdt_read(offset, r, size); + + return r; +} + +static void allwinner_wdt_write(void *opaque, hwaddr offset, + uint64_t val, unsigned size) +{ + AwWdtState *s = AW_WDT(opaque); + const AwWdtClass *c = AW_WDT_GET_CLASS(s); + uint32_t old_val; + + if (offset >= c->regmap_size) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n", + __func__, (uint32_t)offset); + return; + } + + trace_allwinner_wdt_write(offset, val, size); + + switch (c->regmap[offset]) { + case REG_CTRL: + if (c->is_key_valid(s, val)) { + if (val & WDT_RESTART_MASK) { + /* Kick timer */ + allwinner_wdt_update_timer(s); + } + } + break; + case REG_MODE: + old_val = s->regs[REG_MODE]; + s->regs[REG_MODE] = (uint32_t)val; + + /* Check for rising edge on WDOG_MODE_EN */ + if ((s->regs[REG_MODE] & ~old_val) & WDT_EN_MASK) { + allwinner_wdt_update_timer(s); + } + break; + default: + if (!c->write(s, offset, val)) { + qemu_log_mask(LOG_UNIMP, "%s: unimplemented register 0x%04x\n", + __func__, (uint32_t)offset); + } + s->regs[c->regmap[offset]] = (uint32_t)val; + break; + } +} + +static const MemoryRegionOps allwinner_wdt_ops = { + .read = allwinner_wdt_read, + .write = allwinner_wdt_write, + .endianness = DEVICE_NATIVE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4, + }, + .impl.min_access_size = 4, +}; + +static void allwinner_wdt_expired(void *opaque) +{ + AwWdtState *s = AW_WDT(opaque); + const AwWdtClass *c = AW_WDT_GET_CLASS(s); + + bool enabled = s->regs[REG_MODE] & WDT_EN_MASK; + bool reset_enabled = c->can_reset_system(s); + + trace_allwinner_wdt_expired(enabled, reset_enabled); + + /* Perform watchdog action if watchdog is enabled and can trigger reset */ + if (enabled && reset_enabled) { + watchdog_perform_action(); + } +} + +static void allwinner_wdt_reset_enter(Object *obj, ResetType type) +{ + AwWdtState *s = AW_WDT(obj); + + trace_allwinner_wdt_reset_enter(); + + /* Clear registers */ + memset(s->regs, 0, sizeof(s->regs)); +} + +static const VMStateDescription allwinner_wdt_vmstate = { + .name = "allwinner-wdt", + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_PTIMER(timer, AwWdtState), + VMSTATE_UINT32_ARRAY(regs, AwWdtState, AW_WDT_REGS_NUM), + VMSTATE_END_OF_LIST() + } +}; + +static void allwinner_wdt_init(Object *obj) +{ + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); + AwWdtState *s = AW_WDT(obj); + const AwWdtClass *c = AW_WDT_GET_CLASS(s); + + /* Memory mapping */ + memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_wdt_ops, s, + TYPE_AW_WDT, c->regmap_size * 4); + sysbus_init_mmio(sbd, &s->iomem); +} + +static void allwinner_wdt_realize(DeviceState *dev, Error **errp) +{ + AwWdtState *s = AW_WDT(dev); + + s->timer = ptimer_init(allwinner_wdt_expired, s, + PTIMER_POLICY_NO_IMMEDIATE_TRIGGER | + PTIMER_POLICY_NO_IMMEDIATE_RELOAD | + PTIMER_POLICY_NO_COUNTER_ROUND_DOWN); + + ptimer_transaction_begin(s->timer); + /* Set to 2Hz (0.5s period); other periods are multiples of 0.5s. */ + ptimer_set_freq(s->timer, 2); + ptimer_set_limit(s->timer, 0xff, 1); + ptimer_transaction_commit(s->timer); +} + +static void allwinner_wdt_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + ResettableClass *rc = RESETTABLE_CLASS(klass); + + rc->phases.enter = allwinner_wdt_reset_enter; + dc->realize = allwinner_wdt_realize; + dc->vmsd = &allwinner_wdt_vmstate; +} + +static void allwinner_wdt_sun4i_class_init(ObjectClass *klass, void *data) +{ + AwWdtClass *awc = AW_WDT_CLASS(klass); + + awc->regmap = allwinner_wdt_sun4i_regmap; + awc->regmap_size = sizeof(allwinner_wdt_sun4i_regmap); + awc->read = allwinner_wdt_sun4i_read; + awc->write = allwinner_wdt_sun4i_write; + awc->can_reset_system = allwinner_wdt_sun4i_can_reset_system; + awc->is_key_valid = allwinner_wdt_sun4i_is_key_valid; + awc->get_intv_value = allwinner_wdt_sun4i_get_intv_value; +} + +static void allwinner_wdt_sun6i_class_init(ObjectClass *klass, void *data) +{ + AwWdtClass *awc = AW_WDT_CLASS(klass); + + awc->regmap = allwinner_wdt_sun6i_regmap; + awc->regmap_size = sizeof(allwinner_wdt_sun6i_regmap); + awc->read = allwinner_wdt_sun6i_read; + awc->write = allwinner_wdt_sun6i_write; + awc->can_reset_system = allwinner_wdt_sun6i_can_reset_system; + awc->is_key_valid = allwinner_wdt_sun6i_is_key_valid; + awc->get_intv_value = allwinner_wdt_sun6i_get_intv_value; +} + +static const TypeInfo allwinner_wdt_info = { + .name = TYPE_AW_WDT, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_init = allwinner_wdt_init, + .instance_size = sizeof(AwWdtState), + .class_init = allwinner_wdt_class_init, + .class_size = sizeof(AwWdtClass), + .abstract = true, +}; + +static const TypeInfo allwinner_wdt_sun4i_info = { + .name = TYPE_AW_WDT_SUN4I, + .parent = TYPE_AW_WDT, + .class_init = allwinner_wdt_sun4i_class_init, +}; + +static const TypeInfo allwinner_wdt_sun6i_info = { + .name = TYPE_AW_WDT_SUN6I, + .parent = TYPE_AW_WDT, + .class_init = allwinner_wdt_sun6i_class_init, +}; + +static void allwinner_wdt_register(void) +{ + type_register_static(&allwinner_wdt_info); + type_register_static(&allwinner_wdt_sun4i_info); + type_register_static(&allwinner_wdt_sun6i_info); +} + +type_init(allwinner_wdt_register) diff --git a/hw/watchdog/Kconfig b/hw/watchdog/Kconfig index 66e1d029e32..861fd003341 100644 --- a/hw/watchdog/Kconfig +++ b/hw/watchdog/Kconfig @@ -20,3 +20,7 @@ config WDT_IMX2 config WDT_SBSA bool + +config ALLWINNER_WDT + bool + select PTIMER diff --git a/hw/watchdog/meson.build b/hw/watchdog/meson.build index 8974b5cf4c8..5dcd4fbe2f1 100644 --- a/hw/watchdog/meson.build +++ b/hw/watchdog/meson.build @@ -1,4 +1,5 @@ softmmu_ss.add(files('watchdog.c')) +softmmu_ss.add(when: 'CONFIG_ALLWINNER_WDT', if_true: files('allwinner-wdt.c')) softmmu_ss.add(when: 'CONFIG_CMSDK_APB_WATCHDOG', if_true: files('cmsdk-apb-watchdog.c')) softmmu_ss.add(when: 'CONFIG_WDT_IB6300ESB', if_true: files('wdt_i6300esb.c')) softmmu_ss.add(when: 'CONFIG_WDT_IB700', if_true: files('wdt_ib700.c')) diff --git a/hw/watchdog/trace-events b/hw/watchdog/trace-events index 54371ae0755..2739570652b 100644 --- a/hw/watchdog/trace-events +++ b/hw/watchdog/trace-events @@ -1,5 +1,12 @@ # See docs/devel/tracing.rst for syntax documentation. +# allwinner-wdt.c +allwinner_wdt_read(uint64_t offset, uint64_t data, unsigned size) "Allwinner watchdog read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" +allwinner_wdt_write(uint64_t offset, uint64_t data, unsigned size) "Allwinner watchdog write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" +allwinner_wdt_reset_enter(void) "Allwinner watchdog: reset" +allwinner_wdt_update_timer(uint8_t count) "Allwinner watchdog: count %" PRIu8 +allwinner_wdt_expired(bool enabled, bool reset_enabled) "Allwinner watchdog: enabled %u reset_enabled %u" + # cmsdk-apb-watchdog.c cmsdk_apb_watchdog_read(uint64_t offset, uint64_t data, unsigned size) "CMSDK APB watchdog read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" cmsdk_apb_watchdog_write(uint64_t offset, uint64_t data, unsigned size) "CMSDK APB watchdog write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" From patchwork Thu Apr 20 10:04:39 2023 Content-Type: text/plain; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id o2-20020a5d58c2000000b002fe522117fdsm1556388wrf.36.2023.04.20.03.05.01 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Apr 2023 03:05:01 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/21] hw/arm: Add WDT to Allwinner-A10 and Cubieboard Date: Thu, 20 Apr 2023 11:04:39 +0100 Message-Id: <20230420100456.944969-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230420100456.944969-1-peter.maydell@linaro.org> References: <20230420100456.944969-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Strahinja Jankovic This patch adds WDT to Allwinner-A10 and Cubieboard. WDT is added as an overlay to the Timer module memory map. Signed-off-by: Strahinja Jankovic Reviewed-by: Niek Linnenbank Message-id: 20230326202256.22980-3-strahinja.p.jankovic@gmail.com Signed-off-by: Peter Maydell --- docs/system/arm/cubieboard.rst | 1 + include/hw/arm/allwinner-a10.h | 2 ++ hw/arm/allwinner-a10.c | 7 +++++++ hw/arm/Kconfig | 1 + 4 files changed, 11 insertions(+) diff --git a/docs/system/arm/cubieboard.rst b/docs/system/arm/cubieboard.rst index 8d485f5435a..58c4a2d3ea6 100644 --- a/docs/system/arm/cubieboard.rst +++ b/docs/system/arm/cubieboard.rst @@ -15,3 +15,4 @@ Emulated devices: - USB controller - SATA controller - TWI (I2C) controller +- Watchdog timer diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h index 095afb225d6..cd1465c6138 100644 --- a/include/hw/arm/allwinner-a10.h +++ b/include/hw/arm/allwinner-a10.h @@ -13,6 +13,7 @@ #include "hw/misc/allwinner-a10-ccm.h" #include "hw/misc/allwinner-a10-dramc.h" #include "hw/i2c/allwinner-i2c.h" +#include "hw/watchdog/allwinner-wdt.h" #include "sysemu/block-backend.h" #include "target/arm/cpu.h" @@ -41,6 +42,7 @@ struct AwA10State { AwSdHostState mmc0; AWI2CState i2c0; AwRtcState rtc; + AwWdtState wdt; MemoryRegion sram_a; EHCISysBusState ehci[AW_A10_NUM_USB]; OHCISysBusState ohci[AW_A10_NUM_USB]; diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c index b7ca795c712..b0ea3f7f662 100644 --- a/hw/arm/allwinner-a10.c +++ b/hw/arm/allwinner-a10.c @@ -38,6 +38,7 @@ #define AW_A10_EHCI_BASE 0x01c14000 #define AW_A10_OHCI_BASE 0x01c14400 #define AW_A10_SATA_BASE 0x01c18000 +#define AW_A10_WDT_BASE 0x01c20c90 #define AW_A10_RTC_BASE 0x01c20d00 #define AW_A10_I2C0_BASE 0x01c2ac00 @@ -92,6 +93,8 @@ static void aw_a10_init(Object *obj) object_initialize_child(obj, "mmc0", &s->mmc0, TYPE_AW_SDHOST_SUN4I); object_initialize_child(obj, "rtc", &s->rtc, TYPE_AW_RTC_SUN4I); + + object_initialize_child(obj, "wdt", &s->wdt, TYPE_AW_WDT_SUN4I); } static void aw_a10_realize(DeviceState *dev, Error **errp) @@ -203,6 +206,10 @@ static void aw_a10_realize(DeviceState *dev, Error **errp) sysbus_realize(SYS_BUS_DEVICE(&s->i2c0), &error_fatal); sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c0), 0, AW_A10_I2C0_BASE); sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c0), 0, qdev_get_gpio_in(dev, 7)); + + /* WDT */ + sysbus_realize(SYS_BUS_DEVICE(&s->wdt), &error_fatal); + sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->wdt), 0, AW_A10_WDT_BASE, 1); } static void aw_a10_class_init(ObjectClass *oc, void *data) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index db1105c7175..338dabce427 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -325,6 +325,7 @@ config ALLWINNER_A10 select ALLWINNER_A10_PIC select ALLWINNER_A10_CCM select ALLWINNER_A10_DRAMC + select ALLWINNER_WDT select ALLWINNER_EMAC select ALLWINNER_I2C select AXP209_PMU From patchwork Thu Apr 20 10:04:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 675602 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a41:0:0:0:0:0 with SMTP id v1csp221430wrs; Thu, 20 Apr 2023 03:07:51 -0700 (PDT) X-Google-Smtp-Source: AKy350bto0w30GoNeo1EarSVg8lOuEwWJNwqqhoxZo+wIZ9gh3Pj7y/V9ptNg+xdMvm3jn4kQ7eE X-Received: by 2002:a05:6214:27c8:b0:5e7:b5c5:5558 with SMTP id ge8-20020a05621427c800b005e7b5c55558mr867696qvb.44.1681985270907; Thu, 20 Apr 2023 03:07:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681985270; cv=none; d=google.com; s=arc-20160816; b=pSqDMELb84gFPVJYK0hFBNghPNzvbmtVb51qGfb+hML3fVwVK1x7+UDb8obxjj1JOg h0vJCf6E+KvJwF54CeUqErSJmjn/Pb5Xl6aAxQ6448T8Ne7xUQNPb7572XM0ugcQhCm1 lsc4z3QG3Rxf6Vs1rqaZRl/HGdbzs//GyBwiN4txhIHnsKQqlp8mlnzSUdBID3Brot2G bwbVvcEpBtPy2khX0ioE0YTMElUuTbi7NAehdQHCvvRXS2cnh6t902zTO4B1Zj9vRSFf Vk52Agsyq4IDd2asw9uwFDDvDwosC5wUOuf1TYmeyS843BOo+QdWLfk+CjinyRwBJu20 ecUw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=gHMd6Mccc9WWoHnZhKOQsV6TX3fZq4KK5xzXCVpXhHc=; b=ncL1aBfkgk+xiaa323jy4baAUpdR7S8om2XZ7R71DR2nF55E2zWg/EtD26k8X+XYtC XlykS//Zi/mAty4L+STzGkZypseTHGRQLsaCNWuFQjUIGPzEJqM9iSbLZ+P249N5W9D8 xNM6leFiiJKX++vhsEVEwd/NQEeff1AzryRlOrtaw/rC21B4yD6yd8GthuLsyIxCWB4Z CKDuyIAnBCkw944krtMgohaFmLyv+/0+PLA7Zk6co0d18mpZuVBnSpgPPocmjzsgE88m IO621pYmAKXqurQCLtULTLqH9ibIs9Z8xCcfzkNRh5wpNqe/b41vm3QQt71inIbkQMQM hzyw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jV43J+jP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id o2-20020a5d58c2000000b002fe522117fdsm1556388wrf.36.2023.04.20.03.05.01 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Apr 2023 03:05:01 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/21] hw/arm: Add WDT to Allwinner-H3 and Orangepi-PC Date: Thu, 20 Apr 2023 11:04:40 +0100 Message-Id: <20230420100456.944969-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230420100456.944969-1-peter.maydell@linaro.org> References: <20230420100456.944969-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, WEIRD_QUOTING=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Strahinja Jankovic This patch adds WDT to Allwinner-H3 and Orangepi-PC. WDT is added as an overlay to the Timer module memory area. Signed-off-by: Strahinja Jankovic Reviewed-by: Niek Linnenbank Message-id: 20230326202256.22980-4-strahinja.p.jankovic@gmail.com Signed-off-by: Peter Maydell --- docs/system/arm/orangepi.rst | 1 + include/hw/arm/allwinner-h3.h | 5 ++++- hw/arm/allwinner-h3.c | 8 ++++++++ hw/arm/Kconfig | 1 + 4 files changed, 14 insertions(+), 1 deletion(-) diff --git a/docs/system/arm/orangepi.rst b/docs/system/arm/orangepi.rst index e5973600a15..9afa54213b0 100644 --- a/docs/system/arm/orangepi.rst +++ b/docs/system/arm/orangepi.rst @@ -26,6 +26,7 @@ The Orange Pi PC machine supports the following devices: * System Control module * Security Identifier device * TWI (I2C) + * Watchdog timer Limitations """"""""""" diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h index 59e0f822d2d..f15d6d7cc7d 100644 --- a/include/hw/arm/allwinner-h3.h +++ b/include/hw/arm/allwinner-h3.h @@ -48,6 +48,7 @@ #include "hw/net/allwinner-sun8i-emac.h" #include "hw/rtc/allwinner-rtc.h" #include "hw/i2c/allwinner-i2c.h" +#include "hw/watchdog/allwinner-wdt.h" #include "target/arm/cpu.h" #include "sysemu/block-backend.h" @@ -96,7 +97,8 @@ enum { AW_H3_DEV_RTC, AW_H3_DEV_CPUCFG, AW_H3_DEV_R_TWI, - AW_H3_DEV_SDRAM + AW_H3_DEV_SDRAM, + AW_H3_DEV_WDT }; /** Total number of CPU cores in the H3 SoC */ @@ -141,6 +143,7 @@ struct AwH3State { AWI2CState r_twi; AwSun8iEmacState emac; AwRtcState rtc; + AwWdtState wdt; GICState gic; MemoryRegion sram_a1; MemoryRegion sram_a2; diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c index 69d0ad6f50e..f05afddf7e0 100644 --- a/hw/arm/allwinner-h3.c +++ b/hw/arm/allwinner-h3.c @@ -49,6 +49,7 @@ const hwaddr allwinner_h3_memmap[] = { [AW_H3_DEV_OHCI3] = 0x01c1d400, [AW_H3_DEV_CCU] = 0x01c20000, [AW_H3_DEV_PIT] = 0x01c20c00, + [AW_H3_DEV_WDT] = 0x01c20ca0, [AW_H3_DEV_UART0] = 0x01c28000, [AW_H3_DEV_UART1] = 0x01c28400, [AW_H3_DEV_UART2] = 0x01c28800, @@ -234,6 +235,8 @@ static void allwinner_h3_init(Object *obj) object_initialize_child(obj, "twi1", &s->i2c1, TYPE_AW_I2C_SUN6I); object_initialize_child(obj, "twi2", &s->i2c2, TYPE_AW_I2C_SUN6I); object_initialize_child(obj, "r_twi", &s->r_twi, TYPE_AW_I2C_SUN6I); + + object_initialize_child(obj, "wdt", &s->wdt, TYPE_AW_WDT_SUN6I); } static void allwinner_h3_realize(DeviceState *dev, Error **errp) @@ -453,6 +456,11 @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->r_twi), 0, qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_R_TWI)); + /* WDT */ + sysbus_realize(SYS_BUS_DEVICE(&s->wdt), &error_fatal); + sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->wdt), 0, + s->memmap[AW_H3_DEV_WDT], 1); + /* Unimplemented devices */ for (i = 0; i < ARRAY_SIZE(unimplemented); i++) { create_unimplemented_device(unimplemented[i].device_name, diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 338dabce427..91636ab460c 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -337,6 +337,7 @@ config ALLWINNER_H3 select ALLWINNER_A10_PIT select ALLWINNER_SUN8I_EMAC select ALLWINNER_I2C + select ALLWINNER_WDT select SERIAL select ARM_TIMER select ARM_GIC From patchwork Thu Apr 20 10:04:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 675607 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a41:0:0:0:0:0 with SMTP id v1csp221786wrs; Thu, 20 Apr 2023 03:08:37 -0700 (PDT) X-Google-Smtp-Source: AKy350bylofCb/jhmntK160Om+SX9Zqk14cvCp5NapvthxWLV8jFAuB0EdiF5oL1kg5TkuQRFDf9 X-Received: by 2002:a05:6214:124c:b0:5cd:1adc:30e2 with SMTP id r12-20020a056214124c00b005cd1adc30e2mr1070810qvv.11.1681985317248; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id o2-20020a5d58c2000000b002fe522117fdsm1556388wrf.36.2023.04.20.03.05.02 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Apr 2023 03:05:02 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 06/21] tests/avocado: Add reboot tests to Cubieboard Date: Thu, 20 Apr 2023 11:04:41 +0100 Message-Id: <20230420100456.944969-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230420100456.944969-1-peter.maydell@linaro.org> References: <20230420100456.944969-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Strahinja Jankovic Cubieboard tests end with comment "reboot not functioning; omit test". Fix this so reboot is done at the end of each test. Signed-off-by: Strahinja Jankovic Reviewed-by: Niek Linnenbank Tested-by: Niek Linnenbank Message-id: 20230326202256.22980-5-strahinja.p.jankovic@gmail.com Signed-off-by: Peter Maydell --- tests/avocado/boot_linux_console.py | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/tests/avocado/boot_linux_console.py b/tests/avocado/boot_linux_console.py index 574609bf43b..c0675809e64 100644 --- a/tests/avocado/boot_linux_console.py +++ b/tests/avocado/boot_linux_console.py @@ -581,7 +581,10 @@ def test_arm_cubieboard_initrd(self): 'Allwinner sun4i/sun5i') exec_command_and_wait_for_pattern(self, 'cat /proc/iomem', 'system-control@1c00000') - # cubieboard's reboot is not functioning; omit reboot test. + exec_command_and_wait_for_pattern(self, 'reboot', + 'reboot: Restarting system') + # Wait for VM to shut down gracefully + self.vm.wait() def test_arm_cubieboard_sata(self): """ @@ -625,7 +628,10 @@ def test_arm_cubieboard_sata(self): 'Allwinner sun4i/sun5i') exec_command_and_wait_for_pattern(self, 'cat /proc/partitions', 'sda') - # cubieboard's reboot is not functioning; omit reboot test. + exec_command_and_wait_for_pattern(self, 'reboot', + 'reboot: Restarting system') + # Wait for VM to shut down gracefully + self.vm.wait() @skipUnless(os.getenv('AVOCADO_ALLOW_LARGE_STORAGE'), 'storage limited') def test_arm_cubieboard_openwrt_22_03_2(self): @@ -672,7 +678,10 @@ def test_arm_cubieboard_openwrt_22_03_2(self): exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo', 'Allwinner sun4i/sun5i') - # cubieboard's reboot is not functioning; omit reboot test. + exec_command_and_wait_for_pattern(self, 'reboot', + 'reboot: Restarting system') + # Wait for VM to shut down gracefully + self.vm.wait() @skipUnless(os.getenv('AVOCADO_TIMEOUT_EXPECTED'), 'Test might timeout') def test_arm_quanta_gsj(self): From patchwork Thu Apr 20 10:04:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 675595 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a41:0:0:0:0:0 with SMTP id v1csp220775wrs; Thu, 20 Apr 2023 03:06:29 -0700 (PDT) X-Google-Smtp-Source: AKy350ZEJnFMJgE81AT905DVpb9AkdINOZH3TeWYPyeVGC2bzGNuDidaRcrfFfQm+o5vNaYGGue+ X-Received: by 2002:a05:6214:da3:b0:5ea:a3f0:9fd8 with SMTP id h3-20020a0562140da300b005eaa3f09fd8mr3063491qvh.14.1681985189425; Thu, 20 Apr 2023 03:06:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681985189; cv=none; d=google.com; s=arc-20160816; b=B/JmbqJEN7p9vHCViuJ02yE1Tmyt6iTHw6rsacitJx9BqRVhlJhWq9pROno/QnSnHN BsIlduVJQ1iK3ivMLw2kGE6Bl5/xDy2Ta6hqeHia5+szgIKuonrGTRlUEGv8TUYI0EQu GjjPai5Skb46VKBNIlwRd84vd0BShhKQayiB3GgNEL4FpnOMYMQWfKNMQb8P703pzmfA M4+Qw3NpyeHHXxYlJuvRk9tYMza5Yar/re2FIBWldQZ/ao/OxQsSjfy1LIc1J45NZsMz XcXBAr/ZceB5ky2qky+Cs5RhP10zn5LwIJ/5yp9P199JPUpgNGvsXy1Ygkz/uER2Gmbf hW5w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=4z8lBbo4cNMOCR3wyC7AQJyYBl4UvmsiUQL0/yuq4gI=; b=x8eEjdJHWQZj4jAmQQqK83rnrhfIMPGsLItp9MTVLKzI+n5q8E4ivEfvCGQ/qvFwAV nN64HDrlNCOYleUMtyZUYdtYn5Z+ioTqhmE10TmrHjx0tB8iO4MzcqR7AdtsymMW/KhB uvn9TFyGv3Yw/FXAofkzqnh3mLQxjo0lqh9ZfNyED6dX4rQF90cX70v/XJ0p6i43w7/z GHf8aki40wUYu+QU13195S7k/cFtotP8K9msRcvascTz2oh5KftiygPs+GNBAoYMGM3X Gfaa/sy9+Hf7irl0e57zACRZKjSRFcgsUdCynCySLJHElpKunMmf0uKGo+Q60aZdfZAc ATHw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HRhMK0k1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id o2-20020a5d58c2000000b002fe522117fdsm1556388wrf.36.2023.04.20.03.05.02 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Apr 2023 03:05:02 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/21] hw/timer/imx_epit: don't shadow variable Date: Thu, 20 Apr 2023 11:04:42 +0100 Message-Id: <20230420100456.944969-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230420100456.944969-1-peter.maydell@linaro.org> References: <20230420100456.944969-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Axel Heider Fix issue reported by Coverity. Signed-off-by: Axel Heider Message-id: 168070611775.20412.2883242077302841473-1@git.sr.ht Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/timer/imx_epit.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c index 3a869782bcd..0821c62cd1c 100644 --- a/hw/timer/imx_epit.c +++ b/hw/timer/imx_epit.c @@ -179,7 +179,7 @@ static void imx_epit_update_compare_timer(IMXEPITState *s) * the compare value. Otherwise it may fire at most once in the * current round. */ - bool is_oneshot = (limit >= s->cmp); + is_oneshot = (limit >= s->cmp); if (counter >= s->cmp) { /* The compare timer fires in the current round. */ counter -= s->cmp; From patchwork Thu Apr 20 10:04:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 675601 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a41:0:0:0:0:0 with SMTP id v1csp221381wrs; Thu, 20 Apr 2023 03:07:42 -0700 (PDT) X-Google-Smtp-Source: AKy350ZJWPN8OXi/YArrLO+xMwlMEQ2Dz5isWkqkSmIXnglJVGZEH3MZ0RWfWxr+YTzqQyqubyTt X-Received: by 2002:a05:6214:2aa4:b0:5ef:5481:595 with SMTP id js4-20020a0562142aa400b005ef54810595mr2656516qvb.0.1681985262696; Thu, 20 Apr 2023 03:07:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681985262; cv=none; d=google.com; s=arc-20160816; b=IdjAWf/6wRWizjqDknwNxJ4mmVj1SMXbKGlk+UDUFW04mwvVioRcrGm9Ws0ZGrIHva 7TB+RmrLbNEkepaIz7OEBddh5j9FFOHdKN22FF46d567hhpP4x/CONVV5RrZygz4mnPQ KVTshbawF7wuPIwgOhclgaNvN7v1wNoRx7rSImydJBJNOEn6ZeCWIVr3FE2gDglsPe5R Mp4tImTin6AiuIiXHeU0B/5VfTMetwtC/mk49SHRNyOHFJANRc1pceGmRvfTwGBR1D3G nLbbmbWMILh6LFBnj8BUDNA41Q+4VARvhl2ETA7Cn5OGZDORXBgAlc2Ai5ves3urXkik j9Dg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=EjMl5vexxEGO4PAe7d3muxw4Zdgc0H+6hNltDpoCeUI=; b=nFEoBaP8AkWbbJKoOcST0fSTgmvJkjiN3qsw6eoPNWvr0KhK3CD3Jg05ziqEAF9Df6 iHB8tNP0C3d2u6xj/bXIjYs3x850p4lTs1cXw5bhlphacLW03B0q8AJQfBUMgVh7rAox qbEdw4c3eBS9u5z6DaRL/K/0rywmqiEs+gNrNDq4Epwh2yW11/0tH/9KA8pGAhLiDLuQ UraNsdqsWa18zxHVP6DiykuT47BrolBoysstMqvi8xQJqDz4Vn3GYjOJJFx0Bf4sCbQJ 32Jb81sFjWKCNRPusOG5JKD6j06a2mD3j/BE16qDI9MGxapBfzv1t4DzOubPKzL7LzDZ EiRA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=nZ8QkaA0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id o2-20020a5d58c2000000b002fe522117fdsm1556388wrf.36.2023.04.20.03.05.03 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Apr 2023 03:05:03 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/21] hw/timer/imx_epit: fix limit check Date: Thu, 20 Apr 2023 11:04:43 +0100 Message-Id: <20230420100456.944969-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230420100456.944969-1-peter.maydell@linaro.org> References: <20230420100456.944969-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Axel Heider Fix the limit check. If the limit is less than the compare value, the timer can never reach this value, thus it will never fire. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1491 Signed-off-by: Axel Heider Message-id: 168070611775.20412.2883242077302841473-2@git.sr.ht Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/timer/imx_epit.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c index 0821c62cd1c..640e4399c24 100644 --- a/hw/timer/imx_epit.c +++ b/hw/timer/imx_epit.c @@ -179,7 +179,7 @@ static void imx_epit_update_compare_timer(IMXEPITState *s) * the compare value. Otherwise it may fire at most once in the * current round. */ - is_oneshot = (limit >= s->cmp); + is_oneshot = (limit < s->cmp); if (counter >= s->cmp) { /* The compare timer fires in the current round. */ counter -= s->cmp; From patchwork Thu Apr 20 10:04:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 675605 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a41:0:0:0:0:0 with SMTP id v1csp221629wrs; Thu, 20 Apr 2023 03:08:16 -0700 (PDT) X-Google-Smtp-Source: AKy350Zcw8KzSvLzQTlqrN+mh/sXp4OKwHZjudkBEzYOqRAjjde7/6gQtWsxuw/ZgbPkGKkHUNDw X-Received: by 2002:a05:6214:e4e:b0:5ef:4ecb:cf9d with SMTP id o14-20020a0562140e4e00b005ef4ecbcf9dmr1070048qvc.6.1681985296351; Thu, 20 Apr 2023 03:08:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681985296; cv=none; d=google.com; s=arc-20160816; b=wb2vWKohvs4VEaBY9hEk2/nYWzG+RFnzAmGuylwHtduTwn604mdEQFMorUT34NZmUG ZdNeEdyRFCGt3xAlDNbVxp4HhLZVoHOWX600q1ZWke46O8ylKOr19j3LeJBLICHcZKg8 +BQv5mc2rnJtNKwh+JuPf1+S6xe9tcoFIlKmtk+WybIZBk14MIxeANUjBBYSeh/xHdqp IfZsV52X0t6ov0El3PaC5oNWK2W6VmZCVf8uzGnMVr3EocOdvWhrziWGu6QMSv/Isxam Eya6ZQsT6gD2ykSs+fOJtxuR6ViCMzJkq/dcPjyIK02WKA0ahkqLNl7+OpYrJDJVk0SP On8A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=xejyZEcnXPcOcrIXCJsdEKcNfQCMmDuIs1Hj5HcWKBo=; b=m/SeBnqyL8Z6+oWdNyeU+2NdFeVEp6HWX6y8dVeEJcobYdgorIoXNK5ZDD9kRbmOwL 5REYRXRrFaGF6OtwSI+wXBm9JkhqMhF3u2ACLBy7yc1BvHn2fMr8enJLPB6mO/mxRxiK 9MN90ctbGKJhEVkL3PQRlRel6HMji86ZTvQiP9absyz9nVpR9zWBPZ8rZRC3DLTMr14V xoIVHBnubrkqAjm2hfjrlJmF8QFakPWUcnzoLNp/m+vJmc1jHqCzmj2PBL6yahlvGfjJ /NZpr0gM5eizWDWW58EgP3xV8GcOPRoEp3/3ks6Iu/sKJRHs2jBGxSlOtO8Udvq27Crn HFBw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ENAYuJWx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id o2-20020a5d58c2000000b002fe522117fdsm1556388wrf.36.2023.04.20.03.05.04 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Apr 2023 03:05:04 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/21] target/arm: Remove KVM AArch32 CPU definitions Date: Thu, 20 Apr 2023 11:04:44 +0100 Message-Id: <20230420100456.944969-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230420100456.944969-1-peter.maydell@linaro.org> References: <20230420100456.944969-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Missed in commit 80485d88f9 ("target/arm: Restrict v7A TCG cpus to TCG accel"). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20230405100848.76145-2-philmd@linaro.org Signed-off-by: Peter Maydell --- target/arm/kvm-consts.h | 9 +++------ target/arm/cpu_tcg.c | 2 -- 2 files changed, 3 insertions(+), 8 deletions(-) diff --git a/target/arm/kvm-consts.h b/target/arm/kvm-consts.h index 09967ec5e64..7c6adc14f6e 100644 --- a/target/arm/kvm-consts.h +++ b/target/arm/kvm-consts.h @@ -124,13 +124,10 @@ MISMATCH_CHECK(QEMU_PSCI_RET_INTERNAL_FAILURE, PSCI_RET_INTERNAL_FAILURE); MISMATCH_CHECK(QEMU_PSCI_RET_NOT_PRESENT, PSCI_RET_NOT_PRESENT); MISMATCH_CHECK(QEMU_PSCI_RET_DISABLED, PSCI_RET_DISABLED); -/* Note that KVM uses overlapping values for AArch32 and AArch64 - * target CPU numbers. AArch32 targets: +/* + * Note that KVM uses overlapping values for AArch32 and AArch64 + * target CPU numbers. AArch64 targets: */ -#define QEMU_KVM_ARM_TARGET_CORTEX_A15 0 -#define QEMU_KVM_ARM_TARGET_CORTEX_A7 1 - -/* AArch64 targets: */ #define QEMU_KVM_ARM_TARGET_AEM_V8 0 #define QEMU_KVM_ARM_TARGET_FOUNDATION_V8 1 #define QEMU_KVM_ARM_TARGET_CORTEX_A57 2 diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index df0c45e523b..1911d7ec47f 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -546,7 +546,6 @@ static void cortex_a7_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_EL2); set_feature(&cpu->env, ARM_FEATURE_EL3); set_feature(&cpu->env, ARM_FEATURE_PMU); - cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7; cpu->midr = 0x410fc075; cpu->reset_fpsid = 0x41023075; cpu->isar.mvfr0 = 0x10110222; @@ -595,7 +594,6 @@ static void cortex_a15_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_EL2); set_feature(&cpu->env, ARM_FEATURE_EL3); set_feature(&cpu->env, ARM_FEATURE_PMU); - cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15; /* r4p0 cpu, not requiring expensive tlb flush errata */ cpu->midr = 0x414fc0f0; cpu->revidr = 0x0; From patchwork Thu Apr 20 10:04:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 675611 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a41:0:0:0:0:0 with SMTP id v1csp222086wrs; Thu, 20 Apr 2023 03:09:15 -0700 (PDT) X-Google-Smtp-Source: AKy350ZsotfHxbeeOQmusuDfVPC6LXrJDLSJ/nKmwQZbCqfbw1GkMKPervBdJwmgGWhaKcJAz8tm X-Received: by 2002:ad4:5f0f:0:b0:5e9:9eb:e026 with SMTP id fo15-20020ad45f0f000000b005e909ebe026mr1023653qvb.29.1681985355391; Thu, 20 Apr 2023 03:09:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681985355; cv=none; d=google.com; s=arc-20160816; b=zZ/WgaaP1bomGEaN3ZOYkmQgl9oX0ebpsauPMaxtqN4RhoQzvnn3noM8JmM5rqJDZc VGMhluNx3C2VEy9TZhPV/Ma51s3o47KsBgWqqIHgnPcSc+nA4iSot/uC3yLI/pXfBXOC XeQDb5/N3i30sNYChuGUp+2O5BMcTSImrXI2Q4DiLsbPlrUpVQ907gexgQsIGA9qkb2x KCNIDTw9rTepxNe+G0/YOR5z5aikFbT+OM25mefyplATy3VUDAaIXgj7dPr2jg0/9jiX ymJ2kWRgF8h26X1YYI38Yfr2CsuFxD59WQDdQTTggY2DSqJdCDv6oeMYci5s3i5QUJvR doJQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=gk+qtdkGjNiXdrXuOW9NlMvlVmOSEkalFiEAMg6KIvw=; b=0OdCpwLGQl4QfZeMscZVoaMYzoQ+V9wHmfd5elQzXkfP7N3asS5toDI9xGp7U77lqh BazW1bR97C3est2SHyqq7kdTtkUAg3o6N6ZfJnB1PPBi4RC9Wkr8L+7QJSoSlXDYGfqw OdweY4M/rOH8PvvRv5+vJsVvysfWO84RAwLP07ByyEWrVyYMdwZ6AyTiR0pFOtyF0h/e kqysPaKgDvkwVOSQdykN1zVU8uCmynjRNpkV3JLIUF3JCxGNKnnnC0dTpZombsSPZ9Wc z9zi2u4qfumw02Wfn1YNVEeiLXH2Z8pAKvvJ0HKxrgJnU2pf3LfC+Z3ksjKjWZcdlsYV a+YQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kC3QU6Th; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id o2-20020a5d58c2000000b002fe522117fdsm1556388wrf.36.2023.04.20.03.05.04 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Apr 2023 03:05:05 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 10/21] hw/arm/virt: Restrict Cortex-A7 check to TCG Date: Thu, 20 Apr 2023 11:04:45 +0100 Message-Id: <20230420100456.944969-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230420100456.944969-1-peter.maydell@linaro.org> References: <20230420100456.944969-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé The Cortex-A7 core is only available when TCG is enabled (see commit 80485d88f9 "target/arm: Restrict v7A TCG cpus to TCG accel"). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20230405100848.76145-3-philmd@linaro.org Signed-off-by: Peter Maydell --- hw/arm/virt.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 4983f5fc93a..bdf3d76cc43 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -204,7 +204,9 @@ static const int a15irqmap[] = { }; static const char *valid_cpus[] = { +#ifdef CONFIG_TCG ARM_CPU_TYPE_NAME("cortex-a7"), +#endif ARM_CPU_TYPE_NAME("cortex-a15"), ARM_CPU_TYPE_NAME("cortex-a35"), ARM_CPU_TYPE_NAME("cortex-a53"), From patchwork Thu Apr 20 10:04:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 675609 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a41:0:0:0:0:0 with SMTP id v1csp221932wrs; Thu, 20 Apr 2023 03:08:56 -0700 (PDT) X-Google-Smtp-Source: AKy350ayhtCBh2sw3Z3ZiywxIGqjEuuXMKbkvi2bSqkdvv5R3f5aPFYLDySHDNt845VDXvBvy9Er X-Received: by 2002:ac8:5ac3:0:b0:3e9:cb0:f7c3 with SMTP id d3-20020ac85ac3000000b003e90cb0f7c3mr963666qtd.37.1681985336503; Thu, 20 Apr 2023 03:08:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681985336; cv=none; d=google.com; s=arc-20160816; b=kn03wbBiitmMsm2Mrm2Ahgi2lMc/8zFmmgk29Odo0Geme0WtfjGmlMXaNPm0/aIK4N cWXFeTypK0QJTDhiTonE4vNt94yRwQLZUiqurCPcI/Vb2COMj3lxKDDdOFAy3/HCnyNo uE9ZgMzw+CrGr+1iucohTm4mnqmTYn1z9Ywu9FJB5+Q0Dnf8MhLPfyJH1lmXQtwZNco0 Ayy0wNEz7Z6LT2C6TJ8L2RzWYXHyfBaOhq5AJBOgE+Hj1ahBqSprTLRD1ItyETvxLqtR F8lRhuwD7JPMt4tjUEKgPqcQjAJj327kJPZ7s/CF/0ULqubUjrSg4aSKrD1qf/h1pMW/ TX9A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=UBHmKP2QWvbgSGiIjbO0DHXHxUNpy1cA3E2msdtGyEU=; b=0EUKAtxmazdpfEX2nRVaRRd1LZXEPUQesG7zfA1Z3WzLVSxAqnS6lWBnBC89wlcqxb FrxCuaN7OL43m2rIz0Q/ODYLZMjRUR8zC0WRFTD5BVsM4dziUys/v3nikLi3I0XH51DK u4KNEPKJOZvplv3I/MsHhH4vqM7bSqGxJnzdy0x/X6g7m01kXZy3X++j4ZEfSFwjuxMC AIkGdDAhDzf8+yIjLHwp1pVZXgoll1z1ljAbGveIc36+mvTPAmv0AOBrOilyjeEd+kz5 VyQCNg7Y1h1Me12RCl8+04CGUjSZBZWRm8ZwG3dk5zjG25+qQB8b1p41QRyh6fiMCihP efvQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IMHdiBul; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id o2-20020a5d58c2000000b002fe522117fdsm1556388wrf.36.2023.04.20.03.05.05 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Apr 2023 03:05:05 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/21] target/arm: Initialize debug capabilities only once Date: Thu, 20 Apr 2023 11:04:46 +0100 Message-Id: <20230420100456.944969-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230420100456.944969-1-peter.maydell@linaro.org> References: <20230420100456.944969-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Akihiko Odaki kvm_arm_init_debug() used to be called several times on a SMP system as kvm_arch_init_vcpu() calls it. Move the call to kvm_arch_init() to make sure it will be called only once; otherwise it will overwrite pointers to memory allocated with the previous call and leak it. Fixes: e4482ab7e3 ("target-arm: kvm - add support for HW assisted debug") Suggested-by: Philippe Mathieu-Daudé Signed-off-by: Akihiko Odaki Message-id: 20230405153644.25300-1-akihiko.odaki@daynix.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/kvm_arm.h | 8 ++++++++ target/arm/kvm.c | 2 ++ target/arm/kvm64.c | 18 ++++-------------- 3 files changed, 14 insertions(+), 14 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 99017b635ce..330fbe5c722 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -18,6 +18,14 @@ #define KVM_ARM_VGIC_V2 (1 << 0) #define KVM_ARM_VGIC_V3 (1 << 1) +/** + * kvm_arm_init_debug() - initialize guest debug capabilities + * @s: KVMState + * + * Should be called only once before using guest debug capabilities. + */ +void kvm_arm_init_debug(KVMState *s); + /** * kvm_arm_vcpu_init: * @cs: CPUState diff --git a/target/arm/kvm.c b/target/arm/kvm.c index f022c644d2f..84da49332c4 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -280,6 +280,8 @@ int kvm_arch_init(MachineState *ms, KVMState *s) } } + kvm_arm_init_debug(s); + return ret; } diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 1197253d12f..810db33ccbd 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -74,24 +74,16 @@ GArray *hw_breakpoints, *hw_watchpoints; #define get_hw_bp(i) (&g_array_index(hw_breakpoints, HWBreakpoint, i)) #define get_hw_wp(i) (&g_array_index(hw_watchpoints, HWWatchpoint, i)) -/** - * kvm_arm_init_debug() - check for guest debug capabilities - * @cs: CPUState - * - * kvm_check_extension returns the number of debug registers we have - * or 0 if we have none. - * - */ -static void kvm_arm_init_debug(CPUState *cs) +void kvm_arm_init_debug(KVMState *s) { - have_guest_debug = kvm_check_extension(cs->kvm_state, + have_guest_debug = kvm_check_extension(s, KVM_CAP_SET_GUEST_DEBUG); - max_hw_wps = kvm_check_extension(cs->kvm_state, KVM_CAP_GUEST_DEBUG_HW_WPS); + max_hw_wps = kvm_check_extension(s, KVM_CAP_GUEST_DEBUG_HW_WPS); hw_watchpoints = g_array_sized_new(true, true, sizeof(HWWatchpoint), max_hw_wps); - max_hw_bps = kvm_check_extension(cs->kvm_state, KVM_CAP_GUEST_DEBUG_HW_BPS); + max_hw_bps = kvm_check_extension(s, KVM_CAP_GUEST_DEBUG_HW_BPS); hw_breakpoints = g_array_sized_new(true, true, sizeof(HWBreakpoint), max_hw_bps); return; @@ -920,8 +912,6 @@ int kvm_arch_init_vcpu(CPUState *cs) } cpu->mp_affinity = mpidr & ARM64_AFFINITY_MASK; - kvm_arm_init_debug(cs); - /* Check whether user space can specify guest syndrome value */ kvm_arm_init_serror_injection(cs); From patchwork Thu Apr 20 10:04:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 675613 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a41:0:0:0:0:0 with SMTP id v1csp222173wrs; Thu, 20 Apr 2023 03:09:27 -0700 (PDT) X-Google-Smtp-Source: AKy350apy1CeGHL6PMN//Ujhd/UYOtkNXo+4A40Muklf31wOLQ9ZX60Owq+CvpUIeb/Vp4DIGWPy X-Received: by 2002:ad4:5969:0:b0:5e8:979f:2e49 with SMTP id eq9-20020ad45969000000b005e8979f2e49mr977989qvb.41.1681985367599; Thu, 20 Apr 2023 03:09:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681985367; cv=none; d=google.com; s=arc-20160816; b=gblcI7cjbq+XUwQgeejdygF3XdoJMdb5XxVuonPygZchSQBLiB0LH0eIsoTw4CxjVf wT9f8TWkautMNI/1KLlDFn4GqOSQVYErb8EHre4L2H4FhwQqLSN00/s6dCiBAC1WvfFj 7i9lI6uxz/GLbZ2Y3HNiw/J8YUzmiq9E1l89xaWP3kY0TbFYxdLnGHU5k5wSQ2SvKSNC 2BUH8PdSljz4mQOsz+KOGwECA5vul97ABYeEY5bM/9mGsOdpr7T5/3swkNmKSmh+235O eGXq6Ao8YG2cKEYYZl3XOzUU0+X7TgzBThEDPdYwFzu9guWMPRE0Avj/s8bThuBJtId+ 2fhw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=evM3bJgzg0o01IMtcO3BFkkA5dz04OO5SQWdXeDF5tY=; b=sfwg1uPVWs5PubPD/yVoY4a39vdgb/QyQcXFPgtoryqCH5eFfdrh5PVP3Ycy/j8onH 1Caz64IedCkFtN7tpwfvllB9bLZtGzW4w1ojfACYIDKHLd4baBM2/Ci/+q8hD6v67MSN /6dr42RsCmpeE+BPAFFAsptoRhBRzMirVlYKajdoHJ+RbKxk4nA5gJBtziix2kc5scPv OV2+9TjyJI71YpBmU9oQxR/Js4dTXCEIA0UyfxYEIKPkiDn0o/GbPiBKq/QwQgjUpgMp 2hbctGBbi0kO6xVTwkCsIOd+PTxYPZnqmhbhAoW92l5f01228SLJqkCj16/7bOz5n2uO inVQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=E5kMW4dE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id o2-20020a5d58c2000000b002fe522117fdsm1556388wrf.36.2023.04.20.03.05.05 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Apr 2023 03:05:05 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/21] target/arm: Pass ARMMMUFaultInfo to merge_syn_data_abort() Date: Thu, 20 Apr 2023 11:04:47 +0100 Message-Id: <20230420100456.944969-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230420100456.944969-1-peter.maydell@linaro.org> References: <20230420100456.944969-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org We already pass merge_syn_data_abort() two fields from the ARMMMUFaultInfo struct, and we're about to want to use a third field. Refactor to just pass a pointer to the fault info. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-id: 20230331145045.2584941-2-peter.maydell@linaro.org --- target/arm/tcg/tlb_helper.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c index 31eb77f7df9..1a61adb8a68 100644 --- a/target/arm/tcg/tlb_helper.c +++ b/target/arm/tcg/tlb_helper.c @@ -24,9 +24,9 @@ bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx) } static inline uint32_t merge_syn_data_abort(uint32_t template_syn, + ARMMMUFaultInfo *fi, unsigned int target_el, - bool same_el, bool ea, - bool s1ptw, bool is_write, + bool same_el, bool is_write, int fsc) { uint32_t syn; @@ -43,9 +43,9 @@ static inline uint32_t merge_syn_data_abort(uint32_t template_syn, * ISS encoding for an exception from a Data Abort, the * ISV field. */ - if (!(template_syn & ARM_EL_ISV) || target_el != 2 || s1ptw) { + if (!(template_syn & ARM_EL_ISV) || target_el != 2 || fi->s1ptw) { syn = syn_data_abort_no_iss(same_el, 0, - ea, 0, s1ptw, is_write, fsc); + fi->ea, 0, fi->s1ptw, is_write, fsc); } else { /* * Fields: IL, ISV, SAS, SSE, SRT, SF and AR come from the template @@ -54,7 +54,7 @@ static inline uint32_t merge_syn_data_abort(uint32_t template_syn, */ syn = syn_data_abort_with_iss(same_el, 0, 0, 0, 0, 0, - ea, 0, s1ptw, is_write, fsc, + fi->ea, 0, fi->s1ptw, is_write, fsc, true); /* Merge the runtime syndrome with the template syndrome. */ syn |= template_syn; @@ -117,9 +117,8 @@ void arm_deliver_fault(ARMCPU *cpu, vaddr addr, syn = syn_insn_abort(same_el, fi->ea, fi->s1ptw, fsc); exc = EXCP_PREFETCH_ABORT; } else { - syn = merge_syn_data_abort(env->exception.syndrome, target_el, - same_el, fi->ea, fi->s1ptw, - access_type == MMU_DATA_STORE, + syn = merge_syn_data_abort(env->exception.syndrome, fi, target_el, + same_el, access_type == MMU_DATA_STORE, fsc); if (access_type == MMU_DATA_STORE && arm_feature(env, ARM_FEATURE_V6)) { From patchwork Thu Apr 20 10:04:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 675596 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a41:0:0:0:0:0 with SMTP id v1csp220797wrs; Thu, 20 Apr 2023 03:06:31 -0700 (PDT) X-Google-Smtp-Source: AKy350ZTBJ5pOZTumwgTTGmHQmcnYMDpWLBfJEV1KPp0LFHAkTuHJB5vQVEcefTpNZR7mp7CAYzb X-Received: by 2002:a05:6214:4012:b0:56b:eb95:9a52 with SMTP id kd18-20020a056214401200b0056beb959a52mr780740qvb.15.1681985191621; Thu, 20 Apr 2023 03:06:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681985191; cv=none; d=google.com; s=arc-20160816; b=uozrIYjeE9errOaxoRiIxKX6GLvcWUuQiI0pShWJ9t81DPKAxDtvomujiCbZ1kKrph jYeox1ZDJfgUfC7YR2l/7brEaYkoq06YlRnMOGi9HRZ5J3GdBnyi8hauh6VSlXpp0Vcz gfjmBu18X6gkPsu7Biq8vQvJda8z6Xs4A7utdXfXhPSLZkt1LS2M0QngvHL8IlSqXQuF KnyzWhyXP15iomXT2Wpt8+kzMQSn1bbFEH4Z2iNxr4LQuF/WUL5+O9sFk3AFF7bE1kH2 pwdY/GJ019Qx+RYfmFkJ8NeO2N+eMEkf9s6UVPRfbtwywx2x0Y/91seePN/fi+UKt/5Y df9w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=NO9cU/K25d1+EVnE2I5xYDNNqPgct0OWLItzEhlSFrQ=; b=qX7f7XkfcuqkInArsPytEQY9UxunA+IC1b1+icjcqv5Cy+9BzXOGDOHDG+7ippQIeW 8hEPGffe8+2LTNikCNSuYyuQQl1hcAhFcMKKZGYn0RTHMyI6SZnltifuDyZkvYrZZDdY EKhIf8ovIhS58iJbHTKutZZbU6VR4qw2VBvUkT5jZfp5u1J5M2CfO94Qk3QAQ4T1qxST 5VZDlIwWruW7zO/ZH3iW9E/uoUmtHxV1iAzwkrCuDlgfzeqJCqgPCSMcHQ9vwuD66WM5 3mfpWDKVWs/VEk9Qk6vvzdGOv98zgqxJ0Jottns7bIpZO1Jg6yC1g2g3nDUAaG8fAZGC +V7A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=W4vKKjIw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id o2-20020a5d58c2000000b002fe522117fdsm1556388wrf.36.2023.04.20.03.05.06 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Apr 2023 03:05:06 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/21] target/arm: Don't set ISV when reporting stage 1 faults in ESR_EL2 Date: Thu, 20 Apr 2023 11:04:48 +0100 Message-Id: <20230420100456.944969-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230420100456.944969-1-peter.maydell@linaro.org> References: <20230420100456.944969-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The syndrome value reported to ESR_EL2 should only contain the detailed instruction syndrome information when the fault has been caused by a stage 2 abort, not when the fault was a stage 1 abort (i.e. caused by execution at EL2). We were getting this wrong and reporting the detailed ISV information all the time. Fix the bug by checking fi->stage2. Add a TODO comment noting the cases where we'll have to come back and revisit this when we implement FEAT_LS64 and friends. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230331145045.2584941-3-peter.maydell@linaro.org --- target/arm/tcg/tlb_helper.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c index 1a61adb8a68..d5a89bc5141 100644 --- a/target/arm/tcg/tlb_helper.c +++ b/target/arm/tcg/tlb_helper.c @@ -32,8 +32,9 @@ static inline uint32_t merge_syn_data_abort(uint32_t template_syn, uint32_t syn; /* - * ISV is only set for data aborts routed to EL2 and - * never for stage-1 page table walks faulting on stage 2. + * ISV is only set for stage-2 data aborts routed to EL2 and + * never for stage-1 page table walks faulting on stage 2 + * or for stage-1 faults. * * Furthermore, ISV is only set for certain kinds of load/stores. * If the template syndrome does not have ISV set, we should leave @@ -42,8 +43,14 @@ static inline uint32_t merge_syn_data_abort(uint32_t template_syn, * See ARMv8 specs, D7-1974: * ISS encoding for an exception from a Data Abort, the * ISV field. + * + * TODO: FEAT_LS64/FEAT_LS64_V/FEAT_SL64_ACCDATA: Translation, + * Access Flag, and Permission faults caused by LD64B, ST64B, + * ST64BV, or ST64BV0 insns report syndrome info even for stage-1 + * faults and regardless of the target EL. */ - if (!(template_syn & ARM_EL_ISV) || target_el != 2 || fi->s1ptw) { + if (!(template_syn & ARM_EL_ISV) || target_el != 2 + || fi->s1ptw || !fi->stage2) { syn = syn_data_abort_no_iss(same_el, 0, fi->ea, 0, fi->s1ptw, is_write, fsc); } else { From patchwork Thu Apr 20 10:04:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 675598 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a41:0:0:0:0:0 with SMTP id v1csp220966wrs; Thu, 20 Apr 2023 03:06:51 -0700 (PDT) X-Google-Smtp-Source: AKy350YcR5LNMGKwD1LBDUyxDsK2b57AKNr9bQ74Lq+/dVu+5OEP61w7n9nbwP5EXkWimqatZjJq X-Received: by 2002:ac8:5fd1:0:b0:3d7:1979:829e with SMTP id k17-20020ac85fd1000000b003d71979829emr1032338qta.27.1681985211388; Thu, 20 Apr 2023 03:06:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681985211; cv=none; d=google.com; s=arc-20160816; b=jaaGa1yDd2gX+MCFpeGmUguAa8wAb4jbVnTIoIvGrCEjRdmxcBGYM0hYMgp1JAUWGP rNaW0vVakzroktJuG3GxxUU9e7l0A8qZK1BtQ2M/PaOzg7oZNfeU/9SdTzNnzAD9A4Cq /hUCHywMeqaBlN7MsVOJt708fDB/hiEbHGuiDVJ1ursxTQCUYIlklz5opetNc7vzmtNs 8c/eqHXG108MqMGu6oVScv0rpZCwOl7gvI3YIU5YtsdBTfStbst+EPYf65YX+ncuYC7K 4vgCT5yRAKO8PJCunbSjumOS1Y+AuLaNjovwIDhwiJLnUg+BPPCO45xiahyKzq9IZoCM x8lQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=voz5szJvZiVSo8m5NzDOi1MHXMGYIWpvcJhNz8W52IE=; b=JY7wlC3wo2y5P5owfjgNQePgrj2vFEhXM6TXoIDqCEe9Cyu35fm2J8pkWiYKPuhoBU ayA61/N9BIClWIfR1mOPvHcW5E889p+zm8oLbhCNH7Omk1yNlAPCqabeCz+loLU2c3mr YwXLVSF/ft8pLCMxDFhJp2URjrqTgm5oCPD7+kWBycGGvLJRsfreHxWa5eUhHG2j7Zhc y+AFEvAlpdqHr0HqhIohjQRfAGfSojkQcludbPl8OKoJaqsb2RVTtprIsnKPOKiMTW8i 3mk6x9RJf2OcIvKAV4mRihmIQBlTWdkPhdfKkGWo8hfTx0KpWgHUyNml87LcNYidVJR0 e4Cw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VSojBVv4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id o2-20020a5d58c2000000b002fe522117fdsm1556388wrf.36.2023.04.20.03.05.06 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Apr 2023 03:05:06 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/21] target/arm: Implement FEAT_PAN3 Date: Thu, 20 Apr 2023 11:04:49 +0100 Message-Id: <20230420100456.944969-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230420100456.944969-1-peter.maydell@linaro.org> References: <20230420100456.944969-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org FEAT_PAN3 adds an EPAN bit to SCTLR_EL1 and SCTLR_EL2, which allows the PAN bit to make memory non-privileged-read/write if it is user-executable as well as if it is user-read/write. Implement this feature and enable it in the AArch64 'max' CPU. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230331145045.2584941-4-peter.maydell@linaro.org --- docs/system/arm/emulation.rst | 1 + target/arm/cpu.h | 5 +++++ target/arm/cpu64.c | 2 +- target/arm/ptw.c | 14 +++++++++++++- 4 files changed, 20 insertions(+), 2 deletions(-) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 2062d712610..73389878755 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -56,6 +56,7 @@ the following architecture extensions: - FEAT_MTE3 (MTE Asymmetric Fault Handling) - FEAT_PAN (Privileged access never) - FEAT_PAN2 (AT S1E1R and AT S1E1W instruction variants affected by PSTATE.PAN) +- FEAT_PAN3 (Support for SCTLR_ELx.EPAN) - FEAT_PAuth (Pointer authentication) - FEAT_PMULL (PMULL, PMULL2 instructions) - FEAT_PMUv3p1 (PMU Extensions v3.1) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c097cae9882..d469a2637b3 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3823,6 +3823,11 @@ static inline bool isar_feature_aa64_ats1e1(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 2; } +static inline bool isar_feature_aa64_pan3(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 3; +} + static inline bool isar_feature_aa64_hcx(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HCX) != 0; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 0fb07cc7b6d..735ca541634 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -1302,7 +1302,7 @@ static void aarch64_max_initfn(Object *obj) t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1); /* FEAT_VHE */ t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* FEAT_HPDS */ t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1); /* FEAT_LOR */ - t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* FEAT_PAN2 */ + t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 3); /* FEAT_PAN3 */ t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* FEAT_XNX */ t = FIELD_DP64(t, ID_AA64MMFR1, ETS, 1); /* FEAT_ETS */ t = FIELD_DP64(t, ID_AA64MMFR1, HCX, 1); /* FEAT_HCX */ diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 6d72950a795..bd75da8dbcf 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -947,6 +947,7 @@ static int get_S2prot(CPUARMState *env, int s2ap, int xn, bool s1_is_el0) static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64, int ap, int ns, int xn, int pxn) { + ARMCPU *cpu = env_archcpu(env); bool is_user = regime_is_user(env, mmu_idx); int prot_rw, user_rw; bool have_wxn; @@ -958,8 +959,19 @@ static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64, if (is_user) { prot_rw = user_rw; } else { + /* + * PAN controls can forbid data accesses but don't affect insn fetch. + * Plain PAN forbids data accesses if EL0 has data permissions; + * PAN3 forbids data accesses if EL0 has either data or exec perms. + * Note that for AArch64 the 'user can exec' case is exactly !xn. + * We make the IMPDEF choices that SCR_EL3.SIF and Realm EL2&0 + * do not affect EPAN. + */ if (user_rw && regime_is_pan(env, mmu_idx)) { - /* PAN forbids data accesses but doesn't affect insn fetch */ + prot_rw = 0; + } else if (cpu_isar_feature(aa64_pan3, cpu) && is_aa64 && + regime_is_pan(env, mmu_idx) && + (regime_sctlr(env, mmu_idx) & SCTLR_EPAN) && !xn) { prot_rw = 0; } else { prot_rw = simple_ap_to_rw_prot_is_user(ap, false); From patchwork Thu Apr 20 10:04:50 2023 Content-Type: text/plain; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id o2-20020a5d58c2000000b002fe522117fdsm1556388wrf.36.2023.04.20.03.05.07 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Apr 2023 03:05:07 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 15/21] docs/devel/kconfig.rst: Fix incorrect markup Date: Thu, 20 Apr 2023 11:04:50 +0100 Message-Id: <20230420100456.944969-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230420100456.944969-1-peter.maydell@linaro.org> References: <20230420100456.944969-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In rST markup syntax, the inline markup (*italics*, **bold** and ``monospaced``) must be separated from the surrending text by non-word characters, otherwise it is not interpreted as markup. To force interpretation as markup in the middle of a word, you need to use a backslash-escaped space (which will not appear as a space in the output). Fix a missing backslash-space in this file, which meant that the `` after "select" was output literally and the monospacing was incorrectly extended all the way to the end of the next monospaced word. Signed-off-by: Peter Maydell Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Message-id: 20230411105424.3994585-1-peter.maydell@linaro.org --- docs/devel/kconfig.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/devel/kconfig.rst b/docs/devel/kconfig.rst index cc1a456edf0..ac9453eba90 100644 --- a/docs/devel/kconfig.rst +++ b/docs/devel/kconfig.rst @@ -274,7 +274,7 @@ or commenting out lines in the second group. It is also possible to run QEMU's configure script with the ``--without-default-devices`` option. When this is done, everything defaults -to ``n`` unless it is ``select``ed or explicitly switched on in the +to ``n`` unless it is ``select``\ ed or explicitly switched on in the ``.mak`` files. In other words, ``default`` and ``imply`` directives are disabled. When QEMU is built with this option, the user will probably want to change some lines in the first group, for example like this:: From patchwork Thu Apr 20 10:04:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 675612 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a41:0:0:0:0:0 with SMTP id v1csp222088wrs; Thu, 20 Apr 2023 03:09:15 -0700 (PDT) X-Google-Smtp-Source: AKy350Y4WWCEXM7CiJfq4W3LnlmOjdAUadVJh9mTVKhmISB4Beak2knHfbYeho9QlsCrrmZ9Uk6J X-Received: by 2002:ac8:5d87:0:b0:3e7:ec0b:f63c with SMTP id d7-20020ac85d87000000b003e7ec0bf63cmr947987qtx.33.1681985355550; Thu, 20 Apr 2023 03:09:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681985355; cv=none; d=google.com; s=arc-20160816; b=Ri/OIu25yf8yjpsVlVfchQvK4GAIVjG40qFJfAtB2mkjsfQfblteYqHgvXhWCgX2Vj tARBQQ+gMpIwIemkQWTap5rOmurBO4Qmzy/nlKgJpW4YXa+KpODbd8o9hd33cKRpY8OF KfcQauJ3KPUydmS0dioyzxDCrf/1i1VJRC0lq2a4p5GoYVcpn9T7WvHfFP98gYlX+bJp PlRjhmuNIuKQY5lP8w8L13k5ZCYfVsoHXgBVN5xo5zLGPZls4Qr8MGwIOKsxrJlPTtE2 4zAVlMH/lx/9hVHvEW9CbXrcXbRcENXku+weWgt1PsWh9WyHVPdBKmVANCmuxTQW6mzu deRA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=QXIl1fa++9Ow0aVWNLQPOb6RkM7apUVyviw4bR4/41c=; b=GPhhTBB14uv7aU3nxkifsUGgLJJKkO/vGhn0FMhGaJ+L7oH5bXOYEBbqpBICmGFxOF iIiqP3Ep4v1+fpR3ASteyZEtIQ2mmjVFW2mWM4QA4x27OZ0xeSNF++wIpZtHDT9EcI3b QEswaeeP1EK1xzxFzy7g8cl4iFUVMvPooR6QO+4Z6bZ6u3Ddz907KrA251B4IboKJN3O 5aJz4TzCwGW5a9IwdG/0DYAWEJhmdDrioTKAO9yJh+hQM3xQ/KoR4Euq9Bb9t41cy3uX ig6b+PWBCihO0br8ooZDcw/1esBqpggKEbNSlMKplMVjHyaj4qWnZomegqiYKcp0TZ3n yhuw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cySqbOws; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id o2-20020a5d58c2000000b002fe522117fdsm1556388wrf.36.2023.04.20.03.05.07 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Apr 2023 03:05:07 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 16/21] target/arm: Report pauth information to gdb as 'pauth_v2' Date: Thu, 20 Apr 2023 11:04:51 +0100 Message-Id: <20230420100456.944969-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230420100456.944969-1-peter.maydell@linaro.org> References: <20230420100456.944969-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org So that we can avoid the "older gdb crashes" problem described in commit 5787d17a42f7af4 and which caused us to disable reporting pauth information via the gdbstub, newer gdb is going to implement support for recognizing the pauth information via a new feature name: org.gnu.gdb.aarch64.pauth_v2 Older gdb won't recognize this feature name, so we can re-enable the pauth support under the new name without risking them crashing. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230406150827.3322670-1-peter.maydell@linaro.org --- target/arm/gdbstub.c | 9 ++++----- gdb-xml/aarch64-pauth.xml | 2 +- 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index 13fbe9b0d7e..03b17c814f6 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -521,18 +521,17 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) aarch64_gdb_set_fpu_reg, 34, "aarch64-fpu.xml", 0); } -#if 0 /* - * GDB versions 9 through 12 have a bug which means they will - * crash if they see this XML from QEMU; disable it for the 8.0 - * release, pending a better solution. + * Note that we report pauth information via the feature name + * org.gnu.gdb.aarch64.pauth_v2, not org.gnu.gdb.aarch64.pauth. + * GDB versions 9 through 12 have a bug where they will crash + * if they see the latter XML from QEMU. */ if (isar_feature_aa64_pauth(&cpu->isar)) { gdb_register_coprocessor(cs, aarch64_gdb_get_pauth_reg, aarch64_gdb_set_pauth_reg, 4, "aarch64-pauth.xml", 0); } -#endif #endif } else { if (arm_feature(env, ARM_FEATURE_NEON)) { diff --git a/gdb-xml/aarch64-pauth.xml b/gdb-xml/aarch64-pauth.xml index 24af5f903c1..0a5c566d668 100644 --- a/gdb-xml/aarch64-pauth.xml +++ b/gdb-xml/aarch64-pauth.xml @@ -6,7 +6,7 @@ notice and this notice are preserved. --> - + From patchwork Thu Apr 20 10:04:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 675597 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a41:0:0:0:0:0 with SMTP id v1csp220914wrs; Thu, 20 Apr 2023 03:06:45 -0700 (PDT) X-Google-Smtp-Source: AKy350ZE1b/y0YDU+SeTXT8Osoy9dEJrXpCsRgxQtGnT0w1bX2aPTd3H4iIegk5pw/6Mhn1zSFIz X-Received: by 2002:ac8:7f05:0:b0:3ef:3fcd:3c1c with SMTP id f5-20020ac87f05000000b003ef3fcd3c1cmr716876qtk.63.1681985205195; Thu, 20 Apr 2023 03:06:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681985205; cv=none; d=google.com; s=arc-20160816; b=H/UyoG553gYXbilymQbswNWakCzQthEHaEhSn9AuXNkFYrWFmlThB3dwfw+ZIMWAmr HD5jIevqu8An4u9cxoiYK5ShJ2jh3K3S/VTROGOE2BU9NINuHPHp3MGBxZ8TwBlwyMJT Qag1bVMMVYK6VaqxBSsz1zk2P/cMO6DAAkH0o0TBOKtLgbh0aYQ6JjFIqdvzOxwS6YR6 6KSQgw5HPh5Ra0IEXxCNaSbEu0wnZ1FLOV2FowxfuIckPw0MRQLibaPbAJGZQ9uMjX3J ybbfcTY+fVgAqFCKG6m+ofZ0E8I5zH0IIZJ7+mUJv+Cd1CInZF7VS4evCP6BWGyhJ7+6 h+Ww== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=q8LtUQbrNbIcb7AmK/HYZ5o0bALmmnEK3mbIWEsTZ58=; b=a/35308Zf3IyYFdYr4uah2rgPsl4qzP0dMFzOBfudrEs9SIh2TxUjT52rGGzfNeL8c KeobCpAjwaLpVlagtVbWpBgGvWx72jhRqq6l9KVhrTeai9ENvjhG3OkDDu90cCJ/R83o MpmXDO3lpE9Zte+LgJflH02QTXLMB/LgIt/iEidw1FYumdM3gjitXIPvMRSk8jPSb44/ HeCwxQolg1M52dhOiQDUti89RsinWecpKSVBP0cz1XgE2J2dWQWtkEQyBQrfSOgOnNvk ZQCs64MmiRVXMQdjCDS0EvY9l5eTVY31gxa+09LYXO3yYb92gAe5XQT2i1EUwdUu7VUV jTRQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=yDCp9XmG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id o2-20020a5d58c2000000b002fe522117fdsm1556388wrf.36.2023.04.20.03.05.07 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Apr 2023 03:05:08 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 17/21] hw/net/imx_fec: Support two Ethernet interfaces connected to single MDIO bus Date: Thu, 20 Apr 2023 11:04:52 +0100 Message-Id: <20230420100456.944969-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230420100456.944969-1-peter.maydell@linaro.org> References: <20230420100456.944969-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Guenter Roeck The SOC on i.MX6UL and i.MX7 has 2 Ethernet interfaces. The PHY on each may be connected to separate MDIO busses, or both may be connected on the same MDIO bus using different PHY addresses. Commit 461c51ad4275 ("Add a phy-num property to the i.MX FEC emulator") added support for specifying PHY addresses, but it did not provide support for linking the second PHY on a given MDIO bus to the other Ethernet interface. To be able to support two PHY instances on a single MDIO bus, two properties are needed: First, there needs to be a flag indicating if the MDIO bus on a given Ethernet interface is connected. If not, attempts to read from this bus must always return 0xffff. Implement this property as phy-connected. Second, if the MDIO bus on an interface is active, it needs a link to the consumer interface to be able to provide PHY access for it. Implement this property as phy-consumer. Signed-off-by: Guenter Roeck Message-id: 20230315145248.1639364-2-linux@roeck-us.net Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/hw/net/imx_fec.h | 2 ++ hw/net/imx_fec.c | 27 +++++++++++++++++++++++---- 2 files changed, 25 insertions(+), 4 deletions(-) diff --git a/include/hw/net/imx_fec.h b/include/hw/net/imx_fec.h index e3a8755db92..2d13290c787 100644 --- a/include/hw/net/imx_fec.h +++ b/include/hw/net/imx_fec.h @@ -270,6 +270,8 @@ struct IMXFECState { uint32_t phy_int; uint32_t phy_int_mask; uint32_t phy_num; + bool phy_connected; + struct IMXFECState *phy_consumer; bool is_fec; diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c index c862d965930..5d1f1f104cc 100644 --- a/hw/net/imx_fec.c +++ b/hw/net/imx_fec.c @@ -282,11 +282,19 @@ static uint32_t imx_phy_read(IMXFECState *s, int reg) uint32_t val; uint32_t phy = reg / 32; - if (phy != s->phy_num) { - trace_imx_phy_read_num(phy, s->phy_num); + if (!s->phy_connected) { return 0xffff; } + if (phy != s->phy_num) { + if (s->phy_consumer && phy == s->phy_consumer->phy_num) { + s = s->phy_consumer; + } else { + trace_imx_phy_read_num(phy, s->phy_num); + return 0xffff; + } + } + reg %= 32; switch (reg) { @@ -343,11 +351,19 @@ static void imx_phy_write(IMXFECState *s, int reg, uint32_t val) { uint32_t phy = reg / 32; - if (phy != s->phy_num) { - trace_imx_phy_write_num(phy, s->phy_num); + if (!s->phy_connected) { return; } + if (phy != s->phy_num) { + if (s->phy_consumer && phy == s->phy_consumer->phy_num) { + s = s->phy_consumer; + } else { + trace_imx_phy_write_num(phy, s->phy_num); + return; + } + } + reg %= 32; trace_imx_phy_write(val, phy, reg); @@ -1327,6 +1343,9 @@ static Property imx_eth_properties[] = { DEFINE_NIC_PROPERTIES(IMXFECState, conf), DEFINE_PROP_UINT32("tx-ring-num", IMXFECState, tx_ring_num, 1), DEFINE_PROP_UINT32("phy-num", IMXFECState, phy_num, 0), + DEFINE_PROP_BOOL("phy-connected", IMXFECState, phy_connected, true), + DEFINE_PROP_LINK("phy-consumer", IMXFECState, phy_consumer, TYPE_IMX_FEC, + IMXFECState *), DEFINE_PROP_END_OF_LIST(), }; From patchwork Thu Apr 20 10:04:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 675608 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a41:0:0:0:0:0 with SMTP id v1csp221842wrs; Thu, 20 Apr 2023 03:08:44 -0700 (PDT) X-Google-Smtp-Source: AKy350Z8kMdZVWWd3aUtAJUpv/c3H9Lp/IddHmUXTavgEuS4cdctDiMakWBJvUE5K5AbhWg+9m1M X-Received: by 2002:ad4:5d66:0:b0:5aa:8e3e:496e with SMTP id fn6-20020ad45d66000000b005aa8e3e496emr1017883qvb.34.1681985324181; Thu, 20 Apr 2023 03:08:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681985324; cv=none; d=google.com; s=arc-20160816; b=nyPJHNNqmRGdB/g/NVVsZnTFrcKSdXKm4VKER9xo3ODwstYdhnSVS3/oyCArxbTvb9 4/55L7RvWO8M8Vo62xDQTZbsZALrkr5AccR+uvBc0zFVtZCNb2uL6d0M8pum0uAZCqtd RzRXy+zICFNqVu+U4pQaEA+xNJOMRhFsiPcEr+IeQRMyVChBC3A8UD8LJKJOFaMFq/dI Lr7EuCOkZ3af8opB4534r0lx+YAQ5/3dTyzYbWO/8fUoEFQQiYM0Q26RMCX66ofPQFR3 2BNrOvSmYE1HUhhB+v0kH2oCVpH2EgAuf5HrCAyx5usUIzzJf1yh7UlcmjMdS9NCKP5H YY1A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Pzbn4cqrDD/rPP1zQmiL6uq/uryn5Rqdl4z0KRkcO9U=; b=u96vOftW5CCZ7++/8FazNrNmtuZzzeKcQwa3f8xGRON6H1sE5pHmkRbGJNyzN7vP9K 8rLpJjAYNO/kyY/ZvB24w7nmUjoZZCQWu3h63U8zMZ8qPchlrSD0GVn+AjBh4lAWJsfc cGBLdtaiOYAgTUguLjNPYA3aT+jC4ejkF3eLrwErSqfTXiZmEYUkrPaNRy7W+fJcNoJv ddipQyIEEu+q5P59hSjJ5bTuamdxl/fO24v37H/Ab9xEKn6Wx9GDpQbxZfwKOpaD5i2w nxtpMKuxK5DKhoWv5cCiM0n3ln/YfrM04BE4L102rbrrUBoc9zK1vzMrtIL+s23ylwST J+Rw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=C0sRrYoJ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id o2-20020a5d58c2000000b002fe522117fdsm1556388wrf.36.2023.04.20.03.05.08 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Apr 2023 03:05:08 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 18/21] fsl-imx6ul: Add fec[12]-phy-connected properties Date: Thu, 20 Apr 2023 11:04:53 +0100 Message-Id: <20230420100456.944969-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230420100456.944969-1-peter.maydell@linaro.org> References: <20230420100456.944969-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Guenter Roeck Add fec[12]-phy-connected properties and use it to set phy-connected and phy-consumer properties for imx_fec. Signed-off-by: Guenter Roeck Message-id: 20230315145248.1639364-3-linux@roeck-us.net Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/hw/arm/fsl-imx6ul.h | 1 + hw/arm/fsl-imx6ul.c | 20 ++++++++++++++++++++ 2 files changed, 21 insertions(+) diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h index 1952cb984d6..9ee15ae38d6 100644 --- a/include/hw/arm/fsl-imx6ul.h +++ b/include/hw/arm/fsl-imx6ul.h @@ -89,6 +89,7 @@ struct FslIMX6ULState { MemoryRegion ocram_alias; uint32_t phy_num[FSL_IMX6UL_NUM_ETHS]; + bool phy_connected[FSL_IMX6UL_NUM_ETHS]; }; enum FslIMX6ULMemoryMap { diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c index d88d6cc1c5f..2189dcbb72c 100644 --- a/hw/arm/fsl-imx6ul.c +++ b/hw/arm/fsl-imx6ul.c @@ -407,7 +407,23 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) /* * Ethernet + * + * We must use two loops since phy_connected affects the other interface + * and we have to set all properties before calling sysbus_realize(). */ + for (i = 0; i < FSL_IMX6UL_NUM_ETHS; i++) { + object_property_set_bool(OBJECT(&s->eth[i]), "phy-connected", + s->phy_connected[i], &error_abort); + /* + * If the MDIO bus on this controller is not connected, assume the + * other controller provides support for it. + */ + if (!s->phy_connected[i]) { + object_property_set_link(OBJECT(&s->eth[1 - i]), "phy-consumer", + OBJECT(&s->eth[i]), &error_abort); + } + } + for (i = 0; i < FSL_IMX6UL_NUM_ETHS; i++) { static const hwaddr FSL_IMX6UL_ENETn_ADDR[FSL_IMX6UL_NUM_ETHS] = { FSL_IMX6UL_ENET1_ADDR, @@ -620,6 +636,10 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) static Property fsl_imx6ul_properties[] = { DEFINE_PROP_UINT32("fec1-phy-num", FslIMX6ULState, phy_num[0], 0), DEFINE_PROP_UINT32("fec2-phy-num", FslIMX6ULState, phy_num[1], 1), + DEFINE_PROP_BOOL("fec1-phy-connected", FslIMX6ULState, phy_connected[0], + true), + DEFINE_PROP_BOOL("fec2-phy-connected", FslIMX6ULState, phy_connected[1], + true), DEFINE_PROP_END_OF_LIST(), }; From patchwork Thu Apr 20 10:04:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 675600 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a41:0:0:0:0:0 with SMTP id v1csp221285wrs; Thu, 20 Apr 2023 03:07:32 -0700 (PDT) X-Google-Smtp-Source: AKy350YK2VMX2ofWWm533uxj5sMUM91J7BhFDDrbMZzs5e5HcuUYMLgIrQOpC3XoXq4ww7Lva9bo X-Received: by 2002:a05:6214:240c:b0:5dd:aee7:dffb with SMTP id fv12-20020a056214240c00b005ddaee7dffbmr1158719qvb.22.1681985252545; Thu, 20 Apr 2023 03:07:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681985252; cv=none; d=google.com; s=arc-20160816; b=EBM1hQmwBPXGJN9vDQSPK1tKCHkRjTXmAwQq9ce4KPJhVC21djcVeSO+ReGhsO4JfC xANtpNypjacSpwKoc6uEb1qaCdoxYnrP47Wk1TmZk569yazR2qCv+c6NExOxoBl66NHC le3v2gtJi8snoN6XmZaOclT+OfTPg5ThP5Jow5vV5RyqO7Zagwemx7+/8WsgJRL9e4tr j6Jm5bs+SZGdKoW5h5wmWeJPOR5swg/TU2Tx5F6LFbM28RY9TQicOVOfLIMvVzhKC57K r/ANMymfzFiDKuqdLFRnYbPaDI6tUFkxL5LSHzlkiRjNhSluu3qKT/QWBcDZZPvFvQX0 mwcQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=UUZfejXshrs3SIBhcXosBMyPn1kdvSAUIgMZvHXxREw=; b=icX0iO+R7D/X5sECnA3VqNCXE+peaPzkBJG03/wf7ECAVhHiYN9U3wqki/PGqQzTES xWT7s7WGBsAGE97n1l920FBI9IG7bVzQ8BWOApb6ERG49u2n4msFAXqEDogEkHdL3AZ2 iFg8TltqAn9zxePDoPtCEX/t9DMzsr43kdbgu0caZISCGFoOWC14xPSMdk2sh5vF80Mi sHAW2mzpoKfz6ZXECnC6lguS8MsWjEBIVQoYvybg/evPIxkvDH7RGM3WC6KK0B5sCNbS 51/MOpYEdAfa/DrHuEeDAacS/RYrfDaln93qqgMH3zVGj/AsmpjJu7zwVcNogqv8ciaI LwPA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=q3YQIeeI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id o2-20020a5d58c2000000b002fe522117fdsm1556388wrf.36.2023.04.20.03.05.08 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Apr 2023 03:05:08 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 19/21] arm/mcimx6ul-evk: Set fec1-phy-connected property to false Date: Thu, 20 Apr 2023 11:04:54 +0100 Message-Id: <20230420100456.944969-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230420100456.944969-1-peter.maydell@linaro.org> References: <20230420100456.944969-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Guenter Roeck On mcimx6ul-evk, the MDIO bus is connected to the second Ethernet interface. Set fec1-phy-connected to false to reflect this. Signed-off-by: Guenter Roeck Message-id: 20230315145248.1639364-4-linux@roeck-us.net Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/mcimx6ul-evk.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/arm/mcimx6ul-evk.c b/hw/arm/mcimx6ul-evk.c index d83c3c380e8..3ac1e2ea9b4 100644 --- a/hw/arm/mcimx6ul-evk.c +++ b/hw/arm/mcimx6ul-evk.c @@ -41,6 +41,8 @@ static void mcimx6ul_evk_init(MachineState *machine) object_property_add_child(OBJECT(machine), "soc", OBJECT(s)); object_property_set_uint(OBJECT(s), "fec1-phy-num", 2, &error_fatal); object_property_set_uint(OBJECT(s), "fec2-phy-num", 1, &error_fatal); + object_property_set_bool(OBJECT(s), "fec1-phy-connected", false, + &error_fatal); qdev_realize(DEVICE(s), NULL, &error_fatal); memory_region_add_subregion(get_system_memory(), FSL_IMX6UL_MMDC_ADDR, From patchwork Thu Apr 20 10:04:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 675594 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a41:0:0:0:0:0 with SMTP id v1csp220759wrs; Thu, 20 Apr 2023 03:06:27 -0700 (PDT) X-Google-Smtp-Source: AKy350a5R2+VrdMhEs8rhG89Mobv83pM4BC3ZyYRVyr2hq53nsFXP8oyhcPKSbQMNmzGxeE9brXl X-Received: by 2002:a05:622a:40d:b0:3d2:7f3b:c691 with SMTP id n13-20020a05622a040d00b003d27f3bc691mr1077315qtx.47.1681985187182; Thu, 20 Apr 2023 03:06:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681985187; cv=none; d=google.com; s=arc-20160816; b=sfcTdWrUvxBfrYUpj3ceAz/M89G++INrZrzo9PatnVHcrnSLUY5q+lSlws7wdFaAn8 HNClhhc2y9whZxEsgglAJ5taJNmYblu0jx+xQsB4W8M2KweZb828WoYLsT29v0l+kwuz jwKAvqHUvRDnZHAQpHGTcmrNlekd7UOALe9G772xNEjygcNhTZWAw1WOS2YnRWQbAP/z 2aGM2BX89l6ZPYbgzpqiWLsg1a9q3jlTS8b+q2WAcM6VXBDacPhU22ToJ3LjBhZA4vGp m8zEWS76PlM7JtyGqmEu/IGUkKg/7N77I8DH5GSh+3jPiz+zRT98GpL8PN3tJQYhT9mY BGCw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=SsIzI92Bnfubvao4eevVsX6zp783WFWOJizGT2tAtrE=; b=HFpfspLeJIRKky+CH9Hc+sw8dPbs/ezTmYXtSnIOnEAkTytXjJEEIMpDdEjiPt5vOZ mzhdcHc6b8UGuRzJq+0simZ1fwn0O6xBQZzfzpfHEWGPNnQ/Qzcdv1Dje1y14APR7uaN 603vRcrotzYvqYuAEErM3YyKRALle4wra9bb9FgZQaOS+W1V8yNv8tqTEP0Nu+fjKbGc xnJX6glmlO8j+OjBbMlusDgVwMBwo9RnR1YUMmzMZM85NVLRHb1YmwwWfZCxP5IWYsWP YzpBHcNuSqsvIRFOdbXMqpZWPuvdVo4cbLrP9G4Eydxue1uFWezZ7qiRYg8nrNQfQH1P U+FA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TYsZtb4n; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id o2-20020a5d58c2000000b002fe522117fdsm1556388wrf.36.2023.04.20.03.05.09 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Apr 2023 03:05:09 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 20/21] fsl-imx7: Add fec[12]-phy-connected properties Date: Thu, 20 Apr 2023 11:04:55 +0100 Message-Id: <20230420100456.944969-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230420100456.944969-1-peter.maydell@linaro.org> References: <20230420100456.944969-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Guenter Roeck Add fec[12]-phy-connected properties and use it to set phy-connected and phy-consumer properties for imx_fec. Signed-off-by: Guenter Roeck Message-id: 20230315145248.1639364-5-linux@roeck-us.net Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/hw/arm/fsl-imx7.h | 1 + hw/arm/fsl-imx7.c | 20 ++++++++++++++++++++ 2 files changed, 21 insertions(+) diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h index 355bd8ea838..54ea2f0890a 100644 --- a/include/hw/arm/fsl-imx7.h +++ b/include/hw/arm/fsl-imx7.h @@ -82,6 +82,7 @@ struct FslIMX7State { ChipideaState usb[FSL_IMX7_NUM_USBS]; DesignwarePCIEHost pcie; uint32_t phy_num[FSL_IMX7_NUM_ETHS]; + bool phy_connected[FSL_IMX7_NUM_ETHS]; }; enum FslIMX7MemoryMap { diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c index afc74807990..9e41d4b6772 100644 --- a/hw/arm/fsl-imx7.c +++ b/hw/arm/fsl-imx7.c @@ -395,7 +395,23 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) /* * Ethernet + * + * We must use two loops since phy_connected affects the other interface + * and we have to set all properties before calling sysbus_realize(). */ + for (i = 0; i < FSL_IMX7_NUM_ETHS; i++) { + object_property_set_bool(OBJECT(&s->eth[i]), "phy-connected", + s->phy_connected[i], &error_abort); + /* + * If the MDIO bus on this controller is not connected, assume the + * other controller provides support for it. + */ + if (!s->phy_connected[i]) { + object_property_set_link(OBJECT(&s->eth[1 - i]), "phy-consumer", + OBJECT(&s->eth[i]), &error_abort); + } + } + for (i = 0; i < FSL_IMX7_NUM_ETHS; i++) { static const hwaddr FSL_IMX7_ENETn_ADDR[FSL_IMX7_NUM_ETHS] = { FSL_IMX7_ENET1_ADDR, @@ -601,6 +617,10 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) static Property fsl_imx7_properties[] = { DEFINE_PROP_UINT32("fec1-phy-num", FslIMX7State, phy_num[0], 0), DEFINE_PROP_UINT32("fec2-phy-num", FslIMX7State, phy_num[1], 1), + DEFINE_PROP_BOOL("fec1-phy-connected", FslIMX7State, phy_connected[0], + true), + DEFINE_PROP_BOOL("fec2-phy-connected", FslIMX7State, phy_connected[1], + true), DEFINE_PROP_END_OF_LIST(), }; From patchwork Thu Apr 20 10:04:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 675603 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a41:0:0:0:0:0 with SMTP id v1csp221499wrs; Thu, 20 Apr 2023 03:08:00 -0700 (PDT) X-Google-Smtp-Source: AKy350Z4Brn+XMC2irCJZeUTCoGYf+5+SWboJcmQ5LCPXjoRgrpYuXhwk5x/4ekmH+94KNUkcw/5 X-Received: by 2002:ad4:5d65:0:b0:5ef:8c40:6733 with SMTP id fn5-20020ad45d65000000b005ef8c406733mr1138362qvb.20.1681985280200; Thu, 20 Apr 2023 03:08:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681985280; cv=none; d=google.com; s=arc-20160816; b=LU/3up8+gFmptjOY0YzqyyanN7YKD480WIuLBqRmjoon9OY5TjWpFdTx2GGjlEkJgf xdOnDvJ5wkblWIzzs9J/1QU2+VRROoGz6PqMEM8z8CJfm28I1s9QlzSYCLOZI8b3Wln8 unq5YXnv000JQpsrUxxOEfBsTmfWcvGzH1sKJXm3S9PgkoTkofSKipqrfeG43DnsF2cp ggl2ON20jXGvUx2+a5F9e2Zl/gWeybT6kBDGGAo9XnBnlsT8JdK6vCoyhmCXZu1rvvwT eFvX4frRPi7898rIPcBrY9sXgWMwyaT/H0HpFRQIsxQueJfADvlUcEi9qVxrmybJRWW8 AyqA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=IXETFNmGs9QvQq2m1ZAi/6SAVGC9Nw/XwN7n3Zh6D20=; b=NUb1H+/nTH/zuuuUbSZz/ZHDqgPH21Tx1IZ3X4iWnlRia6G7i1OCMw4kxC4Qb/EfTL tJAm6meoYWLleOSvAAVq/t3/6SEjkRKjgNDLe+I9R9bPdJVttAZrRYNtIiMmbZXAf9Pb 4yFYgBP12DpoAIzIk4199LF+AGMy7zuGjHnWEXnl9rhwW9gZnh+CT2JiXyVshS7tPhO6 7AhAlbEv9eE43iuL7+6zuLH+V4mho7sy/BsrjhhJiTMzrO4jMx4DGqgurFD7ham+SNBj JHjJgqUZ6BWGzjw/NFjUHqZJhCQpvTBhamEnYA3khVYFsoJk5ZNGbGWLwNAYQVh7jvyH VaCQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Hq5RX4Yd; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id o2-20020a5d58c2000000b002fe522117fdsm1556388wrf.36.2023.04.20.03.05.09 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Apr 2023 03:05:09 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 21/21] arm/mcimx7d-sabre: Set fec2-phy-connected property to false Date: Thu, 20 Apr 2023 11:04:56 +0100 Message-Id: <20230420100456.944969-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230420100456.944969-1-peter.maydell@linaro.org> References: <20230420100456.944969-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Guenter Roeck On mcimx7d-sabre, the MDIO bus is connected to the first Ethernet interface. Set fec2-phy-connected to false to reflect this. Signed-off-by: Guenter Roeck Message-id: 20230315145248.1639364-6-linux@roeck-us.net Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/mcimx7d-sabre.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/arm/mcimx7d-sabre.c b/hw/arm/mcimx7d-sabre.c index 6182b15f190..d1778122b64 100644 --- a/hw/arm/mcimx7d-sabre.c +++ b/hw/arm/mcimx7d-sabre.c @@ -41,6 +41,8 @@ static void mcimx7d_sabre_init(MachineState *machine) s = FSL_IMX7(object_new(TYPE_FSL_IMX7)); object_property_add_child(OBJECT(machine), "soc", OBJECT(s)); + object_property_set_bool(OBJECT(s), "fec2-phy-connected", false, + &error_fatal); qdev_realize(DEVICE(s), NULL, &error_fatal); memory_region_add_subregion(get_system_memory(), FSL_IMX7_MMDC_ADDR,