From patchwork Fri May 31 02:13:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suman Anna X-Patchwork-Id: 165474 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp107704ili; Thu, 30 May 2019 19:13:34 -0700 (PDT) X-Google-Smtp-Source: APXvYqwpA9IzclGxvLh7fr8T0DQHjkUAMKFQays3WUB1DtzLzHumKuXJAxSuTyUhIV/BewJCGbU6 X-Received: by 2002:a17:90a:9483:: with SMTP id s3mr6586778pjo.22.1559268814097; Thu, 30 May 2019 19:13:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1559268814; cv=none; d=google.com; s=arc-20160816; b=EWsSgOMOHeqsdvV88xKqQ3RiZ22jE/KDurhqPQaktBwAOuvkZsQsbTZBWaP4CkmD6z zWtA71cw8NK6wikMIsfAgaBb7p3/++WjaL+Rsm+xZex51FeYk7R2RFc3VHqpjQqkFUl0 mkWdUZyZKrvmmAGy34bSXRyVM80sf9CeS74r/rnquEQ0jXZPb9UGqzpj/CxDB7fZHmaT KkqnYzvoJ7sBX/NEPvlJi7BoWiMIXGRyhGUk7PQxphkWK42bWFIuYfM66QtjWmFG6rwR a4D5X+yCUMVWGOW8iECbICd3BTmVg0iJKPB8lLs/xqY9QuTVl9PQY1dHxOHna4AlPxAj tQdg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ihidVVcFNIyittejhS+bbU/Ve3sebgl4qU990HXA5s8=; b=lNCtXnsElHi0aLLX+XNkXbYulJ4okE4D6RDe0xX+AqYVQ6tPUu6Vozx2QmWQR91Yi+ eJRqFDVOxNoSdwnP1aO8CHRajCVPr8QsO75ILM+2rt8H9BzteBH4aDL6/l+DII0ynTZq AWezEtA+woDjjOrSLq4HfvQirnCY3nXSMNnKlUDREfYJertmPXa+YP/jCJFQ3LBFP7o+ oCddU/RNomPsoYJryGktVaxwQVzDPmMFfMNRvhU8gPMITKBkZG+1iSXa5mjkpL8+prWx ISdDIEqscPA2rRJvjsoW6jt+ej4EGFCWaQKpIla3ebIuo4H5nWaR6gFLTcOkJM86kFSt lPdw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=UBaLIbXl; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id i11si4623412plb.416.2019.05.30.19.13.31; Thu, 30 May 2019 19:13:34 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=UBaLIbXl; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726418AbfEaCNa (ORCPT + 7 others); Thu, 30 May 2019 22:13:30 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:60874 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726372AbfEaCN3 (ORCPT ); Thu, 30 May 2019 22:13:29 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x4V2DOXo098765; Thu, 30 May 2019 21:13:24 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1559268804; bh=ihidVVcFNIyittejhS+bbU/Ve3sebgl4qU990HXA5s8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=UBaLIbXlctcH4PNdaixSS3Mbp8yqO0KBGnTQ9FHrZg7p8jKtRYBmC4dX18uUwTGUK ofDRtlgXsXZnq334I1Lkwc4oEhhJUXehInrqx1ebF9G7ql4zH4NWoIPWpetWBGq3n3 s5pToFqLwE3iqO80FvAF5nrOw5yfnyZsuCOTtlzU= Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x4V2DO8k111177 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 30 May 2019 21:13:24 -0500 Received: from DFLE103.ent.ti.com (10.64.6.24) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Thu, 30 May 2019 21:13:24 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Thu, 30 May 2019 21:13:24 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id x4V2DNxG008960; Thu, 30 May 2019 21:13:24 -0500 Received: from localhost (irmo.dhcp.ti.com [128.247.58.153]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id x4V2DNm18132; Thu, 30 May 2019 21:13:23 -0500 (CDT) From: Suman Anna To: Bjorn Andersson , Rob Herring CC: , , , , Suman Anna Subject: [PATCH 2/3] hwspinlock/omap: Add support for TI K3 SoCs Date: Thu, 30 May 2019 21:13:20 -0500 Message-ID: <20190531021321.14025-3-s-anna@ti.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190531021321.14025-1-s-anna@ti.com> References: <20190531021321.14025-1-s-anna@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org A HwSpinlock IP is also present on the newer TI K3 AM65x and J721E family of SoCs within the Main NavSS sub-module. Reuse the existing OMAP Hwspinlock driver to extend the support for this IP on K3 AM65x SoCs as well. The IP has slightly different bit-fields in the SYSCONFIG and SYSSTATUS registers. Signed-off-by: Suman Anna --- drivers/hwspinlock/Kconfig | 2 +- drivers/hwspinlock/omap_hwspinlock.c | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) -- 2.21.0 diff --git a/drivers/hwspinlock/Kconfig b/drivers/hwspinlock/Kconfig index 7869c67e5b6b..37740e992cfa 100644 --- a/drivers/hwspinlock/Kconfig +++ b/drivers/hwspinlock/Kconfig @@ -9,7 +9,7 @@ menuconfig HWSPINLOCK config HWSPINLOCK_OMAP tristate "OMAP Hardware Spinlock device" depends on HWSPINLOCK - depends on ARCH_OMAP4 || SOC_OMAP5 || SOC_DRA7XX || SOC_AM33XX || SOC_AM43XX + depends on ARCH_OMAP4 || SOC_OMAP5 || SOC_DRA7XX || SOC_AM33XX || SOC_AM43XX || ARCH_K3 help Say y here to support the OMAP Hardware Spinlock device (firstly introduced in OMAP4). diff --git a/drivers/hwspinlock/omap_hwspinlock.c b/drivers/hwspinlock/omap_hwspinlock.c index 625844e0abef..a4d7a7bc863a 100644 --- a/drivers/hwspinlock/omap_hwspinlock.c +++ b/drivers/hwspinlock/omap_hwspinlock.c @@ -171,6 +171,7 @@ static int omap_hwspinlock_remove(struct platform_device *pdev) static const struct of_device_id omap_hwspinlock_of_match[] = { { .compatible = "ti,omap4-hwspinlock", }, + { .compatible = "ti,am654-hwspinlock", }, { /* end */ }, }; MODULE_DEVICE_TABLE(of, omap_hwspinlock_of_match); From patchwork Fri May 31 02:13:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suman Anna X-Patchwork-Id: 165476 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp107731ili; Thu, 30 May 2019 19:13:35 -0700 (PDT) X-Google-Smtp-Source: APXvYqxNDJq9u6R/CmdRuheMTC9PyRiTQcBAfw5UNsAin36q8qbRkDe+28YpHEUHCyb7v2j6NMhD X-Received: by 2002:a63:ee0a:: with SMTP id e10mr6447160pgi.28.1559268815795; Thu, 30 May 2019 19:13:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1559268815; cv=none; d=google.com; s=arc-20160816; b=asZehbL5vb4AtjIDlFXf6nTKjCEjEyCEp7/XVB35QOurAfSje6nxd8KE7aIsiLb+fX HXw6GFsW6gxqd4TvLDQHpZ7yJSbBqEBpuNqchc3Bmb9PakTenHNxZNrm0z5LWIDBT/yZ WCIc4Wsmtr2MJXDSsZ2AJ6neKVpZQP8ZuDjQqcgHEIOo3USCf0i0FWc6WYWkF6oDy3/w 0nOR0Fdxx+r8Id+UXo2Cip43UHPZt1FJgJ680KpeiQbyx33zHI1mEMGElfJC8yv3YqW9 fo7B2YRLaSzi5oVNx1tvCgpGkq+Dgp/gA/f7Z9xSpRscex7JZ071w2JSFZHtl4glKdnO 59Mw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=hs354EoGbV73TbB075I8Lanu8CNWjwVr00edQ5IOMWo=; b=Pxjq1yWJpbdwPWNUrh3+Qi/Z+Bx38eMr4/drLM+EU/lz/3hp2pKcQoKKYfzqCKG1Up ijZZ/o1JdElkL2KDY62KlQ2Y6Ac1F6RgCwHfCm0MqyxkObZiVqTLorY4LV9y6rf7sqJq 7qWyqrqwYaTLb72tDI9IiVacU9DHRUKitm1vGAFPcvhe64pZF6SlO9Gs3Bhi/YivQxTV uQIRs7di/dcgtDn0GPAl7OSqWj3jUwX3ktETcuqIEs6NqYfc0B0jj83h8WstmvEII5JP wgxqqxGatU53DeXaX3tXmHIhiCh/LgzvifHre+mfgfuwUXDeMDNBMQpdPu5eVa4vlAUW 9vxw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=FkqaIt0O; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id i11si4623412plb.416.2019.05.30.19.13.35; Thu, 30 May 2019 19:13:35 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=FkqaIt0O; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726543AbfEaCNb (ORCPT + 7 others); Thu, 30 May 2019 22:13:31 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:52674 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726408AbfEaCNb (ORCPT ); Thu, 30 May 2019 22:13:31 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x4V2DOCH105395; Thu, 30 May 2019 21:13:24 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1559268804; bh=hs354EoGbV73TbB075I8Lanu8CNWjwVr00edQ5IOMWo=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=FkqaIt0OwYhrxKB0BgGMX+rrb/5/fpm9FgyaDJfGOD4hXPVJkSb2ydZYWRhfT57sy 4lZGx+1Y+kVEfNECHzqr9rBVHG6uxLEQaJN7ujdmKJdMA7l3xgVRT9apwiznorEZbX 1/C63RG29eiDFbpVypUsGYZ3Bh28CwvPoXD4CNjM= Received: from DLEE113.ent.ti.com (dlee113.ent.ti.com [157.170.170.24]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x4V2DOhR108705 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 30 May 2019 21:13:24 -0500 Received: from DLEE108.ent.ti.com (157.170.170.38) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Thu, 30 May 2019 21:13:24 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Thu, 30 May 2019 21:13:24 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id x4V2DOPO027212; Thu, 30 May 2019 21:13:24 -0500 Received: from localhost (irmo.dhcp.ti.com [128.247.58.153]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id x4V2DOm18136; Thu, 30 May 2019 21:13:24 -0500 (CDT) From: Suman Anna To: Bjorn Andersson , Rob Herring CC: , , , , Suman Anna Subject: [PATCH 3/3] hwspinlock/omap: Add a trace during probe Date: Thu, 30 May 2019 21:13:21 -0500 Message-ID: <20190531021321.14025-4-s-anna@ti.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190531021321.14025-1-s-anna@ti.com> References: <20190531021321.14025-1-s-anna@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add a debug level trace statement in the OMAP HwSpinlock driver probe function to print the number of hwlocks on a successful registration. Signed-off-by: Suman Anna --- drivers/hwspinlock/omap_hwspinlock.c | 3 +++ 1 file changed, 3 insertions(+) -- 2.21.0 diff --git a/drivers/hwspinlock/omap_hwspinlock.c b/drivers/hwspinlock/omap_hwspinlock.c index a4d7a7bc863a..14e1a532ebb5 100644 --- a/drivers/hwspinlock/omap_hwspinlock.c +++ b/drivers/hwspinlock/omap_hwspinlock.c @@ -140,6 +140,9 @@ static int omap_hwspinlock_probe(struct platform_device *pdev) if (ret) goto reg_fail; + dev_dbg(&pdev->dev, "Registered %d locks with HwSpinlock core\n", + num_locks); + return 0; reg_fail: