From patchwork Wed May 29 21:13:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suman Anna X-Patchwork-Id: 165379 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp55694ili; Wed, 29 May 2019 14:13:57 -0700 (PDT) X-Google-Smtp-Source: APXvYqx4A8E3qeNPdSeSzxzf7zXL87cXD0Uom27vNR/QwzwvjOKxpkug6zXnBGLR8G9bgjPkTf4S X-Received: by 2002:a65:430a:: with SMTP id j10mr39742pgq.133.1559164437306; Wed, 29 May 2019 14:13:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1559164437; cv=none; d=google.com; s=arc-20160816; b=cuJ0Zjx6qmulO43PQnGHq33MZGCR5MW3vGXRz+ZwSjgPZPm6usTaoWz6E3S5zZ64ZU fotFWYmebNsp2eJcQ91P7dW9DqMl8QIbJXtxkpLyhFEeUWtUYoKiE2nwtIOltr6TPSvC +KBTvBMBDeaCbVaQQHnJYnv9ZWxlJ4f5llWjVuuZglckN+ty/6sgU9aUW8+L/OnFDKPk az5lWi1yVk/HzCskNrzK2Kinc40zQDoj//jhvCZ7Vbw/2BilIpicYK43b03fJvqZLoBM MVlaGwmE0ZHSYNXE/cezW4Es/deSI5RvYzLDQXqvA7cbqGrg533L0EVMBBYgQBsZS3Px 27jw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=UtfU/8233aUmiqr/3DAdlqIZFtCoTeyL2Sth6JDKYVY=; b=Ab/rJ9h3f3PXBBo6pYgrkXZzcZjPRLvHOH/MC1AXW+Xf62vIDxWoF0z0GzMlsyWffW hoUBxVJGsYWrrwrah5KU9oVKXeQRt6YkJq2/jd3FaD5eeACWISCi7T8qmZLwsfI4xZWd 7sUJ+VJ00uO9z/c06IdqZEK6fh3ESBTkXPxmm37kfGg19kIxOpvY69TQWahVejXah5QA p4HvDc3sAf7QcCdveQgI7R+zidNuMdIsZUqsYfKSip0Cyo8oMQoC4aNIcPf9+Aeb5irj pu5bIY8YnMB95StB+rQcpCbvhf1DOvG+gEW0ahGwo6cgaga0B+/inIZp9z3U/8prSUnL fk4w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=hrzvBo3k; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id u21si587740pjx.58.2019.05.29.14.13.55; Wed, 29 May 2019 14:13:56 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=hrzvBo3k; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726408AbfE2VNz (ORCPT + 7 others); Wed, 29 May 2019 17:13:55 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:51894 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726189AbfE2VNz (ORCPT ); Wed, 29 May 2019 17:13:55 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id x4TLDnc3011365; Wed, 29 May 2019 16:13:49 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1559164429; bh=UtfU/8233aUmiqr/3DAdlqIZFtCoTeyL2Sth6JDKYVY=; h=From:To:CC:Subject:Date; b=hrzvBo3kTOZd3dPKYEcsPSf9u+AYiOc/9/Y8FWHPrfeH775H9jeTU4tTWJ1XA2Gm3 bunCbkZ4wRRu115eAwbK+Mh22QoLTkz2QVHy2xLcAmucSi8oyzWfyCgplznAaPd98G AFj+TB6BEHwAaRqT7Q9hvcrIeSxR5MFcJi7LrWJI= Received: from DFLE106.ent.ti.com (dfle106.ent.ti.com [10.64.6.27]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x4TLDnDI016010 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 29 May 2019 16:13:49 -0500 Received: from DFLE110.ent.ti.com (10.64.6.31) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Wed, 29 May 2019 16:13:49 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Wed, 29 May 2019 16:13:49 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id x4TLDnEu015680; Wed, 29 May 2019 16:13:49 -0500 Received: from localhost (irmo.dhcp.ti.com [128.247.58.153]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id x4TLDnm04056; Wed, 29 May 2019 16:13:49 -0500 (CDT) From: Suman Anna To: Tero Kristo , Nishanth Menon CC: Rob Herring , , , Roger Quadros , Suman Anna Subject: [PATCH] arm64: dts: ti: k3-am65: Add MSMC RAM ranges in interconnect node Date: Wed, 29 May 2019 16:13:44 -0500 Message-ID: <20190529211344.18014-1-s-anna@ti.com> X-Mailer: git-send-email 2.21.0 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Roger Quadros Add the MSCM RAM address space to the ranges property of the cbass_main interconnect node so that the addresses can be translated properly. This fixes the probe failure in the sram driver for the MSMC RAM node. Signed-off-by: Roger Quadros Signed-off-by: Suman Anna --- The following error message is seen without this: [ 0.480261] sram interconnect@100000:sram@70000000: found no memory resource [ 0.487497] sram: probe of interconnect@100000:sram@70000000 failed with error -22 regards Suman arch/arm64/boot/dts/ti/k3-am65.dtsi | 1 + 1 file changed, 1 insertion(+) -- 2.21.0 Acked-by: Nishanth Menon diff --git a/arch/arm64/boot/dts/ti/k3-am65.dtsi b/arch/arm64/boot/dts/ti/k3-am65.dtsi index 50f4be2047a9..68b3f954f1d1 100644 --- a/arch/arm64/boot/dts/ti/k3-am65.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65.dtsi @@ -68,6 +68,7 @@ <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */ <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */ <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */ + <0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* MSMC SRAM */ /* MCUSS Range */ <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>,