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[209.51.188.17]) by mx.google.com with ESMTPS id iy4-20020a0562140f6400b0056ebc773032si2904739qvb.73.2023.04.14.09.05.27 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 14 Apr 2023 09:05:27 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Z86cmet/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pnLuX-0006IZ-3E; Fri, 14 Apr 2023 12:04:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pnLuU-0006Gn-5V for qemu-devel@nongnu.org; Fri, 14 Apr 2023 12:04:26 -0400 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pnLuN-0007uA-Fr for qemu-devel@nongnu.org; Fri, 14 Apr 2023 12:04:25 -0400 Received: by mail-wm1-x333.google.com with SMTP id l10-20020a05600c1d0a00b003f04bd3691eso21024842wms.5 for ; Fri, 14 Apr 2023 09:04:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1681488255; x=1684080255; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jUHq0yTT6mZpyW8ymPG55BvWQqRfjylp1jFh1uUnshs=; b=Z86cmet/oFJLig9vLG0ILm1/FNhYYRfu7A35GrX/shAqhvqcdzEqz52CrVEekTAwIL S7vqSxDS293h99upQmb/0f0z6oJfVc/L2jmw7XvlnkJnVpL9w2xY5SdzsJU7oHtBbQ/f 0ZmHvFaV/D3jn0wRqc1KzHMbywPywnVPFpPM2PauCtRe2tO/TfLoMMEGI8jsOVfXGw16 lFkYf6rCmx2ERV9/xNB33KmSoSoxio1GY1SD+s0S6ceGCEVAcrKdgq0WyRW0+DMWUu6l bkYVsLJrMyVNAJDomEXoHZ0z4matpM6MIIVth4qaVD8kCwVQDDdJGgPIXmYG9QknG3fs ABKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681488255; x=1684080255; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jUHq0yTT6mZpyW8ymPG55BvWQqRfjylp1jFh1uUnshs=; b=LENF2SLkge35pyvyn27lxBrxHk4GXvQc2vKzqVnKsC7YeDhVAE4v1InXPI1FFK/HgY DbPYcu8sGLufLH8UyDFy2zz74FwQnIAaTjdIdJ3pV3kJdX0O1OU9WzuS6XU1hkdywyfV QuYWowjZlFO00DXun6Ts8EVKpXUUTeKxLTLykIy8wzyjv3KKGyNjA3V1iIdEN2wy5Z5A fZSZwYok6fqduEuu4a2kW6d1dsd1/2VIsNILHP+xcn33q6tljYVb7WOdki3Qfq7CeXry 90rSX4wnlJO1EBzw8iManQRUZOkPs3MBobUJdPjB/UItlILzBZ0jhYeDwp9rYETwE6XE lGBA== X-Gm-Message-State: AAQBX9d2fsueOUoWN9iPyl/JvZxxvFcOj0QWAR0kGQf203n8bO7cA5De aYWHaeSeTrf9sHrOgfCJAKPB2w== X-Received: by 2002:a05:600c:2289:b0:3ee:6161:7d98 with SMTP id 9-20020a05600c228900b003ee61617d98mr4732437wmf.16.1681488255598; Fri, 14 Apr 2023 09:04:15 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 8-20020a05600c22c800b003ef71d541cbsm4673752wmg.1.2023.04.14.09.04.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Apr 2023 09:04:15 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Richard Henderson Subject: [PATCH 1/3] target/arm: Don't allow stage 2 page table walks to downgrade to NS Date: Fri, 14 Apr 2023 17:04:11 +0100 Message-Id: <20230414160413.549801-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230414160413.549801-1-peter.maydell@linaro.org> References: <20230414160413.549801-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Bit 63 in a Table descriptor is only the NSTable bit for stage 1 translations; in stage 2 it is RES0. We were incorrectly looking at it all the time. This causes problems if: * the stage 2 table descriptor was incorrectly setting the RES0 bit * we are doing a stage 2 translation in Secure address space for a NonSecure stage 1 regime -- in this case we would incorrectly do an immediate downgrade to NonSecure A bug elsewhere in the code currently prevents us from getting to the second situation, but when we fix that it will be possible. Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/arm/ptw.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 6d72950a795..06865227642 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1403,17 +1403,18 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, descaddrmask &= ~indexmask_grainsize; /* - * Secure accesses start with the page table in secure memory and + * Secure stage 1 accesses start with the page table in secure memory and * can be downgraded to non-secure at any step. Non-secure accesses * remain non-secure. We implement this by just ORing in the NSTable/NS * bits at each step. + * Stage 2 never gets this kind of downgrade. */ tableattrs = is_secure ? 0 : (1 << 4); next_level: descaddr |= (address >> (stride * (4 - level))) & indexmask; descaddr &= ~7ULL; - nstable = extract32(tableattrs, 4, 1); + nstable = !regime_is_stage2(mmu_idx) && extract32(tableattrs, 4, 1); if (nstable) { /* * Stage2_S -> Stage2 or Phys_S -> Phys_NS From patchwork Fri Apr 14 16:04:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 673128 Delivered-To: patch@linaro.org Received: by 2002:adf:fcce:0:0:0:0:0 with SMTP id f14csp261943wrs; Fri, 14 Apr 2023 09:05:02 -0700 (PDT) X-Google-Smtp-Source: AKy350bZreGBhQmYVNn5yWDmNlYyamoW9Q8uEVn3D4kSA1bXL7DRL8tZbPmhp/CmgOAfrWHTcSEA X-Received: by 2002:ac8:5f8c:0:b0:3a8:a84:7ffa with SMTP id j12-20020ac85f8c000000b003a80a847ffamr9720579qta.57.1681488302115; Fri, 14 Apr 2023 09:05:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681488302; cv=none; d=google.com; s=arc-20160816; b=qaWIedDx1zwlhAWarYkE7LtuMA/g5LjpHa81VOTypnngUVe3gJhody65P/+ydPlcWA tfsGXpCeUsrNO1rUeECU/GzlAYNxsyqjK34i8o5NLKsneNDmkm++XCpkr+XAOPbG5bXo uTcSZm41ahZ/f9kWBnbAgxxuXB2j4GXO5EpHfYX7ZJwVIpxR0EMhlc9gf5CBexH7rD9Q Qu3atdNjgcsiq1Ab7Ote1KBqSY5vdiBQ0lKg2z7QmFDOIlo+PxwYccHmTIGClb4wK+TI 9n6vdJyzEQhpbc/kUycJRZ5cD02LFUEHeMYQzSkDA+5e4MOYUIuW/0qPtmtB2sqDSwPa yQnA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=JuAuDSPuE/JnH8NiYlJET7XN0aNFOky+lUCpFOTs4Zw=; b=ht0iNb43X54g2IiAitanbG4M7ogHR1zQBwNVpTILsXnq3LJEDLXAtbSJ07eM6clC9V la7kr0z71/+oOKYsxcgt+yWsX6TJmD2WLm+772D9QpQhS+/7cMBFq77IBj7p/Z79SkcC dyaZHWQrvlKOqbfsNI5s3TmZsowsI9Au0dxzpNd66JpIp8N7/RSAwztM+UtLnydL2yF8 8rwR6rev+19optAfLwq59U409dXlfADlXqR9HMqifka0dMSL9GmNvldeQUwrOETcVi7K EW3fNHk7BtO99D3w2iFJu/SQUcsyqGFNECUpKFpU68NV+VJ/BmTSDXgY6x43q8v0ChPt Uthg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kLOeWaX5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 8-20020a05600c22c800b003ef71d541cbsm4673752wmg.1.2023.04.14.09.04.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Apr 2023 09:04:15 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Richard Henderson Subject: [PATCH 2/3] target/arm: Set ptw->out_secure correctly for stage 2 translations Date: Fri, 14 Apr 2023 17:04:12 +0100 Message-Id: <20230414160413.549801-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230414160413.549801-1-peter.maydell@linaro.org> References: <20230414160413.549801-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In S1_ptw_translate(), we are in one of two situations: (1) translating an S1 page table walk through S2 (2) translating an S2 page table walk through a physical regime In case (1), ptw->in_secure indicates whether S1 is a Secure or NonSecure translation regime. In case (2), ptw->in_secure indicates whether this stage 2 translation is for a Secure IPA or a NonSecure IPA. In particular, because of the VTCR_EL2.NSW and VSTCR_EL2.SW bits, we can be doing a translation of a NonSecure IPA where the page tables are in the Secure space. Correct the setting of the ptw->out_secure value for the regime-is-physical case: * it depends on whether s2_mmu_idx is Phys_S or Phys, not on the value of is_secure * we don't need to look at the VTCR_EL2.NSW and VSTCR.SW bits again here, as we already did that in get_phys_addr_twostage() to set the correct in_ptw_idx This error doesn't currently cause a problem in itself because we are incorrectly setting ptw->in_secure to s2walk_secure in get_phys_addr_twostage(), but we need to fix this before we can correct that problem. Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/ptw.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 06865227642..c1e124df495 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -249,7 +249,7 @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, /* Regime is physical. */ ptw->out_phys = addr; pte_attrs = 0; - pte_secure = is_secure; + pte_secure = s2_mmu_idx == ARMMMUIdx_Phys_S; } ptw->out_host = NULL; ptw->out_rw = false; @@ -291,13 +291,15 @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, fi->s1ns = !is_secure; return false; } + /* Check if page table walk is to secure or non-secure PA space. */ + ptw->out_secure = (is_secure + && !(pte_secure + ? env->cp15.vstcr_el2 & VSTCR_SW + : env->cp15.vtcr_el2 & VTCR_NSW)); + } else { + /* Regime is physical */ + ptw->out_secure = pte_secure; } - - /* Check if page table walk is to secure or non-secure PA space. */ - ptw->out_secure = (is_secure - && !(pte_secure - ? env->cp15.vstcr_el2 & VSTCR_SW - : env->cp15.vtcr_el2 & VTCR_NSW)); ptw->out_be = regime_translation_big_endian(env, mmu_idx); return true; From patchwork Fri Apr 14 16:04:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 673131 Delivered-To: patch@linaro.org Received: by 2002:adf:fcce:0:0:0:0:0 with SMTP id f14csp262084wrs; Fri, 14 Apr 2023 09:05:18 -0700 (PDT) X-Google-Smtp-Source: AKy350ac0s6HjHteT22zgOtPeEL1V3UKYz25JS4+UwoiVYWFj8i7TWu7hqsausXNCGn+Q9rp9U9r X-Received: by 2002:a05:622a:306:b0:3e9:353a:b674 with SMTP id q6-20020a05622a030600b003e9353ab674mr9763842qtw.8.1681488317920; Fri, 14 Apr 2023 09:05:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681488317; cv=none; d=google.com; s=arc-20160816; b=zvJz8XLCRmVmVinJsEDNjSuyhvqS6NvEt41pwb+YOkAYKXdh9wO1UBJw/6C8Jern9u 3PusddjLmAfWlrqkEzqOf9zaKqxABjfGa6lz3ueRH9GVLD2TXDkc1VyfFTG/Ij+wSYkk KywBTdun0tem1Y1QZkWcnn6cWa4p1p8u963MOuIaXyBaM+l6CVhhW2b4O3OtC2mTu/+S 2H0zhTsdlXKFpzpVRsfyG2iw5vSt/Kv5PJD7CTxV0LyiKYnOjvSEFuEL7AGU9wwho5vL 8qzdS6fvFpHP84y3YPqG9FO86Ds5BJ3GNBDiBy9Wtce08W1MOxRD6/vIyl4XjGA/3jBa xywA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=YMa/jjOI3MD8EqV7FtoT5tBQ7kPLlHERL0vXAgxCR5Y=; b=cXh3rJj2G5+ZebJKxVzVFKiScwTalNI/RcwIISa8TkC70ZUH0/8xl4yUmGmKhWtHP5 0ZixiQ4JLtGJAVGnjQMVs36FadCk/jH0onzig6feMAURs1QRtuwu72POHjsTObv9NAZ6 CSiX4SoB17w7qIVWV2hgTT6xr20mvPQD2s68X8/7gIznfxQgKf76j7VcQxHA4Fx6Ru7s PVBLsD9h1vPd6xiQTJNRg/RO/S7ei0on/8yoIMjrXJJOR+aZiBxc2HuZr8NtsN5K3Ab1 rxw4mIwES6cl/YZtCrmFiE480e1/ggaNZF4Ux4vWDtEscJvYSFyBp6eaIXTx/iYErEOZ CJlQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=RrqyY3tL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 8-20020a05600c22c800b003ef71d541cbsm4673752wmg.1.2023.04.14.09.04.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Apr 2023 09:04:16 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Richard Henderson Subject: [PATCH 3/3] target/arm: handle ipa_secure vs s2walk_secure correctly Date: Fri, 14 Apr 2023 17:04:13 +0100 Message-Id: <20230414160413.549801-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230414160413.549801-1-peter.maydell@linaro.org> References: <20230414160413.549801-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In get_phys_addr_twostage() when we set up the stage 2 translation, we currently incorrectly set all of in_mmu_idx, in_ptw_idx and in_secure based on s2walk_secure. Here s2walk_secure is true if we should be doing this stage 2 walk to physical memory. ipa_secure is true if the intermediate physical address we got from stage 1 is secure. The VSTCR_EL2.SW and VTCR_EL2.NSW bits allow the guest to configure secure EL2 so that these two things are different, eg: * a stage 2 walk for an NS IPA done to secure physical memory (where the translation table base address and other parameters for the walk come from the NS control registers VTTBR_EL2 and VTCR_EL2) * a stage 2 walk for an S IPA done to non-secure physical memory (where the parameters from the walk come from the S control registers VSTTBR_EL2 and VSTCR_EL2) To tell get_phys_addr_lpae() to do this, we need to pass in an in_mmu_idx based on ipa_secure, and an in_ptw_idx based on s2walk_secure. The in_secure parameter follows in_mmu_idx, as usual. Note that this change relies on fixes in the previous two commits ("Don't allow stage 2 page table walks to downgrade to NS" and "Set ptw->out_secure correctly for stage 2 translations"). Cc: qemu-stable@nongnu.org Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1600 Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- This change also means that v8M, which also uses get_phys_addr_twostage(), is no longer using a ptw->in_mmu_idx calculated based on s2walk_secure, which was always a little strange given that v8M doesn't do any kind of s2 walk, even though it didn't produce incorrect behaviour. --- target/arm/ptw.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index c1e124df495..2ee2b0b9241 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2741,9 +2741,9 @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw, } is_el0 = ptw->in_mmu_idx == ARMMMUIdx_Stage1_E0; - ptw->in_mmu_idx = s2walk_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2; + ptw->in_mmu_idx = ipa_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2; ptw->in_ptw_idx = s2walk_secure ? ARMMMUIdx_Phys_S : ARMMMUIdx_Phys_NS; - ptw->in_secure = s2walk_secure; + ptw->in_secure = ipa_secure; /* * S1 is done, now do S2 translation.