From patchwork Wed May 29 09:58:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 165366 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp9655692ili; Wed, 29 May 2019 03:00:32 -0700 (PDT) X-Google-Smtp-Source: APXvYqyewX2uxurP+STNS7tc95MTes6HaP4CwVASyH/Cjpux5AfChHnYbHbQv9H2I87kKxwgPY20 X-Received: by 2002:aa7:9115:: with SMTP id 21mr119563175pfh.14.1559124032750; Wed, 29 May 2019 03:00:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1559124032; cv=none; d=google.com; s=arc-20160816; b=KYBZt/hfRx7MgijAaDTopcepRfzE1D8ehnAE4eMQ4p7WmR4C86tnUFPAiaYzeugh3q XAI1qSPdZiAod+a/XabRCJ8LiBaXIUGcJoEQ7u7k0KotiEvnf283qklavzeKGAlr5vHU WI1+ePauFoliNkWEnrtr1vfDPOfi42k6xSB7BTsuiYlOg7If4Kic86CnklgDrXMk0qOZ Kw+jtBPeXjWIg8fAQ3pxpbVWQGRjXfHeAr29lUlmXCFYE10UeJ9L1N7jwwcMtfgxhYmr CeuQ2TYEFKI2o0U1Xu+LZiTLXQjsoDxw1tw30QMogpwYW3YKJEuxR/X7E6lbqjhQrqdP MaOQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from; bh=mlUeci07ifz48zPWr6VNKuIlm3xoReYWQS99J8NNBaY=; b=WlRY+xFL5xkeRY3TtNU+QjZ7MdkhJ7rRARGX9sBkaUbexcgBPh3YlOWvYSz5/JUc7Y 9kYSP+MYk2FJNYQYSNTJ1E3s6GZFdWakgEPdpoeop1lfU/sUVZrMovdqgc/qEFZRm3Bn Ejbrtxvkhup1relUWjMLun79ZGGmk+fo6orfHUO9bGl7tTOefT2gsXRFBtLw/0oWy3Lr 60RoGAb2+j3kxObp23itS6jI9EZxeiqYxUhP0YuolgdM49xC+axWSVSJUP6xkX54UTPp dLZm+ihdpxhizXdjU7H+OyzOeRdqiRsGBsRjLkJm9q+UqpN4QFQEL0/QfgjteoPMHEgO KZSg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id d23si24713060pgv.513.2019.05.29.03.00.32; Wed, 29 May 2019 03:00:32 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726326AbfE2KA1 (ORCPT + 30 others); Wed, 29 May 2019 06:00:27 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:57564 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726054AbfE2KAX (ORCPT ); Wed, 29 May 2019 06:00:23 -0400 Received: from DGGEMS402-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 9B490CFF3ED112421722; Wed, 29 May 2019 18:00:18 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS402-HUB.china.huawei.com (10.3.19.202) with Microsoft SMTP Server id 14.3.439.0; Wed, 29 May 2019 18:00:10 +0800 From: John Garry To: , CC: , , , Xiang Chen , "John Garry" Subject: [PATCH 1/6] scsi: hisi_sas: Delete PHYs' timer when rmmod or probe failed Date: Wed, 29 May 2019 17:58:42 +0800 Message-ID: <1559123927-160502-2-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1559123927-160502-1-git-send-email-john.garry@huawei.com> References: <1559123927-160502-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xiang Chen When removing the driver or for when probe fails, we need to delete PHY's timer. Signed-off-by: Xiang Chen Signed-off-by: John Garry --- drivers/scsi/hisi_sas/hisi_sas_main.c | 8 ++++++++ 1 file changed, 8 insertions(+) -- 2.17.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c b/drivers/scsi/hisi_sas/hisi_sas_main.c index 8a7feb8ed8d6..256f93e6f89f 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_main.c +++ b/drivers/scsi/hisi_sas/hisi_sas_main.c @@ -2480,6 +2480,14 @@ EXPORT_SYMBOL_GPL(hisi_sas_alloc); void hisi_sas_free(struct hisi_hba *hisi_hba) { + int i; + + for (i = 0; i < hisi_hba->n_phy; i++) { + struct hisi_sas_phy *phy = &hisi_hba->phy[i]; + + del_timer_sync(&phy->timer); + } + if (hisi_hba->wq) destroy_workqueue(hisi_hba->wq); } From patchwork Wed May 29 09:58:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 165367 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp9655759ili; Wed, 29 May 2019 03:00:36 -0700 (PDT) X-Google-Smtp-Source: APXvYqyDAicBWqXHBNG+GJKRWjIYUpOjACtaci3iqVGGSPd03dYYpxGpDgb9JtC5nxqIa8sVAhWF X-Received: by 2002:a17:902:2ae6:: with SMTP id j93mr118446324plb.130.1559124035990; Wed, 29 May 2019 03:00:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1559124035; cv=none; d=google.com; s=arc-20160816; b=atqgTO7xlEiZLTtJ/JKnFD8eizyC+lz1Xb+GVG6iUMsKkXRASc58th4jjgMwuXt8cd 6S0CiSsrE6Lx27qTWJ2lGwgcgPQ1nRdhe3dLcYrzOK8F5HTuDfDTgMXmTSSoreKmqdUg UsgQq2zY77ASqNjAfgNoxL1VnC3GVjfPfmOT9CgYzb2/S6F8eRQNcZ8QRrdwrHonLVGG oKYBPiWPefmoNHxwoA7G92pPIrglx+27Nz9cGtck+q78WNAnJiXfIaMlpDGhDKBElvuV JB4Pu/JFiK/fssrrOZT4aP/HXd8aP9CN8wi8KhK75BR5yykZPzkMgOGgFbaVS426afZ8 BSlg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from; bh=wso9aWmRBbtBuf+Ddz0xYYej6aHzB2Ey7WGy2F9zcLo=; b=Kl0eThdMjaoQDyuq/2hOFvZ2jr/RLM+ujJTT8S+1Xy+v6fMWsN0f18GPP3O/nYZ8aB 2iu6ixB/Zjk725XiAQkx/V9058w6EX8DYZyHkC50CRoEpgRn3hmmRKlnQTaC3tezpO6m uGPE8HgdB1Zexkx3ORRX9oR96xzUNM2B/pDQiiGPksNh+CssLATg5Xlmbtf80BUxmHwG 8Ij5y3vzeRbGMsjZHX2JJUmigNBYRATKaRse3LXI+UmAzIvw5FEt6N0kwpwE2ma8V/Ak 1at9BWmqbhSw0bwlVXvfqGO+uI2dMATWqtSV+04uE/3D/g9I36e5r35SS4HjToH6A5q2 0ghw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id d23si24713060pgv.513.2019.05.29.03.00.35; Wed, 29 May 2019 03:00:35 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726776AbfE2KA1 (ORCPT + 30 others); Wed, 29 May 2019 06:00:27 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:57544 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726038AbfE2KAW (ORCPT ); Wed, 29 May 2019 06:00:22 -0400 Received: from DGGEMS402-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 90C1534F7DF3A24A781C; Wed, 29 May 2019 18:00:18 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS402-HUB.china.huawei.com (10.3.19.202) with Microsoft SMTP Server id 14.3.439.0; Wed, 29 May 2019 18:00:11 +0800 From: John Garry To: , CC: , , , Xiaofei Tan , John Garry Subject: [PATCH 2/6] scsi: hisi_sas: Fix the issue of argument mismatch of printing ecc errors Date: Wed, 29 May 2019 17:58:43 +0800 Message-ID: <1559123927-160502-3-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1559123927-160502-1-git-send-email-john.garry@huawei.com> References: <1559123927-160502-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xiaofei Tan The argument of dev_err() called by multi_bit_ecc_error_process_v3_hw() is not right. We pass two arguments, but there is only one printk format specifier in the string. Besides, move the print format string to dev_err(). Then compiler can find such issue in earlier stage. Signed-off-by: Xiaofei Tan Signed-off-by: John Garry --- drivers/scsi/hisi_sas/hisi_sas_v2_hw.c | 46 ++++++++++++++------------ drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 25 +++++++------- 2 files changed, 37 insertions(+), 34 deletions(-) -- 2.17.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c index d4650bed8274..b8c0ba778293 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c @@ -427,70 +427,70 @@ static const struct hisi_sas_hw_error one_bit_ecc_errors[] = { .irq_msk = BIT(SAS_ECC_INTR_DQE_ECC_1B_OFF), .msk = HGC_DQE_ECC_1B_ADDR_MSK, .shift = HGC_DQE_ECC_1B_ADDR_OFF, - .msg = "hgc_dqe_acc1b_intr found: Ram address is 0x%08X\n", + .msg = "hgc_dqe_ecc1b_intr", .reg = HGC_DQE_ECC_ADDR, }, { .irq_msk = BIT(SAS_ECC_INTR_IOST_ECC_1B_OFF), .msk = HGC_IOST_ECC_1B_ADDR_MSK, .shift = HGC_IOST_ECC_1B_ADDR_OFF, - .msg = "hgc_iost_acc1b_intr found: Ram address is 0x%08X\n", + .msg = "hgc_iost_ecc1b_intr", .reg = HGC_IOST_ECC_ADDR, }, { .irq_msk = BIT(SAS_ECC_INTR_ITCT_ECC_1B_OFF), .msk = HGC_ITCT_ECC_1B_ADDR_MSK, .shift = HGC_ITCT_ECC_1B_ADDR_OFF, - .msg = "hgc_itct_acc1b_intr found: am address is 0x%08X\n", + .msg = "hgc_itct_ecc1b_intr", .reg = HGC_ITCT_ECC_ADDR, }, { .irq_msk = BIT(SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF), .msk = HGC_LM_DFX_STATUS2_IOSTLIST_MSK, .shift = HGC_LM_DFX_STATUS2_IOSTLIST_OFF, - .msg = "hgc_iostl_acc1b_intr found: memory address is 0x%08X\n", + .msg = "hgc_iostl_ecc1b_intr", .reg = HGC_LM_DFX_STATUS2, }, { .irq_msk = BIT(SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF), .msk = HGC_LM_DFX_STATUS2_ITCTLIST_MSK, .shift = HGC_LM_DFX_STATUS2_ITCTLIST_OFF, - .msg = "hgc_itctl_acc1b_intr found: memory address is 0x%08X\n", + .msg = "hgc_itctl_ecc1b_intr", .reg = HGC_LM_DFX_STATUS2, }, { .irq_msk = BIT(SAS_ECC_INTR_CQE_ECC_1B_OFF), .msk = HGC_CQE_ECC_1B_ADDR_MSK, .shift = HGC_CQE_ECC_1B_ADDR_OFF, - .msg = "hgc_cqe_acc1b_intr found: Ram address is 0x%08X\n", + .msg = "hgc_cqe_ecc1b_intr", .reg = HGC_CQE_ECC_ADDR, }, { .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF), .msk = HGC_RXM_DFX_STATUS14_MEM0_MSK, .shift = HGC_RXM_DFX_STATUS14_MEM0_OFF, - .msg = "rxm_mem0_acc1b_intr found: memory address is 0x%08X\n", + .msg = "rxm_mem0_ecc1b_intr", .reg = HGC_RXM_DFX_STATUS14, }, { .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF), .msk = HGC_RXM_DFX_STATUS14_MEM1_MSK, .shift = HGC_RXM_DFX_STATUS14_MEM1_OFF, - .msg = "rxm_mem1_acc1b_intr found: memory address is 0x%08X\n", + .msg = "rxm_mem1_ecc1b_intr", .reg = HGC_RXM_DFX_STATUS14, }, { .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF), .msk = HGC_RXM_DFX_STATUS14_MEM2_MSK, .shift = HGC_RXM_DFX_STATUS14_MEM2_OFF, - .msg = "rxm_mem2_acc1b_intr found: memory address is 0x%08X\n", + .msg = "rxm_mem2_ecc1b_intr", .reg = HGC_RXM_DFX_STATUS14, }, { .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF), .msk = HGC_RXM_DFX_STATUS15_MEM3_MSK, .shift = HGC_RXM_DFX_STATUS15_MEM3_OFF, - .msg = "rxm_mem3_acc1b_intr found: memory address is 0x%08X\n", + .msg = "rxm_mem3_ecc1b_intr", .reg = HGC_RXM_DFX_STATUS15, }, }; @@ -500,70 +500,70 @@ static const struct hisi_sas_hw_error multi_bit_ecc_errors[] = { .irq_msk = BIT(SAS_ECC_INTR_DQE_ECC_MB_OFF), .msk = HGC_DQE_ECC_MB_ADDR_MSK, .shift = HGC_DQE_ECC_MB_ADDR_OFF, - .msg = "hgc_dqe_accbad_intr (0x%x) found: Ram address is 0x%08X\n", + .msg = "hgc_dqe_eccbad_intr", .reg = HGC_DQE_ECC_ADDR, }, { .irq_msk = BIT(SAS_ECC_INTR_IOST_ECC_MB_OFF), .msk = HGC_IOST_ECC_MB_ADDR_MSK, .shift = HGC_IOST_ECC_MB_ADDR_OFF, - .msg = "hgc_iost_accbad_intr (0x%x) found: Ram address is 0x%08X\n", + .msg = "hgc_iost_eccbad_intr", .reg = HGC_IOST_ECC_ADDR, }, { .irq_msk = BIT(SAS_ECC_INTR_ITCT_ECC_MB_OFF), .msk = HGC_ITCT_ECC_MB_ADDR_MSK, .shift = HGC_ITCT_ECC_MB_ADDR_OFF, - .msg = "hgc_itct_accbad_intr (0x%x) found: Ram address is 0x%08X\n", + .msg = "hgc_itct_eccbad_intr", .reg = HGC_ITCT_ECC_ADDR, }, { .irq_msk = BIT(SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF), .msk = HGC_LM_DFX_STATUS2_IOSTLIST_MSK, .shift = HGC_LM_DFX_STATUS2_IOSTLIST_OFF, - .msg = "hgc_iostl_accbad_intr (0x%x) found: memory address is 0x%08X\n", + .msg = "hgc_iostl_eccbad_intr", .reg = HGC_LM_DFX_STATUS2, }, { .irq_msk = BIT(SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF), .msk = HGC_LM_DFX_STATUS2_ITCTLIST_MSK, .shift = HGC_LM_DFX_STATUS2_ITCTLIST_OFF, - .msg = "hgc_itctl_accbad_intr (0x%x) found: memory address is 0x%08X\n", + .msg = "hgc_itctl_eccbad_intr", .reg = HGC_LM_DFX_STATUS2, }, { .irq_msk = BIT(SAS_ECC_INTR_CQE_ECC_MB_OFF), .msk = HGC_CQE_ECC_MB_ADDR_MSK, .shift = HGC_CQE_ECC_MB_ADDR_OFF, - .msg = "hgc_cqe_accbad_intr (0x%x) found: Ram address is 0x%08X\n", + .msg = "hgc_cqe_eccbad_intr", .reg = HGC_CQE_ECC_ADDR, }, { .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF), .msk = HGC_RXM_DFX_STATUS14_MEM0_MSK, .shift = HGC_RXM_DFX_STATUS14_MEM0_OFF, - .msg = "rxm_mem0_accbad_intr (0x%x) found: memory address is 0x%08X\n", + .msg = "rxm_mem0_eccbad_intr", .reg = HGC_RXM_DFX_STATUS14, }, { .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF), .msk = HGC_RXM_DFX_STATUS14_MEM1_MSK, .shift = HGC_RXM_DFX_STATUS14_MEM1_OFF, - .msg = "rxm_mem1_accbad_intr (0x%x) found: memory address is 0x%08X\n", + .msg = "rxm_mem1_eccbad_intr", .reg = HGC_RXM_DFX_STATUS14, }, { .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF), .msk = HGC_RXM_DFX_STATUS14_MEM2_MSK, .shift = HGC_RXM_DFX_STATUS14_MEM2_OFF, - .msg = "rxm_mem2_accbad_intr (0x%x) found: memory address is 0x%08X\n", + .msg = "rxm_mem2_eccbad_intr", .reg = HGC_RXM_DFX_STATUS14, }, { .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF), .msk = HGC_RXM_DFX_STATUS15_MEM3_MSK, .shift = HGC_RXM_DFX_STATUS15_MEM3_OFF, - .msg = "rxm_mem3_accbad_intr (0x%x) found: memory address is 0x%08X\n", + .msg = "rxm_mem3_eccbad_intr", .reg = HGC_RXM_DFX_STATUS15, }, }; @@ -2978,7 +2978,8 @@ one_bit_ecc_error_process_v2_hw(struct hisi_hba *hisi_hba, u32 irq_value) val = hisi_sas_read32(hisi_hba, ecc_error->reg); val &= ecc_error->msk; val >>= ecc_error->shift; - dev_warn(dev, ecc_error->msg, val); + dev_warn(dev, "%s found: mem addr is 0x%08X\n", + ecc_error->msg, val); } } } @@ -2997,7 +2998,8 @@ static void multi_bit_ecc_error_process_v2_hw(struct hisi_hba *hisi_hba, val = hisi_sas_read32(hisi_hba, ecc_error->reg); val &= ecc_error->msk; val >>= ecc_error->shift; - dev_err(dev, ecc_error->msg, irq_value, val); + dev_err(dev, "%s (0x%x) found: mem addr is 0x%08X\n", + ecc_error->msg, irq_value, val); queue_work(hisi_hba->wq, &hisi_hba->rst_work); } } diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c index 49620c2411df..3efb1e72bdab 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c @@ -1831,77 +1831,77 @@ static const struct hisi_sas_hw_error multi_bit_ecc_errors[] = { .irq_msk = BIT(SAS_ECC_INTR_DQE_ECC_MB_OFF), .msk = HGC_DQE_ECC_MB_ADDR_MSK, .shift = HGC_DQE_ECC_MB_ADDR_OFF, - .msg = "hgc_dqe_eccbad_intr found: ram addr is 0x%08X\n", + .msg = "hgc_dqe_eccbad_intr", .reg = HGC_DQE_ECC_ADDR, }, { .irq_msk = BIT(SAS_ECC_INTR_IOST_ECC_MB_OFF), .msk = HGC_IOST_ECC_MB_ADDR_MSK, .shift = HGC_IOST_ECC_MB_ADDR_OFF, - .msg = "hgc_iost_eccbad_intr found: ram addr is 0x%08X\n", + .msg = "hgc_iost_eccbad_intr", .reg = HGC_IOST_ECC_ADDR, }, { .irq_msk = BIT(SAS_ECC_INTR_ITCT_ECC_MB_OFF), .msk = HGC_ITCT_ECC_MB_ADDR_MSK, .shift = HGC_ITCT_ECC_MB_ADDR_OFF, - .msg = "hgc_itct_eccbad_intr found: ram addr is 0x%08X\n", + .msg = "hgc_itct_eccbad_intr", .reg = HGC_ITCT_ECC_ADDR, }, { .irq_msk = BIT(SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF), .msk = HGC_LM_DFX_STATUS2_IOSTLIST_MSK, .shift = HGC_LM_DFX_STATUS2_IOSTLIST_OFF, - .msg = "hgc_iostl_eccbad_intr found: mem addr is 0x%08X\n", + .msg = "hgc_iostl_eccbad_intr", .reg = HGC_LM_DFX_STATUS2, }, { .irq_msk = BIT(SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF), .msk = HGC_LM_DFX_STATUS2_ITCTLIST_MSK, .shift = HGC_LM_DFX_STATUS2_ITCTLIST_OFF, - .msg = "hgc_itctl_eccbad_intr found: mem addr is 0x%08X\n", + .msg = "hgc_itctl_eccbad_intr", .reg = HGC_LM_DFX_STATUS2, }, { .irq_msk = BIT(SAS_ECC_INTR_CQE_ECC_MB_OFF), .msk = HGC_CQE_ECC_MB_ADDR_MSK, .shift = HGC_CQE_ECC_MB_ADDR_OFF, - .msg = "hgc_cqe_eccbad_intr found: ram address is 0x%08X\n", + .msg = "hgc_cqe_eccbad_intr", .reg = HGC_CQE_ECC_ADDR, }, { .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF), .msk = HGC_RXM_DFX_STATUS14_MEM0_MSK, .shift = HGC_RXM_DFX_STATUS14_MEM0_OFF, - .msg = "rxm_mem0_eccbad_intr found: mem addr is 0x%08X\n", + .msg = "rxm_mem0_eccbad_intr", .reg = HGC_RXM_DFX_STATUS14, }, { .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF), .msk = HGC_RXM_DFX_STATUS14_MEM1_MSK, .shift = HGC_RXM_DFX_STATUS14_MEM1_OFF, - .msg = "rxm_mem1_eccbad_intr found: mem addr is 0x%08X\n", + .msg = "rxm_mem1_eccbad_intr", .reg = HGC_RXM_DFX_STATUS14, }, { .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF), .msk = HGC_RXM_DFX_STATUS14_MEM2_MSK, .shift = HGC_RXM_DFX_STATUS14_MEM2_OFF, - .msg = "rxm_mem2_eccbad_intr found: mem addr is 0x%08X\n", + .msg = "rxm_mem2_eccbad_intr", .reg = HGC_RXM_DFX_STATUS14, }, { .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF), .msk = HGC_RXM_DFX_STATUS15_MEM3_MSK, .shift = HGC_RXM_DFX_STATUS15_MEM3_OFF, - .msg = "rxm_mem3_eccbad_intr found: mem addr is 0x%08X\n", + .msg = "rxm_mem3_eccbad_intr", .reg = HGC_RXM_DFX_STATUS15, }, { .irq_msk = BIT(SAS_ECC_INTR_OOO_RAM_ECC_MB_OFF), .msk = AM_ROB_ECC_ERR_ADDR_MSK, .shift = AM_ROB_ECC_ERR_ADDR_OFF, - .msg = "ooo_ram_eccbad_intr found: ROB_ECC_ERR_ADDR=0x%08X\n", + .msg = "ooo_ram_eccbad_intr", .reg = AM_ROB_ECC_ERR_ADDR, }, }; @@ -1920,7 +1920,8 @@ static void multi_bit_ecc_error_process_v3_hw(struct hisi_hba *hisi_hba, val = hisi_sas_read32(hisi_hba, ecc_error->reg); val &= ecc_error->msk; val >>= ecc_error->shift; - dev_err(dev, ecc_error->msg, irq_value, val); + dev_err(dev, "%s (0x%x) found: mem addr is 0x%08X\n", + ecc_error->msg, irq_value, val); queue_work(hisi_hba->wq, &hisi_hba->rst_work); } } From patchwork Wed May 29 09:58:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 165364 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp9655528ili; Wed, 29 May 2019 03:00:25 -0700 (PDT) X-Google-Smtp-Source: APXvYqzJn+97rEzRjkbBSZGgOnRD0UciND3utLueuYWDIPIPBil1iPBBqRRXpgAWfGeosJrSXuLA X-Received: by 2002:a63:2844:: with SMTP id o65mr51045645pgo.297.1559124025585; Wed, 29 May 2019 03:00:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1559124025; cv=none; d=google.com; s=arc-20160816; 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[209.132.180.67]) by mx.google.com with ESMTP id d23si24713060pgv.513.2019.05.29.03.00.25; Wed, 29 May 2019 03:00:25 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726701AbfE2KAY (ORCPT + 30 others); Wed, 29 May 2019 06:00:24 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:57488 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1725894AbfE2KAV (ORCPT ); Wed, 29 May 2019 06:00:21 -0400 Received: from DGGEMS402-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 873DAA6CDEC2254E07E; Wed, 29 May 2019 18:00:18 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS402-HUB.china.huawei.com (10.3.19.202) with Microsoft SMTP Server id 14.3.439.0; Wed, 29 May 2019 18:00:11 +0800 From: John Garry To: , CC: , , , John Garry , "dann frazier" Subject: [PATCH 3/6] scsi: hisi_sas: Reduce HISI_SAS_SGE_PAGE_CNT in size Date: Wed, 29 May 2019 17:58:44 +0800 Message-ID: <1559123927-160502-4-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1559123927-160502-1-git-send-email-john.garry@huawei.com> References: <1559123927-160502-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Macro HISI_SAS_SGE_PAGE_CNT is defined to SG_CHUNK_SIZE, which is 128. This means that sizeof(struct hisi_sas_slot_buf_table) is 4192. This is just over a 4K, which can mean inefficient DMA memory usage (for no PI). Reduce the size of HISI_SAS_SGE_PAGE_CNT to 124 to fit in a 4K page. With this change, we experience no performance hit. Cc: dann frazier Signed-off-by: John Garry --- drivers/scsi/hisi_sas/hisi_sas.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h index fc87994b5d73..06f22fb372b1 100644 --- a/drivers/scsi/hisi_sas/hisi_sas.h +++ b/drivers/scsi/hisi_sas/hisi_sas.h @@ -484,12 +484,12 @@ struct hisi_sas_command_table_stp { u8 atapi_cdb[ATAPI_CDB_LEN]; }; -#define HISI_SAS_SGE_PAGE_CNT SG_CHUNK_SIZE +#define HISI_SAS_SGE_PAGE_CNT (124) struct hisi_sas_sge_page { struct hisi_sas_sge sge[HISI_SAS_SGE_PAGE_CNT]; } __aligned(16); -#define HISI_SAS_SGE_DIF_PAGE_CNT SG_CHUNK_SIZE +#define HISI_SAS_SGE_DIF_PAGE_CNT HISI_SAS_SGE_PAGE_CNT struct hisi_sas_sge_dif_page { struct hisi_sas_sge sge[HISI_SAS_SGE_DIF_PAGE_CNT]; } __aligned(16); From patchwork Wed May 29 09:58:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 165369 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp9656061ili; Wed, 29 May 2019 03:00:47 -0700 (PDT) X-Google-Smtp-Source: APXvYqzca+dDqGVA3GU0qWE6f4tYR4TdRsoqhi0ILnx+aUOn+7UkWCH2Anr0iTf6v3r5SaAMlVeI X-Received: by 2002:a17:90a:8586:: with SMTP id m6mr11046130pjn.129.1559124047518; Wed, 29 May 2019 03:00:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1559124047; cv=none; d=google.com; s=arc-20160816; b=WVm3O4OMicE/lM47cnsrGF5Sj7fAjEv77DUWX3MdNPFZVChivrH3JSU9XcFVAZLdKH KZLHH1dgqvmITLIbih53SBkkkZhYHtLZetbG/0Bl7shuxNQlPXZsd1MUPiorNyVqcCEg Xo+ydrETgP3SM0haq3kmnMS3ufSY0FQba4AFv3xcOBthv16KmLLO4MItaNyMdCo1KkYi JKCJFxwOQzMveYfIq+OzcwRWYSOsCj4oobx04UJf7351tyE0NRs0FEtfv0+jJ2xSTg5p JNng9tRI5NKgJYDOpLkL2cugtr0oHfHrsJ6PdmKc0K7fp4tnHXmruF0B7NuhZo/aWrp+ qxjw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from; bh=6qg4868omeIs7G91CJX6vTiVd4comMhEAedpiJhJckQ=; b=Rpg6JXSFj+rugdIkT3ojzFoZq8F7TUgFGka8rx840SAUsl7fGXCfS/5YQIZSN7IAiY SZKtdMcPjG7mN8JvkCBgsF83dVK9bhO0L+tIT9UZkOXntjKyqrtL78ZMymFbRye/35Cp MVDGFy2uxsRmTnlTBq0P+UsK1yCCTYuaQNC6DrqxCI7Um9gOXIn9uN5FgcHi6+4gD3cu zQumBfJcv9TioFDMB512jOt/+LkTFFzUHYih/WhWH5wCNzpCf0/2kJLvjzSzzvU9bVml 20g/ogpJuDWmiO95SmxlRtUQdGemyB6DDW2f2SaDtmBlNOYU1LP0GK5Pv1+ca02iQtQU VThw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id h5si20137324pgc.8.2019.05.29.03.00.47; Wed, 29 May 2019 03:00:47 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726842AbfE2KAq (ORCPT + 30 others); Wed, 29 May 2019 06:00:46 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:57558 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726043AbfE2KAW (ORCPT ); Wed, 29 May 2019 06:00:22 -0400 Received: from DGGEMS402-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 96C3825A9C013174C762; Wed, 29 May 2019 18:00:18 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS402-HUB.china.huawei.com (10.3.19.202) with Microsoft SMTP Server id 14.3.439.0; Wed, 29 May 2019 18:00:11 +0800 From: John Garry To: , CC: , , , Xiang Chen , "John Garry" Subject: [PATCH 4/6] scsi: hisi_sas: Change the type of some numbers to unsigned Date: Wed, 29 May 2019 17:58:45 +0800 Message-ID: <1559123927-160502-5-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1559123927-160502-1-git-send-email-john.garry@huawei.com> References: <1559123927-160502-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xiang Chen It reports a error as follows from some tools at two places in our code: runtime error: left shift of 4 by 29 places cannot be represented in type 'int' So change the type of the two number to unsigned to avoid the error. Signed-off-by: Xiang Chen Signed-off-by: John Garry --- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c index 3efb1e72bdab..492ada65d41a 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c @@ -1344,7 +1344,7 @@ static void prep_ata_v3_hw(struct hisi_hba *hisi_hba, if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type)) hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF); else - hdr->dw0 |= cpu_to_le32(4 << CMD_HDR_CMD_OFF); + hdr->dw0 |= cpu_to_le32(4U << CMD_HDR_CMD_OFF); switch (task->data_dir) { case DMA_TO_DEVICE: @@ -1412,7 +1412,7 @@ static void prep_abort_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_port *port = slot->port; /* dw0 */ - hdr->dw0 = cpu_to_le32((5 << CMD_HDR_CMD_OFF) | /*abort*/ + hdr->dw0 = cpu_to_le32((5U << CMD_HDR_CMD_OFF) | /*abort*/ (port->id << CMD_HDR_PORT_OFF) | (dev_is_sata(dev) << CMD_HDR_ABORT_DEVICE_TYPE_OFF) | From patchwork Wed May 29 09:58:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 165365 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp9655628ili; Wed, 29 May 2019 03:00:29 -0700 (PDT) X-Google-Smtp-Source: APXvYqwKtwxqw1KPI8JMPUX2lRpqH/cJZ0I11HOCAfBvG7JXAgVQo7cChg6Lk6+UtIatk9ObiQno X-Received: by 2002:a17:902:b195:: with SMTP id s21mr38639258plr.16.1559124029848; Wed, 29 May 2019 03:00:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1559124029; cv=none; d=google.com; s=arc-20160816; b=RScJqSKiH1h6Ix3yFdrvXVy/tUu8e0sFvGLh+Br/hUvl2XwcYh1dnYdr+GkMsw8UPE jo0ksq07pQYsC2Birm0ZAApXc0C1zBB7DEvRmLQGO+KfL49Ikry9SoVqbmhpVwm1u4eE IQVmP06DB1ymlmaisKQHz3YNmBFduUUt9+6FFQUxdTvmWrHQ3ohUWKoKz6tV4M4xr0h0 imnciGBE9oao29PDUaUYytZMHfuEdhTbjh1vWyIwAY1bSy5BTj+ruVrjuEvmvdRiN9J/ D7Y2GwfXjlOZiJLXwk1T6bs0WTfdH71ikSTVk1p6uNNGo+/RCgwGWXIl3+NELNhCX2uj azBg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from; bh=NB6XmEn6QSnY61VDD0E3BWi7e1Femfj1E0/RYFH2vP0=; b=yfBGNlYGJHI3koiXz+wkVGGMfM379wZ8IuoeXeNcyDMMrAeNfDGsRkua6SqjUjytN3 UzgyO9eUHBib8MkHiCgSXMHZvu27nAt5DUoVhizJwZrNyLqTzSfL0isFu/IgfDJDsury /uwT5JE0EVVDrLkQ9l8/1FMOHlaihNG34HNa4XkU8BIMRD5D1xf1+YG/xs53NXwo5eOU YwfdRYOi6oLeB/WDFCbl63lfif1B0dbvzFBNMvwNAYCMy8KjiINKbw8InovWPQA8HRoC BYA4Z5X5mZsVqFEE6eZQHB+YEPeQ8mDrDEnZoGhdO86uzzHRKycGoWI8VFkeZnEO6rxj 1IOQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id d23si24713060pgv.513.2019.05.29.03.00.29; Wed, 29 May 2019 03:00:29 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726816AbfE2KA2 (ORCPT + 30 others); Wed, 29 May 2019 06:00:28 -0400 Received: from szxga07-in.huawei.com ([45.249.212.35]:35664 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726658AbfE2KAZ (ORCPT ); Wed, 29 May 2019 06:00:25 -0400 Received: from DGGEMS402-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 9D5EF2381E56D4F64836; Wed, 29 May 2019 18:00:22 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS402-HUB.china.huawei.com (10.3.19.202) with Microsoft SMTP Server id 14.3.439.0; Wed, 29 May 2019 18:00:12 +0800 From: John Garry To: , CC: , , , Luo Jiaxing , John Garry Subject: [PATCH 5/6] scsi: hisi_sas: Ignore the error code between phy down to phy up Date: Wed, 29 May 2019 17:58:46 +0800 Message-ID: <1559123927-160502-6-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1559123927-160502-1-git-send-email-john.garry@huawei.com> References: <1559123927-160502-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Luo Jiaxing Several error code will be generated between PHY down to up. This issue was introduced by HW design, so the designers come to a conclusion that we should ignore these several error code. Signed-off-by: Jiaxing Luo Signed-off-by: John Garry --- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) -- 2.17.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c index 492ada65d41a..fbf0a1e9c8c2 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c @@ -911,8 +911,14 @@ static void enable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) static void disable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) { u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); + u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2_MSK); + static const u32 msk = BIT(CHL_INT2_RX_DISP_ERR_OFF) | + BIT(CHL_INT2_RX_CODE_ERR_OFF) | + BIT(CHL_INT2_RX_INVLD_DW_OFF); u32 state; + hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2_MSK, msk | irq_msk); + cfg &= ~PHY_CFG_ENA_MSK; hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); @@ -923,6 +929,15 @@ static void disable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) cfg |= PHY_CFG_PHY_RST_MSK; hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); } + + udelay(1); + + hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_INVLD_DW); + hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DISP_ERR); + hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_CODE_ERR); + + hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, msk); + hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2_MSK, irq_msk); } static void start_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) From patchwork Wed May 29 09:58:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 165368 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp9655859ili; Wed, 29 May 2019 03:00:40 -0700 (PDT) X-Google-Smtp-Source: APXvYqzeGwiMQGZG9ox5yxmiy0ZsY3ZqcC3Zt9GCphWpBoIsrXmzi6SHscQFBhxvD4ZSwOy/rQgQ X-Received: by 2002:a17:902:8214:: with SMTP id x20mr117042174pln.308.1559124040352; Wed, 29 May 2019 03:00:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1559124040; cv=none; d=google.com; s=arc-20160816; b=GnFxXEkzLe8GyVv7stO5EeQOlUjYc2G0REn5EZ+Q1WiBOGbe5UjfBWvzZvNpaxbo4q /FzuP/3klDRZ5usdtIiWEAGNIvPMpgS5I6eQJB3XE7dwP/bJ0koihFwZly4uyQxpJ7rk bR82P8pQsO4awy9WdXT8dwnQnUxOvE41yQdXvx7V+urJreeMME+OIZVL3hE9GV/mmd8q PFwKTvGqmBY1OWKsOqn2HY4s6B78S1LTqY4JVJLBdG/SfWfcmKrjtsR3oYJ5d34Dwh7c IS12pGHc+pEhGVOOTtLldd/avUpPuNcN7nyrUaNKKoZmKDdgl7JutKO9+bIl2Z1c6ngb XJSQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from; bh=Rxv397qlEiS2ToB7sxNyNC43iMkEDkKRa+Awvu8ylNI=; b=AElpKR1RgkBbe0IOqgZpgqEd5xGVRN5HWknfvVBLltFWTP6RQ0nNbdFEdpWVNefP5Q GXE6ux8J7G1g6IvxgjxptxFvAIC5faMqLo8XQqtT+cfQ9aSofqld8Uq8W9KsQP06LPzx PErGRsCoKQ704SPCDFrsVEItZxTmrpjuHAvNeiQ4nNxWjdoLmQ20CI0HnYKbwbaEKDeL tkHmOSCvYQOT+Ny9Tj3BENE+d4pOwe7A1OwWRSFEEsFEH2KbdNtHVD6AyXttEZWIDeZz cEn+/vzFRoETml4yOjxfLL3aiQHrKx+Fl2iMnYzy+SJdfa1x2JfBIjUIUySRaOr753wO QGkA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id j17si1264509pfn.226.2019.05.29.03.00.40; Wed, 29 May 2019 03:00:40 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726828AbfE2KAj (ORCPT + 30 others); Wed, 29 May 2019 06:00:39 -0400 Received: from szxga07-in.huawei.com ([45.249.212.35]:35662 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726670AbfE2KAY (ORCPT ); Wed, 29 May 2019 06:00:24 -0400 Received: from DGGEMS402-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 98DF4438F3D9E84A517B; Wed, 29 May 2019 18:00:22 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS402-HUB.china.huawei.com (10.3.19.202) with Microsoft SMTP Server id 14.3.439.0; Wed, 29 May 2019 18:00:12 +0800 From: John Garry To: , CC: , , , Xiang Chen , "John Garry" Subject: [PATCH 6/6] scsi: hisi_sas: Disable stash for v3 hw Date: Wed, 29 May 2019 17:58:47 +0800 Message-ID: <1559123927-160502-7-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1559123927-160502-1-git-send-email-john.garry@huawei.com> References: <1559123927-160502-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xiang Chen For v3 hw, stash is enabled to promote performance, but it does little help for promoting performance according to current test. What's more, it causes exception for some situations, so disable it. Signed-off-by: Xiang Chen Signed-off-by: John Garry --- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 2 ++ 1 file changed, 2 insertions(+) -- 2.17.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c index fbf0a1e9c8c2..b92aa6b37e1d 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c @@ -28,6 +28,7 @@ #define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF) #define ITCT_DEV_OFF 0 #define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF) +#define SAS_AXI_USER3 0x50 #define IO_SATA_BROKEN_MSG_ADDR_LO 0x58 #define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c #define SATA_INITI_D2H_STORE_ADDR_LO 0x60 @@ -554,6 +555,7 @@ static void init_reg_v3_hw(struct hisi_hba *hisi_hba) /* Global registers init */ hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, (u32)((1ULL << hisi_hba->queue_count) - 1)); + hisi_sas_write32(hisi_hba, SAS_AXI_USER3, 0); hisi_sas_write32(hisi_hba, CFG_MAX_TAG, 0xfff0400); hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x108); hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x1);