From patchwork Thu Apr 13 22:30:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Judith Mendez X-Patchwork-Id: 674200 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B7D19C77B79 for ; Thu, 13 Apr 2023 22:31:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229997AbjDMWbP (ORCPT ); Thu, 13 Apr 2023 18:31:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47034 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229577AbjDMWbN (ORCPT ); Thu, 13 Apr 2023 18:31:13 -0400 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 59CB3868D; Thu, 13 Apr 2023 15:31:12 -0700 (PDT) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 33DMUqhN071324; Thu, 13 Apr 2023 17:30:52 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1681425052; bh=5oQBE1OTbrIAIvuRzCjIYi4IgsqkNGNtrVbvqNRvhWM=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=MpBVIWzmC1gsGQHm6fwygE+sXuwZsrmCgxIOw7M5fOq26pgoQBUTEJrrIR7mms2vR qR1dUHaLdVsudfZQPwWxTIbT8m613zz7U93fE+LxhoTwHigQSS/6QG3Q5qRxL1jlpE G8cMLV1QB/25gBPp1Zcr8zx8QSMWE3lLvVOWqd5Y= Received: from DLEE104.ent.ti.com (dlee104.ent.ti.com [157.170.170.34]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 33DMUqHq074962 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 13 Apr 2023 17:30:52 -0500 Received: from DLEE106.ent.ti.com (157.170.170.36) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Thu, 13 Apr 2023 17:30:52 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Thu, 13 Apr 2023 17:30:51 -0500 Received: from a0498204.dal.design.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 33DMUpa4063427; Thu, 13 Apr 2023 17:30:51 -0500 From: Judith Mendez To: Chandrasekar Ramakrishnan CC: Nishanth Menon , Vignesh Raghavendra , Andrew Davis , Wolfgang Grandegger , Marc Kleine-Budde , Rob Herring , Krzysztof Kozlowski , , , , , Schuyler Patton Subject: [RFC PATCH 1/5] arm64: dts: ti: Add AM62x MCAN MAIN domain transceiver overlay Date: Thu, 13 Apr 2023 17:30:47 -0500 Message-ID: <20230413223051.24455-2-jm@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230413223051.24455-1-jm@ti.com> References: <20230413223051.24455-1-jm@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add an overlay for main domain MCAN on AM62x SK. The AM62x SK board does not have on-board CAN transceiver so instead of changing the dtb permanently, add an overlay to enable MAIN domain MCAN and support for 1 CAN transceiver. Signed-off-by: Judith Mendez --- arch/arm64/boot/dts/ti/Makefile | 2 ++ .../boot/dts/ti/k3-am625-sk-mcan-main.dtso | 35 +++++++++++++++++++ 2 files changed, 37 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am625-sk-mcan-main.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index c83c9d772b81..abe15e76b614 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -9,8 +9,10 @@ # alphabetically. # Boards with AM62x SoC +k3-am625-sk-mcan-dtbs := k3-am625-sk.dtb k3-am625-sk-mcan-main.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am625-beagleplay.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-sk.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am625-sk-mcan.dtb dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk.dtb # Boards with AM62Ax SoC diff --git a/arch/arm64/boot/dts/ti/k3-am625-sk-mcan-main.dtso b/arch/arm64/boot/dts/ti/k3-am625-sk-mcan-main.dtso new file mode 100644 index 000000000000..72b68fd51121 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am625-sk-mcan-main.dtso @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT overlay for MCAN transceiver in main domain on AM625 SK + * + * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + transceiver1: can-phy0 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + }; +}; + +&main_pmx0 { + main_mcan0_pins_default: main-mcan0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x1dc, PIN_INPUT, 0) /* (E15) MCAN0_RX */ + AM62X_IOPAD(0x1d8, PIN_OUTPUT, 0) /* (C15) MCAN0_TX */ + >; + }; +}; + +&main_mcan0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan0_pins_default>; + phys = <&transceiver1>; +}; From patchwork Thu Apr 13 22:30:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Judith Mendez X-Patchwork-Id: 672896 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1DEE1C77B61 for ; Thu, 13 Apr 2023 22:36:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229735AbjDMWg2 (ORCPT ); Thu, 13 Apr 2023 18:36:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53230 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229720AbjDMWg0 (ORCPT ); Thu, 13 Apr 2023 18:36:26 -0400 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 36542110; Thu, 13 Apr 2023 15:36:24 -0700 (PDT) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 33DMUq1T071320; Thu, 13 Apr 2023 17:30:52 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1681425052; bh=kCdEb/NvZkw25bQuwMNRo9ZrE7qZwdwyaq0NV1d1GTQ=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Y5pYGYIbbQOiUHjlM802gY36neCbyKeHZFBTClAdjN3XeaEP8NM7tp3Z5Qk2IazM2 p052IWDJEbc36ByZ7VnaosCn1zLGLjanCUf1pq1WUPEW5RTCWO5ZCeLFVJzNEHB1Co wFU2/MJ8BFsR8SeAD7+5vpvT+TDKXOsehOkFpi8E= Received: from DLEE115.ent.ti.com (dlee115.ent.ti.com [157.170.170.26]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 33DMUqUv019444 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 13 Apr 2023 17:30:52 -0500 Received: from DLEE112.ent.ti.com (157.170.170.23) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Thu, 13 Apr 2023 17:30:52 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Thu, 13 Apr 2023 17:30:51 -0500 Received: from a0498204.dal.design.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 33DMUpa5063427; Thu, 13 Apr 2023 17:30:51 -0500 From: Judith Mendez To: Chandrasekar Ramakrishnan CC: Nishanth Menon , Vignesh Raghavendra , Andrew Davis , Wolfgang Grandegger , Marc Kleine-Budde , Rob Herring , Krzysztof Kozlowski , , , , , Schuyler Patton Subject: [RFC PATCH 2/5] arm64: defconfig: Enable MCAN driver Date: Thu, 13 Apr 2023 17:30:48 -0500 Message-ID: <20230413223051.24455-3-jm@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230413223051.24455-1-jm@ti.com> References: <20230413223051.24455-1-jm@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Enable CAN_M_CAN and CAN_M_CAN_PLATFORM to be built as modules by default for TI boards. Signed-off-by: Judith Mendez --- arch/arm64/configs/defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 7790ee42c68a..172a2523051f 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -176,6 +176,8 @@ CONFIG_NET_ACT_GATE=m CONFIG_QRTR_SMD=m CONFIG_QRTR_TUN=m CONFIG_CAN=m +CONFIG_CAN_M_CAN=m +CONFIG_CAN_M_CAN_PLATFORM=m CONFIG_BT=m CONFIG_BT_HIDP=m # CONFIG_BT_LE is not set From patchwork Thu Apr 13 22:30:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Judith Mendez X-Patchwork-Id: 674201 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6F0DCC77B6F for ; Thu, 13 Apr 2023 22:31:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229636AbjDMWbO (ORCPT ); Thu, 13 Apr 2023 18:31:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47010 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229457AbjDMWbN (ORCPT ); Thu, 13 Apr 2023 18:31:13 -0400 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 304817AB4; Thu, 13 Apr 2023 15:31:12 -0700 (PDT) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 33DMUq9i016664; Thu, 13 Apr 2023 17:30:52 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1681425052; bh=1nmKT2A1OjUy31bEWZZBxae3cEYPA1EAPfeRQOHQjHk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=cVjxfJ5iEejHjKErniDFBTdO3TK5obGYpwMj2YAr/iybvgJWqac0bbeGm3F3evYqT VNmo0BK0FNYEDUNFlezRcu5Ufc0L6lRs256BGDUNFNnwtfoHjJ0mzRrNn8jx52+X/1 /grbkPccXJHnVxf113E8cZ+x5zV1P06Z+Qbl35UY= Received: from DFLE110.ent.ti.com (dfle110.ent.ti.com [10.64.6.31]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 33DMUqlP074961 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 13 Apr 2023 17:30:52 -0500 Received: from DFLE102.ent.ti.com (10.64.6.23) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Thu, 13 Apr 2023 17:30:52 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Thu, 13 Apr 2023 17:30:52 -0500 Received: from a0498204.dal.design.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 33DMUpa6063427; Thu, 13 Apr 2023 17:30:52 -0500 From: Judith Mendez To: Chandrasekar Ramakrishnan CC: Nishanth Menon , Vignesh Raghavendra , Andrew Davis , Wolfgang Grandegger , Marc Kleine-Budde , Rob Herring , Krzysztof Kozlowski , , , , , Schuyler Patton Subject: [RFC PATCH 3/5] dt-binding: can: m_can: Remove required interrupt attributes Date: Thu, 13 Apr 2023 17:30:49 -0500 Message-ID: <20230413223051.24455-4-jm@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230413223051.24455-1-jm@ti.com> References: <20230413223051.24455-1-jm@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Remove required attributes for interrupt and interrupt names since some MCANs may not have hardware interrupt routed to A53 Linux. Signed-off-by: Judith Mendez --- Documentation/devicetree/bindings/net/can/bosch,m_can.yaml | 2 -- 1 file changed, 2 deletions(-) diff --git a/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml b/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml index 67879aab623b..43f1aa9addc0 100644 --- a/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml +++ b/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml @@ -122,8 +122,6 @@ required: - compatible - reg - reg-names - - interrupts - - interrupt-names - clocks - clock-names - bosch,mram-cfg From patchwork Thu Apr 13 22:30:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Judith Mendez X-Patchwork-Id: 672897 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8091FC77B7D for ; Thu, 13 Apr 2023 22:31:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230020AbjDMWbQ (ORCPT ); Thu, 13 Apr 2023 18:31:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47050 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229924AbjDMWbO (ORCPT ); Thu, 13 Apr 2023 18:31:14 -0400 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A690C86AC; Thu, 13 Apr 2023 15:31:13 -0700 (PDT) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 33DMUqUC021540; Thu, 13 Apr 2023 17:30:52 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1681425052; bh=OEDwhwZYUg5c6D6b0NeNY00UKEjgXiSxHW2Wae+XH3Q=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=BXGfjo50zmrFTwH5KS3e4n2hyX4WGBEx8IJaKFJWH3gNHDHy8kOZtHWs+oSrawi5o CXdpBsDic+2TQRA+JpydvVhrEvKU77g5S30q6oAgeaEIbO/ftDrcCogVVQLMySVJH7 U9dLlozDD46bzmNnV91AHItM4rOWg50f/n83mP0Q= Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 33DMUqDM074970 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 13 Apr 2023 17:30:52 -0500 Received: from DFLE107.ent.ti.com (10.64.6.28) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Thu, 13 Apr 2023 17:30:52 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Thu, 13 Apr 2023 17:30:52 -0500 Received: from a0498204.dal.design.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 33DMUpa7063427; Thu, 13 Apr 2023 17:30:52 -0500 From: Judith Mendez To: Chandrasekar Ramakrishnan CC: Nishanth Menon , Vignesh Raghavendra , Andrew Davis , Wolfgang Grandegger , Marc Kleine-Budde , Rob Herring , Krzysztof Kozlowski , , , , , Schuyler Patton Subject: [RFC PATCH 4/5] arm64: dts: ti: Enable multiple MCAN for AM62x in MCU MCAN overlay Date: Thu, 13 Apr 2023 17:30:50 -0500 Message-ID: <20230413223051.24455-5-jm@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230413223051.24455-1-jm@ti.com> References: <20230413223051.24455-1-jm@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Enable two MCAN in MCU domain. AM62x does not have on-board CAN transcievers, so instead of changing the DTB permanently, add MCU MCAN nodes and transceiver nodes to a MCU MCAN overlay. If there are no hardware interrupts rounted to the GIC interrupt controller for MCAN IP, A53 Linux will not receive hardware interrupts. If an hrtimer is used to generate software interrupts, the two required interrupt attributes in the MCAN node do not have to be included. Signed-off-by: Judith Mendez --- arch/arm64/boot/dts/ti/Makefile | 2 +- .../boot/dts/ti/k3-am625-sk-mcan-mcu.dtso | 75 +++++++++++++++++++ 2 files changed, 76 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/ti/k3-am625-sk-mcan-mcu.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index abe15e76b614..c76be3888e4d 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -9,7 +9,7 @@ # alphabetically. # Boards with AM62x SoC -k3-am625-sk-mcan-dtbs := k3-am625-sk.dtb k3-am625-sk-mcan-main.dtbo +k3-am625-sk-mcan-dtbs := k3-am625-sk.dtb k3-am625-sk-mcan-main.dtbo k3-am625-sk-mcan-mcu.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am625-beagleplay.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-sk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-sk-mcan.dtb diff --git a/arch/arm64/boot/dts/ti/k3-am625-sk-mcan-mcu.dtso b/arch/arm64/boot/dts/ti/k3-am625-sk-mcan-mcu.dtso new file mode 100644 index 000000000000..777705aea546 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am625-sk-mcan-mcu.dtso @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT overlay for MCAN in MCU domain on AM625 SK + * + * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include + + +&{/} { + transceiver2: can-phy1 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + }; + + transceiver3: can-phy2 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + }; +}; + +&mcu_pmx0 { + mcu_mcan1_pins_default: mcu-mcan1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x038, PIN_INPUT, 0) /* (B3) MCU_MCAN0_RX */ + AM62X_IOPAD(0x034, PIN_OUTPUT, 0) /* (D6) MCU_MCAN0_TX */ + >; + }; + + mcu_mcan2_pins_default: mcu-mcan2-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x040, PIN_INPUT, 0) /* (D4) MCU_MCAN1_RX */ + AM62X_IOPAD(0x03C, PIN_OUTPUT, 0) /* (E5) MCU_MCAN1_TX */ + >; + }; +}; + +&cbass_mcu { + mcu_mcan1: can@4e00000 { + compatible = "bosch,m_can"; + reg = <0x00 0x4e00000 0x00 0x8000>, + <0x00 0x4e08000 0x00 0x200>; + reg-names = "message_ram", "m_can"; + power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 188 6>, <&k3_clks 188 1>; + clock-names = "hclk", "cclk"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan1_pins_default>; + phys = <&transceiver2>; + status = "okay"; + }; + + mcu_mcan2: can@4e10000 { + compatible = "bosch,m_can"; + reg = <0x00 0x4e10000 0x00 0x8000>, + <0x00 0x4e18000 0x00 0x200>; + reg-names = "message_ram", "m_can"; + power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 189 6>, <&k3_clks 189 1>; + clock-names = "hclk", "cclk"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan2_pins_default>; + phys = <&transceiver3>; + status = "okay"; + }; +}; From patchwork Thu Apr 13 22:30:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Judith Mendez X-Patchwork-Id: 672898 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 31CEAC77B61 for ; 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Thu, 13 Apr 2023 17:30:52 -0500 Received: from DFLE105.ent.ti.com (10.64.6.26) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Thu, 13 Apr 2023 17:30:52 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Thu, 13 Apr 2023 17:30:52 -0500 Received: from a0498204.dal.design.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 33DMUpa8063427; Thu, 13 Apr 2023 17:30:52 -0500 From: Judith Mendez To: Chandrasekar Ramakrishnan CC: Nishanth Menon , Vignesh Raghavendra , Andrew Davis , Wolfgang Grandegger , Marc Kleine-Budde , Rob Herring , Krzysztof Kozlowski , , , , , Schuyler Patton Subject: [RFC PATCH 5/5] can: m_can: Add hrtimer to generate software interrupt Date: Thu, 13 Apr 2023 17:30:51 -0500 Message-ID: <20230413223051.24455-6-jm@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230413223051.24455-1-jm@ti.com> References: <20230413223051.24455-1-jm@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add a hrtimer to MCAN struct. Each MCAN will have its own hrtimer instantiated if there is no hardware interrupt found. The hrtimer will generate a software interrupt every 1 ms. In hrtimer callback, we check if there is a transaction pending by reading a register, then process by calling the isr if there is. Signed-off-by: Judith Mendez --- drivers/net/can/m_can/m_can.c | 24 ++++++++++++++++++++++-- drivers/net/can/m_can/m_can.h | 3 +++ drivers/net/can/m_can/m_can_platform.c | 9 +++++++-- 3 files changed, 32 insertions(+), 4 deletions(-) diff --git a/drivers/net/can/m_can/m_can.c b/drivers/net/can/m_can/m_can.c index 8e83d6963d85..bb9d53f4d3cc 100644 --- a/drivers/net/can/m_can/m_can.c +++ b/drivers/net/can/m_can/m_can.c @@ -23,6 +23,7 @@ #include #include #include +#include #include "m_can.h" @@ -1584,6 +1585,11 @@ static int m_can_close(struct net_device *dev) if (!cdev->is_peripheral) napi_disable(&cdev->napi); + if (dev->irq < 0) { + dev_info(cdev->dev, "Disabling the hrtimer\n"); + hrtimer_cancel(&cdev->hrtimer); + } + m_can_stop(dev); m_can_clk_stop(cdev); free_irq(dev->irq, dev); @@ -1792,6 +1798,19 @@ static netdev_tx_t m_can_start_xmit(struct sk_buff *skb, return NETDEV_TX_OK; } +enum hrtimer_restart hrtimer_callback(struct hrtimer *timer) +{ + irqreturn_t ret; + struct m_can_classdev *cdev = + container_of(timer, struct m_can_classdev, hrtimer); + + ret = m_can_isr(0, cdev->net); + + hrtimer_forward_now(timer, ns_to_ktime(5 * NSEC_PER_MSEC)); + + return HRTIMER_RESTART; +} + static int m_can_open(struct net_device *dev) { struct m_can_classdev *cdev = netdev_priv(dev); @@ -1836,8 +1855,9 @@ static int m_can_open(struct net_device *dev) } if (err < 0) { - netdev_err(dev, "failed to request interrupt\n"); - goto exit_irq_fail; + dev_info(cdev->dev, "Enabling the hrtimer\n"); + cdev->hrtimer.function = &hrtimer_callback; + hrtimer_start(&cdev->hrtimer, ns_to_ktime(0), HRTIMER_MODE_REL_PINNED); } /* start the m_can controller */ diff --git a/drivers/net/can/m_can/m_can.h b/drivers/net/can/m_can/m_can.h index a839dc71dc9b..ed046d77fdb9 100644 --- a/drivers/net/can/m_can/m_can.h +++ b/drivers/net/can/m_can/m_can.h @@ -28,6 +28,7 @@ #include #include #include +#include /* m_can lec values */ enum m_can_lec_type { @@ -93,6 +94,8 @@ struct m_can_classdev { int is_peripheral; struct mram_cfg mcfg[MRAM_CFG_NUM]; + + struct hrtimer hrtimer; }; struct m_can_classdev *m_can_class_allocate_dev(struct device *dev, int sizeof_priv); diff --git a/drivers/net/can/m_can/m_can_platform.c b/drivers/net/can/m_can/m_can_platform.c index 9c1dcf838006..53e1648e9dab 100644 --- a/drivers/net/can/m_can/m_can_platform.c +++ b/drivers/net/can/m_can/m_can_platform.c @@ -7,6 +7,7 @@ #include #include +#include #include "m_can.h" @@ -98,8 +99,12 @@ static int m_can_plat_probe(struct platform_device *pdev) addr = devm_platform_ioremap_resource_byname(pdev, "m_can"); irq = platform_get_irq_byname(pdev, "int0"); if (IS_ERR(addr) || irq < 0) { - ret = -EINVAL; - goto probe_fail; + if (irq == -EPROBE_DEFER) { + ret = -EPROBE_DEFER; + goto probe_fail; + } + dev_info(mcan_class->dev, "Failed to get irq, initialize hrtimer\n"); + hrtimer_init(&mcan_class->hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL_PINNED); } /* message ram could be shared */