From patchwork Thu Apr 13 15:56:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kuogee Hsieh X-Patchwork-Id: 672867 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A51C8C77B6E for ; Thu, 13 Apr 2023 15:57:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231464AbjDMP5r (ORCPT ); Thu, 13 Apr 2023 11:57:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40746 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231549AbjDMP5m (ORCPT ); Thu, 13 Apr 2023 11:57:42 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9BC15B443; Thu, 13 Apr 2023 08:57:35 -0700 (PDT) Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 33DFtiAS023380; Thu, 13 Apr 2023 15:57:28 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : mime-version : content-type; s=qcppdkim1; bh=lgGwJBcQMhBKAkSJFoI9V99IVAmxurpS1N+u/QL3rq0=; b=ZL7n0yBY0Oge0sb3gRwX5qqw0zD+xz4ENG2rLhi/pbeAj6pO7sFQyAUWftzL8KpJXCUk Ogb0x/jcUuYyM2mBbomDJGTO/ZVDF+l+5uqTUy3f30skfJ4lVfwaD94/kHpMlOpwPy30 UBzbiJof1X9wEqxWhDnTDm/EKaIfJJs9liDXe09A+JTjYpmjrJpYqilRb6Fqo1pB7diu sFEIRUUYmVCFCjbswdBxdASJEsr6dyblsf/mfCST5zrxbZlfE9UZrRB6hCdo5XXmmRMm Uo2aGYulZ8aCj71YKuAsynslIS7tpb+lOv7Vfbhxsr1C3kcVAvJFO6JHt1c37Z8MMJHd CA== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3px6cnhscp-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 13 Apr 2023 15:57:27 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 33DFvQPF030062 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 13 Apr 2023 15:57:26 GMT Received: from khsieh-linux1.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Thu, 13 Apr 2023 08:56:56 -0700 From: Kuogee Hsieh To: , , , , , , , , , CC: , , , , , , Subject: [PATCH v2] drm/msm/dpu: always program dsc active bits Date: Thu, 13 Apr 2023 08:56:41 -0700 Message-ID: <1681401401-15099-1-git-send-email-quic_khsieh@quicinc.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: XqA7GVMGZUGk30xcLzuG4raDxlmGBVUj X-Proofpoint-GUID: XqA7GVMGZUGk30xcLzuG4raDxlmGBVUj X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-04-13_10,2023-04-13_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=894 priorityscore=1501 adultscore=0 mlxscore=0 malwarescore=0 suspectscore=0 phishscore=0 impostorscore=0 spamscore=0 bulkscore=0 lowpriorityscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2304130142 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org In current code, the DSC active bits are written only if cfg->dsc is set. However, for displays which are hot-pluggable, there can be a use-case of disconnecting a DSC supported sink and connecting a non-DSC sink. For those cases we need to clear DSC active bits during tear down. Changes in V2: 1) correct commit text as suggested 2) correct Fixes commit id 3) add FIXME comment Fixes: 77f6da90487c ("drm/msm/disp/dpu1: Add DSC support in hw_ctl") Signed-off-by: Kuogee Hsieh Reviewed-by: Marijn Suijten --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c index bbdc95c..1651cd7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c @@ -541,10 +541,10 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx, if (cfg->merge_3d) DPU_REG_WRITE(c, CTL_MERGE_3D_ACTIVE, BIT(cfg->merge_3d - MERGE_3D_0)); - if (cfg->dsc) { - DPU_REG_WRITE(&ctx->hw, CTL_FLUSH, DSC_IDX); - DPU_REG_WRITE(c, CTL_DSC_ACTIVE, cfg->dsc); - } + + /* FIXME: fix reset_intf_cfg to handle teardown of dsc */ + DPU_REG_WRITE(&ctx->hw, CTL_FLUSH, DSC_IDX); + DPU_REG_WRITE(c, CTL_DSC_ACTIVE, cfg->dsc); } static void dpu_hw_ctl_intf_cfg(struct dpu_hw_ctl *ctx,