From patchwork Wed Apr 12 03:30:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?U3RhbmxleSBDaGFuZ1vmmIzogrLlvrdd?= X-Patchwork-Id: 672823 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BD049C77B70 for ; Wed, 12 Apr 2023 03:30:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229527AbjDLDaX (ORCPT ); Tue, 11 Apr 2023 23:30:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34182 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229503AbjDLDaW (ORCPT ); Tue, 11 Apr 2023 23:30:22 -0400 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A620430CA for ; Tue, 11 Apr 2023 20:30:20 -0700 (PDT) Authenticated-By: X-SpamFilter-By: ArmorX SpamTrap 5.77 with qID 33C3TjLU2001685, This message is accepted by code: ctloc85258 Received: from mail.realtek.com (rtexh36506.realtek.com.tw[172.21.6.27]) by rtits2.realtek.com.tw (8.15.2/2.81/5.90) with ESMTPS id 33C3TjLU2001685 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=OK); Wed, 12 Apr 2023 11:29:45 +0800 Received: from RTEXMBS06.realtek.com.tw (172.21.6.99) by RTEXH36506.realtek.com.tw (172.21.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.17; Wed, 12 Apr 2023 11:30:06 +0800 Received: from RTEXH36505.realtek.com.tw (172.21.6.25) by RTEXMBS06.realtek.com.tw (172.21.6.99) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Wed, 12 Apr 2023 11:30:06 +0800 Received: from localhost.localdomain (172.21.252.101) by RTEXH36505.realtek.com.tw (172.21.6.25) with Microsoft SMTP Server id 15.1.2375.32 via Frontend Transport; Wed, 12 Apr 2023 11:30:06 +0800 From: Stanley Chang To: Thinh Nguyen CC: , Stanley Chang , Rob Herring Subject: [PATCH v2 1/2] usb: dwc3: core: add support for remapping global register start address Date: Wed, 12 Apr 2023 11:30:05 +0800 Message-ID: <20230412033006.10859-1-stanley_chang@realtek.com> X-Mailer: git-send-email 2.40.0 MIME-Version: 1.0 X-KSE-ServerInfo: RTEXMBS06.realtek.com.tw, 9 X-KSE-AntiSpam-Interceptor-Info: fallback X-KSE-Antivirus-Interceptor-Info: fallback X-KSE-AntiSpam-Interceptor-Info: fallback Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org The RTK DHC SoCs were designed the global register address offset at 0x8100. The default address is at DWC3_GLOBALS_REGS_START (0xc100). Therefore, add the property of device-tree to adjust this start address. Signed-off-by: Stanley Chang --- drivers/usb/dwc3/core.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 476b63618511..96d3e634ebbf 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -1785,6 +1785,24 @@ static int dwc3_probe(struct platform_device *pdev) dwc_res = *res; dwc_res.start += DWC3_GLOBALS_REGS_START; + /* + * For some dwc3 controller, the dwc3 global register start address is + * not at DWC3_GLOBALS_REGS_START (0xc100). + */ + if (dev->of_node) { + int global_regs_starting_offset = 0; + + device_property_read_u32(dev, "snps,global-regs-starting-offset", + &global_regs_starting_offset); + if (global_regs_starting_offset) { + dwc_res.start -= DWC3_GLOBALS_REGS_START; + dwc_res.start += global_regs_starting_offset; + dev_info(dev, + "dwc3 global register start address from 0x%x to end 0x%x\n", + (int)dwc_res.start, (int)dwc_res.end); + } + } + regs = devm_ioremap_resource(dev, &dwc_res); if (IS_ERR(regs)) return PTR_ERR(regs);