From patchwork Wed May 29 00:57:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 165315 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp9198348ili; Tue, 28 May 2019 17:57:23 -0700 (PDT) X-Google-Smtp-Source: APXvYqyjVVE6zwI/Wz356nH0EbBIZgudI0AQsFbaamRvLMXmHFUhqXoUTaMbA8JByd/wWG+Reb7A X-Received: by 2002:a62:4e0c:: with SMTP id c12mr20539305pfb.17.1559091443378; Tue, 28 May 2019 17:57:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1559091443; cv=none; d=google.com; s=arc-20160816; b=wh8inMjRqIseCQWHWjsQVDfFW7MKfHn3LqYB/o553m4mGICr2DFy/3UOrCXfK6aM0T hWOiefjFUsf5jiFWvP6WSdBh1UJIu4LhbQZa3OM7FYdMDHevdQGa41fkEbdeVZw1pcIe +FclypblvoZfhGdKuHPUNmpk1EAT1/tBQnfEXJ618sxattZl/lSo1tYJbr/CdDDlmOat N3yeyELEp4ezZ0HJEhzTImyTuhQ77ASAOlkuHMSLbV8yrF285gy2AMu+bB4qLd4x9wrt lTJ45Yp2RZ6Ay7xyiFyEM1t1jYOZuSwf4TQPPPAY/Yyx4oXIbML27DBN1zLtLshRbzxH IwjQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=hlEO6V7+iSB0usIkjd5ruLwMRHdYcss4+6c861fNe8Q=; b=y8hIm0Dhdwyn24uueeu/ZzTW1Bh/BUkvCZfAmm9M4/Lyat0FkZN1HxtwOkxh70iJpI XHYNo1DgjZIUF80Q1vvzerz2WwDhsLVTM6OO1gBIFzYpMD6prfZdjFcUMPCeDGU/N+aE Oc4e0dgy3FuTDHe9ZZMv3t8jGDJBDRpwL500MgIcZksbVrb4SMSFg1Udu/J6CnnBCoe+ 40pQwGmiHu6cKCZM1Ui2c2wWJFLJZHcUmFipPGF/sHj7Irphv7F9jLsTFnrf4u8QmHEd OzcL68/x9/4bg5b9wEQC3v+6enZZNHIimD7mmbiYN6TEDkru9gOs57R+yHKAiXAcUmhV 0E9g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QTTM4Pot; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id j1si25090033pfn.53.2019.05.28.17.57.23; Tue, 28 May 2019 17:57:23 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QTTM4Pot; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726068AbfE2A5R (ORCPT + 15 others); Tue, 28 May 2019 20:57:17 -0400 Received: from mail-pl1-f195.google.com ([209.85.214.195]:33748 "EHLO mail-pl1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726085AbfE2A5R (ORCPT ); Tue, 28 May 2019 20:57:17 -0400 Received: by mail-pl1-f195.google.com with SMTP id g21so282975plq.0 for ; Tue, 28 May 2019 17:57:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=hlEO6V7+iSB0usIkjd5ruLwMRHdYcss4+6c861fNe8Q=; b=QTTM4PotKaA4IWlNuUfDPwLnIF1aRDxixXGN67NyrM/MlBWhi35yl/zppSWddOJUcq bTRLWy2heNAW31E0waEi5L2qiWWBieOzF+urk+EolzhiIrFiKFgrQbDCntfNS42vMUAz LQ2HycxMig495CGrvMg/4Rfq+IBY1/In+hK/2I/6qanhZXy5DRxXyRYExDN1xM0Ugwwy Wk0LrQi3dvi6hr2M02Q0f2pzwmvgM8vefZpjaumkL1BVe4acYIGS5Jn+Jv3IT3aU4dOX xGPe1Ussyf7ZCZcN111RZmdbfQxIETr5ArFYhUgtpxUwFNOm9uy6ii+XqGrmJPCXjBs4 jjNw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=hlEO6V7+iSB0usIkjd5ruLwMRHdYcss4+6c861fNe8Q=; b=pxiEnJdbgCEMr0uzdZ8qTwzpKQT8739AxjkUStoS5XWcmIbNfB8D1itT/V3aK/p+aD Ft6wnHZ+gZnN37pUQHHwHXm7SZALGh9h2PFBP+Az2OYkOBJrLVNgO+VnJ+xYJvIGhrQ+ zrmGZqfHYry3CcWutQrDa591O82lKdZvrxX0SwxioADPkP8aL9BDW0FxaWFbuvWYV6tz NDGqyEoIoh03CXByJIreOU1xUjANt44SyjBmsBOLmYbD7HP4zPI5igSrvNWuXI6RkKEh pI4qYiuGHcpX4nePuSp5e6VtZYDk5Fij0XvnPJgrfaUvYycaJG6NmK6rRX9QS3gG5brk rpgA== X-Gm-Message-State: APjAAAUqXCzQDRXcC1HIWCRXsK3oHG2UxPJ/AcITdqGZDgLGSPEi5eip Qoc1lTy5CqIeKOrLAhBUDwAZsg== X-Received: by 2002:a17:902:b094:: with SMTP id p20mr111611096plr.164.1559091436245; Tue, 28 May 2019 17:57:16 -0700 (PDT) Received: from localhost.localdomain (104-188-17-28.lightspeed.sndgca.sbcglobal.net. [104.188.17.28]) by smtp.gmail.com with ESMTPSA id p16sm15434824pff.35.2019.05.28.17.57.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 28 May 2019 17:57:15 -0700 (PDT) From: Bjorn Andersson To: Lorenzo Pieralisi Cc: Bjorn Helgaas , Rob Herring , Mark Rutland , Stanimir Varbanov , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 2/3] dt-bindings: PCI: qcom: Add QCS404 to the binding Date: Tue, 28 May 2019 17:57:09 -0700 Message-Id: <20190529005710.23950-3-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190529005710.23950-1-bjorn.andersson@linaro.org> References: <20190529005710.23950-1-bjorn.andersson@linaro.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The Qualcomm QCS404 platform contains a PCIe controller, add this to the Qualcomm PCI binding document. The controller is the same version as the one used in IPQ4019, but the PHY part is described separately, hence the difference in clocks and resets. Reviewed-by: Rob Herring Reviewed-by: Vinod Koul Signed-off-by: Bjorn Andersson --- Changes since v4: - Picked up Vinod's r-b .../devicetree/bindings/pci/qcom,pcie.txt | 25 +++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-) -- 2.18.0 diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt index 1fd703bd73e0..ada80b01bf0c 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt @@ -10,6 +10,7 @@ - "qcom,pcie-msm8996" for msm8996 or apq8096 - "qcom,pcie-ipq4019" for ipq4019 - "qcom,pcie-ipq8074" for ipq8074 + - "qcom,pcie-qcs404" for qcs404 - reg: Usage: required @@ -116,6 +117,15 @@ - "ahb" AHB clock - "aux" Auxiliary clock +- clock-names: + Usage: required for qcs404 + Value type: + Definition: Should contain the following entries + - "iface" AHB clock + - "aux" Auxiliary clock + - "master_bus" AXI Master clock + - "slave_bus" AXI Slave clock + - resets: Usage: required Value type: @@ -167,6 +177,17 @@ - "ahb" AHB Reset - "axi_m_sticky" AXI Master Sticky reset +- reset-names: + Usage: required for qcs404 + Value type: + Definition: Should contain the following entries + - "axi_m" AXI Master reset + - "axi_s" AXI Slave reset + - "axi_m_sticky" AXI Master Sticky reset + - "pipe_sticky" PIPE sticky reset + - "pwr" PWR reset + - "ahb" AHB reset + - power-domains: Usage: required for apq8084 and msm8996/apq8096 Value type: @@ -195,12 +216,12 @@ Definition: A phandle to the PCIe endpoint power supply - phys: - Usage: required for apq8084 + Usage: required for apq8084 and qcs404 Value type: Definition: List of phandle(s) as listed in phy-names property - phy-names: - Usage: required for apq8084 + Usage: required for apq8084 and qcs404 Value type: Definition: Should contain "pciephy" From patchwork Wed May 29 00:57:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 165316 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp9198366ili; Tue, 28 May 2019 17:57:24 -0700 (PDT) X-Google-Smtp-Source: APXvYqy01zOkHLWWbSdLWAc4WyQAhMxZEn4OuAVc67rVNozx/8k2P1dCYkeoz470g41d0zLmq5CI X-Received: by 2002:a63:5b18:: with SMTP id p24mr28996087pgb.452.1559091444662; Tue, 28 May 2019 17:57:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1559091444; cv=none; d=google.com; s=arc-20160816; b=WSWTBS+xvmpsgfyAX65zvtFBI8WEu4R3NVHS0LJv22yVi02iByWdqnLpU4NItOc2E/ BkGQrlIRYGvdrFxwE73Lj1rht+UsgnsM35ttDXiHL7+RgIMw6jJZzZPcw9on1MWXHv1M v/iVyvXyF+wxhkYhrXZXZYiKrbHW0AQW7GCrkf/RPC8pdWoutwBWu7v91C4U7veLPwzO WUA+ObEOaBrWQTMd0N2TQTsTfYwDCZKLvB++k88a//3kpL1E/kw1XeT7jkeTbFa1hkkW O13JEqOUS99dgw72znDHVq4z5hNPfFNMQYKyT+gmfYw5WqNX+gpNowvBlbIJvnl8Qxr8 QjZA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=Wzk0rvDelDnq+wIqmO8ngZJJ8/wBww612QEapc+1RXA=; b=k2uVXAkOYUfU/lTADFRIB9IvbIg98cIhj/HrVnHycUS2nC8w/b00BYeCu4176rENhj kX+1u/fp2H4a81MfjivKbLsu7kTXHkBvHFEJ5hzjcjFyE/PFm+r35la6/Z2efuQ6sGBl nhyVqGt4bJ9hbH2WfD/1zh2SuBRojYRgJ4zlTx/AoeLh4ORTa28iZUcjLFY7CNssZvB4 KwkCquIRlZ7osPP/tToU4X+YZC2leg8QLKQX4dALqY/B3c1wWsATYTqi74GiZePh0nqj xPV1xlmKle9zLZV1t0pb7LUpDCNbgy3u3Y27j7BFgEu96+p2acrBczghVp+5n8scNP73 QWrw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MfPVeryc; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id j1si25090033pfn.53.2019.05.28.17.57.24; Tue, 28 May 2019 17:57:24 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MfPVeryc; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726155AbfE2A5S (ORCPT + 15 others); Tue, 28 May 2019 20:57:18 -0400 Received: from mail-pl1-f194.google.com ([209.85.214.194]:34953 "EHLO mail-pl1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726154AbfE2A5S (ORCPT ); Tue, 28 May 2019 20:57:18 -0400 Received: by mail-pl1-f194.google.com with SMTP id p1so275124plo.2 for ; Tue, 28 May 2019 17:57:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Wzk0rvDelDnq+wIqmO8ngZJJ8/wBww612QEapc+1RXA=; b=MfPVeryc778PT7zEV1xwpuPGTGjyYqJxhIvyGN3adsXOhm4REcLbOrAnhV3ZcsOHpI gQ/DLRkrdv+/GU4j24r7uB7NKASh7DJ0K5JERM7KnH47fVoqJB3aTGF6BL6KoMflmINz U2amAfWuTyTeYrFVWp53pPo0IOYq1TFCxUJJUgch8vVd+J8LOBhEzbmtYPa4FocRqAUK NshTzPDnE3dDp/zKdte+n9rl8wgtc7sc+iFUTUvGBh0ngQitetDsQ4gc8CGDyKWirU48 SAu22vSHsrv6kaFKDFiRNdqFvciWiBQJ5cIFZ3zoQRXdhRZLO8cN50mpmJeYGgHeMcSb 1SmQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Wzk0rvDelDnq+wIqmO8ngZJJ8/wBww612QEapc+1RXA=; b=tHwYdvogbHKl/ymcvRF0ZB2A4zkljVlSzDdqZSL3UveHM+ahNUuM1Lk7CdItpzcHjT aL3XUseGPmfsg1cZPEiM8FQb+/1qXDDn/v4OWWakqczu+Fg2O58SCLrY/JtxfVHI8I9v iD2+r098pNNeStfGpbzYZw+RntMrvzFXrw35z8kF+IKE0hAz+X2vevAznwditmnG13UM vNjjsYpyXx+LThvemBAjVwrxIi0jwktapcyiohy1gkgGu/VrnXVkAx/ANASugxXG11rk aLuOlXtM95S7uGuholuldJucZcbfAZ/Os0SJjkaYE5J5a/gUQhNk+WBxyqmF8eFKoOPM dPQg== X-Gm-Message-State: APjAAAXt3Ul19V5hVbVrXClVzUDfg9hw3XHQvWt0rtipeOk0qJIY8z/c 5bmBYO03DGM22JisQETPfru5EQ== X-Received: by 2002:a17:902:7c08:: with SMTP id x8mr924104pll.159.1559091437527; Tue, 28 May 2019 17:57:17 -0700 (PDT) Received: from localhost.localdomain (104-188-17-28.lightspeed.sndgca.sbcglobal.net. [104.188.17.28]) by smtp.gmail.com with ESMTPSA id p16sm15434824pff.35.2019.05.28.17.57.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 28 May 2019 17:57:16 -0700 (PDT) From: Bjorn Andersson To: Lorenzo Pieralisi Cc: Bjorn Helgaas , Rob Herring , Mark Rutland , Stanimir Varbanov , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 3/3] PCI: qcom: Add QCS404 PCIe controller support Date: Tue, 28 May 2019 17:57:10 -0700 Message-Id: <20190529005710.23950-4-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190529005710.23950-1-bjorn.andersson@linaro.org> References: <20190529005710.23950-1-bjorn.andersson@linaro.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The QCS404 platform contains a PCIe controller of version 2.4.0 and a Qualcomm PCIe2 PHY. The driver already supports version 2.4.0, for the IPQ4019, but this support touches clocks and resets related to the PHY as well, and there's no upstream driver for the PHY. On QCS404 we must initialize the PHY, so a separate PHY driver is implemented to take care of this and the controller driver is updated to not require the PHY related resources. This is done by relying on the fact that operations in both the clock and reset framework are nops when passed NULL, so we can isolate this change to only the get_resource function. For QCS404 we also need to enable the AHB (iface) clock, in order to access the register space of the controller, but as this is not part of the IPQ4019 DT binding this is only added for new users of the 2.4.0 controller. Acked-by: Stanimir Varbanov Reviewed-by: Niklas Cassel Reviewed-by: Vinod Koul Signed-off-by: Bjorn Andersson --- Changes since v4: - Picked up Vinod's r-b and Stanimir's a-b drivers/pci/controller/dwc/pcie-qcom.c | 64 +++++++++++++++----------- 1 file changed, 38 insertions(+), 26 deletions(-) -- 2.18.0 diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 23dc01212508..da5dd3639a49 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -112,7 +112,7 @@ struct qcom_pcie_resources_2_3_2 { struct regulator_bulk_data supplies[QCOM_PCIE_2_3_2_MAX_SUPPLY]; }; -#define QCOM_PCIE_2_4_0_MAX_CLOCKS 3 +#define QCOM_PCIE_2_4_0_MAX_CLOCKS 4 struct qcom_pcie_resources_2_4_0 { struct clk_bulk_data clks[QCOM_PCIE_2_4_0_MAX_CLOCKS]; int num_clks; @@ -638,13 +638,16 @@ static int qcom_pcie_get_resources_2_4_0(struct qcom_pcie *pcie) struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0; struct dw_pcie *pci = pcie->pci; struct device *dev = pci->dev; + bool is_ipq = of_device_is_compatible(dev->of_node, "qcom,pcie-ipq4019"); int ret; res->clks[0].id = "aux"; res->clks[1].id = "master_bus"; res->clks[2].id = "slave_bus"; + res->clks[3].id = "iface"; - res->num_clks = 3; + /* qcom,pcie-ipq4019 is defined without "iface" */ + res->num_clks = is_ipq ? 3 : 4; ret = devm_clk_bulk_get(dev, res->num_clks, res->clks); if (ret < 0) @@ -658,27 +661,33 @@ static int qcom_pcie_get_resources_2_4_0(struct qcom_pcie *pcie) if (IS_ERR(res->axi_s_reset)) return PTR_ERR(res->axi_s_reset); - res->pipe_reset = devm_reset_control_get_exclusive(dev, "pipe"); - if (IS_ERR(res->pipe_reset)) - return PTR_ERR(res->pipe_reset); - - res->axi_m_vmid_reset = devm_reset_control_get_exclusive(dev, - "axi_m_vmid"); - if (IS_ERR(res->axi_m_vmid_reset)) - return PTR_ERR(res->axi_m_vmid_reset); - - res->axi_s_xpu_reset = devm_reset_control_get_exclusive(dev, - "axi_s_xpu"); - if (IS_ERR(res->axi_s_xpu_reset)) - return PTR_ERR(res->axi_s_xpu_reset); - - res->parf_reset = devm_reset_control_get_exclusive(dev, "parf"); - if (IS_ERR(res->parf_reset)) - return PTR_ERR(res->parf_reset); - - res->phy_reset = devm_reset_control_get_exclusive(dev, "phy"); - if (IS_ERR(res->phy_reset)) - return PTR_ERR(res->phy_reset); + if (is_ipq) { + /* + * These resources relates to the PHY or are secure clocks, but + * are controlled here for IPQ4019 + */ + res->pipe_reset = devm_reset_control_get_exclusive(dev, "pipe"); + if (IS_ERR(res->pipe_reset)) + return PTR_ERR(res->pipe_reset); + + res->axi_m_vmid_reset = devm_reset_control_get_exclusive(dev, + "axi_m_vmid"); + if (IS_ERR(res->axi_m_vmid_reset)) + return PTR_ERR(res->axi_m_vmid_reset); + + res->axi_s_xpu_reset = devm_reset_control_get_exclusive(dev, + "axi_s_xpu"); + if (IS_ERR(res->axi_s_xpu_reset)) + return PTR_ERR(res->axi_s_xpu_reset); + + res->parf_reset = devm_reset_control_get_exclusive(dev, "parf"); + if (IS_ERR(res->parf_reset)) + return PTR_ERR(res->parf_reset); + + res->phy_reset = devm_reset_control_get_exclusive(dev, "phy"); + if (IS_ERR(res->phy_reset)) + return PTR_ERR(res->phy_reset); + } res->axi_m_sticky_reset = devm_reset_control_get_exclusive(dev, "axi_m_sticky"); @@ -698,9 +707,11 @@ static int qcom_pcie_get_resources_2_4_0(struct qcom_pcie *pcie) if (IS_ERR(res->ahb_reset)) return PTR_ERR(res->ahb_reset); - res->phy_ahb_reset = devm_reset_control_get_exclusive(dev, "phy_ahb"); - if (IS_ERR(res->phy_ahb_reset)) - return PTR_ERR(res->phy_ahb_reset); + if (is_ipq) { + res->phy_ahb_reset = devm_reset_control_get_exclusive(dev, "phy_ahb"); + if (IS_ERR(res->phy_ahb_reset)) + return PTR_ERR(res->phy_ahb_reset); + } return 0; } @@ -1268,6 +1279,7 @@ static const struct of_device_id qcom_pcie_match[] = { { .compatible = "qcom,pcie-msm8996", .data = &ops_2_3_2 }, { .compatible = "qcom,pcie-ipq8074", .data = &ops_2_3_3 }, { .compatible = "qcom,pcie-ipq4019", .data = &ops_2_4_0 }, + { .compatible = "qcom,pcie-qcs404", .data = &ops_2_4_0 }, { } };