From patchwork Mon May 27 08:34:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 165198 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp6873065ili; Mon, 27 May 2019 01:35:20 -0700 (PDT) X-Google-Smtp-Source: APXvYqyRDxL+Y56VnzoOOfLJUAONCcV46VF3XKpKqJgETJDzypHBmpqzToE+Dvsy4L7OsH33jR95 X-Received: by 2002:aa7:910e:: with SMTP id 14mr105246990pfh.153.1558946120059; Mon, 27 May 2019 01:35:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1558946120; cv=none; d=google.com; s=arc-20160816; b=dfwZswhov6rWWPaRrOTiWpAsksIMii/ci0wwv1rYvFc7ATHyJl1K3hJq4qR3Cs4Hum cIA3jcjdAxQMEoj5UD5D7+GvMAyratdOBZoiGCJniT7XaQ6r1ifyuE5ZQU17wh1J/jRt phknODoGCUoQIesmpXdS2EP1+ULGaSknRh0wmOE/Ws94d0WiDXHcaeIDvGV3p9CBXHI1 jsX/KB4YgkApgFNMQXw2cD4do5D5ik1E+f6KTsv0T9YiLL2wLwjSqgqo3WDItL4JpeEh 7FpIaBzln9WiOs9w7xY/O5YC6H74GrvDG4R7whJrzqE2KyO3UnFVzb2d0vnmoXcvP1Sf 5kaQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:dkim-filter; bh=45A2T5W61qPsoviArJh2p+JJaGRj8IKGUEzep9QlvkI=; b=BCK7zXyQYsgQYH85HGRGX4bFaiOSexQYtrkqBxXbR6AXIQESR6SSE21S9rnkq8J+vX IS0Zas/A7jQHPIirdCwPxwgDc2t9DOJiL5O6d4xHeQiZV5gNZGVVF5pPlUAQ8SMtWZ1/ FcJt2LlTCqjMeiFh26d1MsIO2/CqiAVRThEtCH1bkkQnAIjKIPjoaAUzjfHssoqYUfr9 unVWDEwhHS9vxy4tRm7qWtl2z5kAi2ufwNP66Bz6BqC4Fn6dbXoXGTyeIdh2aLFNWDI7 Ob9S/zh9nxcjwh3kXaxJJcdQwrNrOzsJu81dJxeYPTyJRdO4ZYcD6gbceT559fmh0bW9 jF/g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=KC5a03Bc; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s1si16881433pjb.23.2019.05.27.01.35.19; Mon, 27 May 2019 01:35:20 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=KC5a03Bc; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726583AbfE0IfS (ORCPT + 30 others); Mon, 27 May 2019 04:35:18 -0400 Received: from conuserg-10.nifty.com ([210.131.2.77]:51186 "EHLO conuserg-10.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726500AbfE0IfS (ORCPT ); Mon, 27 May 2019 04:35:18 -0400 Received: from localhost.localdomain (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-10.nifty.com with ESMTP id x4R8Yoq4030794; Mon, 27 May 2019 17:34:51 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-10.nifty.com x4R8Yoq4030794 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1558946092; bh=45A2T5W61qPsoviArJh2p+JJaGRj8IKGUEzep9QlvkI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KC5a03BcFatHw2Ht8RdXo/6qQt02T3aH5CE8kRYJwu2x5MtspNHSoYPGqUSN3LfIM 2o124MeKsXE0Yw8kRRuf9LdRDpYRoToFVQFcSpC8g+3PPMRCCTQW1fLvTp0ljFAuSC USO7/CDaX482PYpPuDEILX8MnBkTCG/dzGeufIpH14CwdL4Vr9YrRFpIJ/M6PXL0QJ K5kI+VoPmxIQ4gHSbvigY4d1HguDFSt2KDI7c1IKX0n2SqMPqZM/tea3VVEPiwoqsa jN6cJxu+RBrg++NBcP+/HBH+gWq1lnmAz0i0mORROwbCbBH9mRq7tnjo9uC0Bw0QEE Bcz8Lnlv0mv9Q== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: linux-arm-kernel@lists.infradead.org, Will Deacon Cc: linux-kernel@vger.kernel.org, Catalin Marinas , Masahiro Yamada Subject: [PATCH 1/2] linux/bits.h: make BIT(), GENMASK(), and friends available in assembly Date: Mon, 27 May 2019 17:34:11 +0900 Message-Id: <20190527083412.26651-2-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190527083412.26651-1-yamada.masahiro@socionext.com> References: <20190527083412.26651-1-yamada.masahiro@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org BIT(), GENMASK(), etc. are useful to define register bits of hardware. However, low-level code is often written in assembly, where they are not available due to the hard-coded 1UL, 0UL. In fact, in-kernel headers such as arch/arm64/include/asm/sysreg.h use _BITUL() instead of BIT() so that the register bit macros are available in assembly. Using macros in include/uapi/linux/const.h have two reasons: [1] For use in uapi headers We should use underscore-prefixed variants for user-space. [2] For use in assembly code Since _BITUL() does not use hard-coded 1UL, it can be used as an alternative of BIT(). For [2], it is pretty easy to change BIT() etc. for use in assembly. This allows to replace _BUTUL() in kernel headers with BIT(). Signed-off-by: Masahiro Yamada --- include/linux/bits.h | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) -- 2.17.1 Acked-by: Will Deacon diff --git a/include/linux/bits.h b/include/linux/bits.h index 2b7b532c1d51..669d69441a62 100644 --- a/include/linux/bits.h +++ b/include/linux/bits.h @@ -1,13 +1,15 @@ /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __LINUX_BITS_H #define __LINUX_BITS_H + +#include #include -#define BIT(nr) (1UL << (nr)) -#define BIT_ULL(nr) (1ULL << (nr)) -#define BIT_MASK(nr) (1UL << ((nr) % BITS_PER_LONG)) +#define BIT(nr) (UL(1) << (nr)) +#define BIT_ULL(nr) (ULL(1) << (nr)) +#define BIT_MASK(nr) (UL(1) << ((nr) % BITS_PER_LONG)) #define BIT_WORD(nr) ((nr) / BITS_PER_LONG) -#define BIT_ULL_MASK(nr) (1ULL << ((nr) % BITS_PER_LONG_LONG)) +#define BIT_ULL_MASK(nr) (ULL(1) << ((nr) % BITS_PER_LONG_LONG)) #define BIT_ULL_WORD(nr) ((nr) / BITS_PER_LONG_LONG) #define BITS_PER_BYTE 8 @@ -17,10 +19,11 @@ * GENMASK_ULL(39, 21) gives us the 64bit vector 0x000000ffffe00000. */ #define GENMASK(h, l) \ - (((~0UL) - (1UL << (l)) + 1) & (~0UL >> (BITS_PER_LONG - 1 - (h)))) + (((~UL(0)) - (UL(1) << (l)) + 1) & \ + (~UL(0) >> (BITS_PER_LONG - 1 - (h)))) #define GENMASK_ULL(h, l) \ - (((~0ULL) - (1ULL << (l)) + 1) & \ - (~0ULL >> (BITS_PER_LONG_LONG - 1 - (h)))) + (((~ULL(0)) - (ULL(1) << (l)) + 1) & \ + (~ULL(0) >> (BITS_PER_LONG_LONG - 1 - (h)))) #endif /* __LINUX_BITS_H */ From patchwork Mon May 27 08:34:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 165199 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp6873098ili; Mon, 27 May 2019 01:35:22 -0700 (PDT) X-Google-Smtp-Source: APXvYqz3k7OkJyxuLGgMDqXOeX+Tw8zcxe+FTZi/WzmXhZ3D1DIG+hySBKzzxr9LUnDmfaIkvKmR X-Received: by 2002:a62:7fcd:: with SMTP id a196mr85942264pfd.195.1558946122221; Mon, 27 May 2019 01:35:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1558946122; cv=none; d=google.com; s=arc-20160816; b=V1i+h9BuR32f1ymMeuPVmuUzhPRI1qUQapJhVnZ29Xm4eAFZl3WZmqB1clwB1RePNX 6C/fwWw9hvlV13IfNNxAKfCReLkWitHbHXB/oh+zWBkPQmt3krusWExh7UPZR361hFr2 bffLHdiBjxmzwj+WkRAyB5CeaLG2LbhZfn5StUhVA81dTM8yO341gjMl+2likxAA67M+ 4a7iUHw+YyKHuhGq8iUqEzwipwOMj47QlTh5iBWm3g2L9o/GVbZTuGM0yjB7BhHozqcz yHQbgJJKLGrVFHhAso2b7p5GTJXMUvm8WgcwX6wyv6ndbL2zMDnkeVnS0ElTM+4rt4oj rE5w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:dkim-filter; bh=dq9Xozr64FzGVJ+aw2LL+eX9eu8zuBNETqzyhb/EVhQ=; b=JETCMVL+Q6kmXtJhnoZK2DpBhK6eKAJ9BRU2vBHjbL0x0bdGqsPM2Kcw4sXi+TY+oY y5iP1JBB8Qe6oRUuom9ItByR1HjpGjep3A1LNAq8GhOiCr6yIvfCMAStG2I5kjkVQZHm TI+2euG4JTfwvnkEX55aL8kV2nqkNkqnnsu4V7pMPiQo5mQne85wrPt1neI5vrI+xSbE 57eBdkByeAXxNsHwd6k9vscEtsylW0p2NLCyag448h/oU+x0hTZe3iwZgHZnP8ScworF j4aRNNEUdpfzrng/xx1shPLesCdrExLKRI+mozlQjmKXsFh8+fKsjDnUKGDuTmoBcjxf /3Mg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b="M6SAS/b8"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id d16si17710246pfr.229.2019.05.27.01.35.21; Mon, 27 May 2019 01:35:22 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b="M6SAS/b8"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726626AbfE0IfU (ORCPT + 30 others); Mon, 27 May 2019 04:35:20 -0400 Received: from conuserg-10.nifty.com ([210.131.2.77]:51185 "EHLO conuserg-10.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726497AbfE0IfT (ORCPT ); Mon, 27 May 2019 04:35:19 -0400 Received: from localhost.localdomain (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-10.nifty.com with ESMTP id x4R8Yoq5030794; Mon, 27 May 2019 17:34:52 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-10.nifty.com x4R8Yoq5030794 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1558946092; bh=dq9Xozr64FzGVJ+aw2LL+eX9eu8zuBNETqzyhb/EVhQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=M6SAS/b8mE3OxMR28tPr3uw2XKcJx7epVWglKLCGQV0VSwDlgDRSUIDMBkIrwzoMY feRhow4SiPG8eA4DViP6qEZ/GpGOYaz8Lm8XbP6e0kALHqzW1WMC5eXpVREMXwTtCs 5fv65DAg3t5ETuJTxLT6bKLwbbZQHbSiS8YuK39fFXL2Jkwl8Rc+R7Igp/82ByyGzz ijp1qJqLfQbFePMjlB9Z2vwKcbSe2DjGxpUku1HEvr61MLCU9ZA847Pz9ufRM01/il JBrTprEN8hnLGRo8/cUTLWTsjN9r7JY9GYqkBPch7+VuOwP/8OVYiYnWnIF8F3pZN3 xXFOHyaiEE+EA== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: linux-arm-kernel@lists.infradead.org, Will Deacon Cc: linux-kernel@vger.kernel.org, Catalin Marinas , Masahiro Yamada Subject: [PATCH 2/2] arm64: replace _BITUL() with BIT() Date: Mon, 27 May 2019 17:34:12 +0900 Message-Id: <20190527083412.26651-3-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190527083412.26651-1-yamada.masahiro@socionext.com> References: <20190527083412.26651-1-yamada.masahiro@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Now that BIT() can be used from assembly code, replace _BITUL() with equivalent BIT(). Signed-off-by: Masahiro Yamada --- arch/arm64/include/asm/sysreg.h | 82 ++++++++++++++++----------------- 1 file changed, 41 insertions(+), 41 deletions(-) -- 2.17.1 Acked-by: Will Deacon diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 902d75b60914..3bcd8294acc0 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -20,7 +20,7 @@ #ifndef __ASM_SYSREG_H #define __ASM_SYSREG_H -#include +#include #include /* @@ -458,31 +458,31 @@ #define SYS_ZCR_EL12 sys_reg(3, 5, 1, 2, 0) /* Common SCTLR_ELx flags. */ -#define SCTLR_ELx_DSSBS (_BITUL(44)) -#define SCTLR_ELx_ENIA (_BITUL(31)) -#define SCTLR_ELx_ENIB (_BITUL(30)) -#define SCTLR_ELx_ENDA (_BITUL(27)) -#define SCTLR_ELx_EE (_BITUL(25)) -#define SCTLR_ELx_IESB (_BITUL(21)) -#define SCTLR_ELx_WXN (_BITUL(19)) -#define SCTLR_ELx_ENDB (_BITUL(13)) -#define SCTLR_ELx_I (_BITUL(12)) -#define SCTLR_ELx_SA (_BITUL(3)) -#define SCTLR_ELx_C (_BITUL(2)) -#define SCTLR_ELx_A (_BITUL(1)) -#define SCTLR_ELx_M (_BITUL(0)) +#define SCTLR_ELx_DSSBS (BIT(44)) +#define SCTLR_ELx_ENIA (BIT(31)) +#define SCTLR_ELx_ENIB (BIT(30)) +#define SCTLR_ELx_ENDA (BIT(27)) +#define SCTLR_ELx_EE (BIT(25)) +#define SCTLR_ELx_IESB (BIT(21)) +#define SCTLR_ELx_WXN (BIT(19)) +#define SCTLR_ELx_ENDB (BIT(13)) +#define SCTLR_ELx_I (BIT(12)) +#define SCTLR_ELx_SA (BIT(3)) +#define SCTLR_ELx_C (BIT(2)) +#define SCTLR_ELx_A (BIT(1)) +#define SCTLR_ELx_M (BIT(0)) #define SCTLR_ELx_FLAGS (SCTLR_ELx_M | SCTLR_ELx_A | SCTLR_ELx_C | \ SCTLR_ELx_SA | SCTLR_ELx_I | SCTLR_ELx_IESB) /* SCTLR_EL2 specific flags. */ -#define SCTLR_EL2_RES1 ((_BITUL(4)) | (_BITUL(5)) | (_BITUL(11)) | (_BITUL(16)) | \ - (_BITUL(18)) | (_BITUL(22)) | (_BITUL(23)) | (_BITUL(28)) | \ - (_BITUL(29))) -#define SCTLR_EL2_RES0 ((_BITUL(6)) | (_BITUL(7)) | (_BITUL(8)) | (_BITUL(9)) | \ - (_BITUL(10)) | (_BITUL(13)) | (_BITUL(14)) | (_BITUL(15)) | \ - (_BITUL(17)) | (_BITUL(20)) | (_BITUL(24)) | (_BITUL(26)) | \ - (_BITUL(27)) | (_BITUL(30)) | (_BITUL(31)) | \ +#define SCTLR_EL2_RES1 ((BIT(4)) | (BIT(5)) | (BIT(11)) | (BIT(16)) | \ + (BIT(18)) | (BIT(22)) | (BIT(23)) | (BIT(28)) | \ + (BIT(29))) +#define SCTLR_EL2_RES0 ((BIT(6)) | (BIT(7)) | (BIT(8)) | (BIT(9)) | \ + (BIT(10)) | (BIT(13)) | (BIT(14)) | (BIT(15)) | \ + (BIT(17)) | (BIT(20)) | (BIT(24)) | (BIT(26)) | \ + (BIT(27)) | (BIT(30)) | (BIT(31)) | \ (0xffffefffUL << 32)) #ifdef CONFIG_CPU_BIG_ENDIAN @@ -504,23 +504,23 @@ #endif /* SCTLR_EL1 specific flags. */ -#define SCTLR_EL1_UCI (_BITUL(26)) -#define SCTLR_EL1_E0E (_BITUL(24)) -#define SCTLR_EL1_SPAN (_BITUL(23)) -#define SCTLR_EL1_NTWE (_BITUL(18)) -#define SCTLR_EL1_NTWI (_BITUL(16)) -#define SCTLR_EL1_UCT (_BITUL(15)) -#define SCTLR_EL1_DZE (_BITUL(14)) -#define SCTLR_EL1_UMA (_BITUL(9)) -#define SCTLR_EL1_SED (_BITUL(8)) -#define SCTLR_EL1_ITD (_BITUL(7)) -#define SCTLR_EL1_CP15BEN (_BITUL(5)) -#define SCTLR_EL1_SA0 (_BITUL(4)) - -#define SCTLR_EL1_RES1 ((_BITUL(11)) | (_BITUL(20)) | (_BITUL(22)) | (_BITUL(28)) | \ - (_BITUL(29))) -#define SCTLR_EL1_RES0 ((_BITUL(6)) | (_BITUL(10)) | (_BITUL(13)) | (_BITUL(17)) | \ - (_BITUL(27)) | (_BITUL(30)) | (_BITUL(31)) | \ +#define SCTLR_EL1_UCI (BIT(26)) +#define SCTLR_EL1_E0E (BIT(24)) +#define SCTLR_EL1_SPAN (BIT(23)) +#define SCTLR_EL1_NTWE (BIT(18)) +#define SCTLR_EL1_NTWI (BIT(16)) +#define SCTLR_EL1_UCT (BIT(15)) +#define SCTLR_EL1_DZE (BIT(14)) +#define SCTLR_EL1_UMA (BIT(9)) +#define SCTLR_EL1_SED (BIT(8)) +#define SCTLR_EL1_ITD (BIT(7)) +#define SCTLR_EL1_CP15BEN (BIT(5)) +#define SCTLR_EL1_SA0 (BIT(4)) + +#define SCTLR_EL1_RES1 ((BIT(11)) | (BIT(20)) | (BIT(22)) | (BIT(28)) | \ + (BIT(29))) +#define SCTLR_EL1_RES0 ((BIT(6)) | (BIT(10)) | (BIT(13)) | (BIT(17)) | \ + (BIT(27)) | (BIT(30)) | (BIT(31)) | \ (0xffffefffUL << 32)) #ifdef CONFIG_CPU_BIG_ENDIAN @@ -735,13 +735,13 @@ #define ZCR_ELx_LEN_SIZE 9 #define ZCR_ELx_LEN_MASK 0x1ff -#define CPACR_EL1_ZEN_EL1EN (_BITUL(16)) /* enable EL1 access */ -#define CPACR_EL1_ZEN_EL0EN (_BITUL(17)) /* enable EL0 access, if EL1EN set */ +#define CPACR_EL1_ZEN_EL1EN (BIT(16)) /* enable EL1 access */ +#define CPACR_EL1_ZEN_EL0EN (BIT(17)) /* enable EL0 access, if EL1EN set */ #define CPACR_EL1_ZEN (CPACR_EL1_ZEN_EL1EN | CPACR_EL1_ZEN_EL0EN) /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */ -#define SYS_MPIDR_SAFE_VAL (_BITUL(31)) +#define SYS_MPIDR_SAFE_VAL (BIT(31)) #ifdef __ASSEMBLY__