From patchwork Sat Apr 8 21:40:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 671958 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 47736C77B73 for ; Sat, 8 Apr 2023 21:40:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229458AbjDHVkw (ORCPT ); Sat, 8 Apr 2023 17:40:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38892 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229486AbjDHVkv (ORCPT ); Sat, 8 Apr 2023 17:40:51 -0400 Received: from mail-wr1-x433.google.com (mail-wr1-x433.google.com [IPv6:2a00:1450:4864:20::433]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 06361976B for ; Sat, 8 Apr 2023 14:40:50 -0700 (PDT) Received: by mail-wr1-x433.google.com with SMTP id t4so39632907wra.7 for ; Sat, 08 Apr 2023 14:40:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680990048; x=1683582048; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=G/ds8fvt8IhNIUkcMPcB2187U+f/tO5X7bx8/qa8ONM=; b=m0SLzn1iqfD6YsYtHojGNxnFSimTvg28gxXYWGvhbeFi3ywBXyW2aKpPKcOOnk81GA pLcEC/zzrZ2ZJakFH4GZvs1NXYVS8Q5ZATw+aSem6W2Z4reoZoq35ICKnVa68eA/Po/7 BFDtRtkmaD6WxD4wCiLae4gl/1Q2r4k3JeKUpjo012rA+ctcgAR0df1Cf5XPDm4XLmRV YMWY1CvCaELFO2/x7NQzHDQWbhzCpl7SOTToN6mh4//P9fwC7b1iIqg+NZ8ZIVkIWySc Pi2SUMiMC5Z6faMkDkzq3p3ZxBXZ2Nq+Es4E+Y0cqnd3Kht+YjeQRGlh9xH60wew+601 brew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680990048; x=1683582048; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=G/ds8fvt8IhNIUkcMPcB2187U+f/tO5X7bx8/qa8ONM=; b=RFB8ZwDa8+IX+OlgWRdyROLt1g6m5LEACPdoz2TOk8YzNzFF8MUbmLsAO5PjBwdptm r/+M69dewEEgfV0tthUur2LLiewrKtf4k3lBunAjy881K19LiyStpMfupV8zE7Zidi8d U0BwMCSIB/w2pHqrwptfsJtOSnpe9ebA0ZtYSbwofoxIRmwFqe6dx5SYYP0s0xPbsyCJ XFUKyPXnQhJwVqdajiqEwkNoQ63hwbvSNC0JItJg5E8Xo7kCA2ado/M6M2WP34+m2lYJ wjQWicbTxqbTEqi1KAwDl9TZv+ZaaXh7ceM7K4dEMIu4i+tjvTbOtw5uZYrrnL1oGuz+ g02A== X-Gm-Message-State: AAQBX9fLDmFa18jrOkc1giwzWwrcp098yIaGOnoyiyn+IO8AYIz1xbQt QTOBZWd/OPqscreD0Y+coihDkg== X-Google-Smtp-Source: AKy350ZoIOX+1ULO+/6nI4Sk6F63spIEVpgG402AEJu/jOF7CaFaEsl7we9f/uNDu20eJD4ZJ49o7A== X-Received: by 2002:adf:dc07:0:b0:2e2:730a:c7de with SMTP id t7-20020adfdc07000000b002e2730ac7demr1863136wri.24.1680990048420; Sat, 08 Apr 2023 14:40:48 -0700 (PDT) Received: from localhost.localdomain ([188.25.26.161]) by smtp.gmail.com with ESMTPSA id s6-20020a5d4ec6000000b002efb6e0c495sm3061377wrv.91.2023.04.08.14.40.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 08 Apr 2023 14:40:48 -0700 (PDT) From: Abel Vesa To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Konrad Dybcio , Manivannan Sadhasivam , Alim Akhtar , Avri Altman , Bart Van Assche , Adrian Hunter , "James E . J . Bottomley" , "Martin K . Petersen" , Herbert Xu , "David S . Miller" , Eric Biggers Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, Linux Kernel Mailing List , linux-arm-msm@vger.kernel.org, linux-crypto@vger.kernel.org, linux-scsi@vger.kernel.org Subject: [PATCH v7 1/3] dt-bindings: ufs: qcom: Add ICE phandle Date: Sun, 9 Apr 2023 00:40:39 +0300 Message-Id: <20230408214041.533749-2-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230408214041.533749-1-abel.vesa@linaro.org> References: <20230408214041.533749-1-abel.vesa@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Starting with SM8550, the ICE will have its own devicetree node so add the qcom,ice property to reference it. Signed-off-by: Abel Vesa Reviewed-by: Krzysztof Kozlowski Reviewed-by: tag. But let's just get the bindings fixed. --- The v6 is here: https://lore.kernel.org/all/20230407105029.2274111-3-abel.vesa@linaro.org/ Changes since v6: * Dropped the minItems for both the qcom,ice and the reg in the qcom,ice compatile subschema, like Krzysztof suggested Changes since v5: * dropped the sm8550 specific subschema and replaced it with one that mutually excludes the qcom,ice vs both the ICE specific reg range and the ICE clock Changes since v4: * Added check for sm8550 compatible w.r.t. qcom,ice in order to enforce it while making sure none of the other platforms are allowed to use it Changes since v3: * dropped the "and drop core clock" part from subject line Changes since v2: * dropped all changes except the qcom,ice property .../devicetree/bindings/ufs/qcom,ufs.yaml | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml index c5a06c048389..10d426ba1959 100644 --- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml +++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml @@ -70,6 +70,10 @@ properties: power-domains: maxItems: 1 + qcom,ice: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to the Inline Crypto Engine node + reg: minItems: 1 maxItems: 2 @@ -187,6 +191,26 @@ allOf: # TODO: define clock bindings for qcom,msm8994-ufshc + - if: + properties: + qcom,ice: + maxItems: 1 + then: + properties: + reg: + maxItems: 1 + clocks: + minItems: 8 + maxItems: 8 + else: + properties: + reg: + minItems: 2 + maxItems: 2 + clocks: + minItems: 9 + maxItems: 11 + unevaluatedProperties: false examples: From patchwork Sat Apr 8 21:40:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 671957 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E75DBC77B70 for ; Sat, 8 Apr 2023 21:40:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229540AbjDHVk5 (ORCPT ); Sat, 8 Apr 2023 17:40:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38998 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229531AbjDHVky (ORCPT ); Sat, 8 Apr 2023 17:40:54 -0400 Received: from mail-wr1-x42c.google.com (mail-wr1-x42c.google.com [IPv6:2a00:1450:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1BB4949E3 for ; Sat, 8 Apr 2023 14:40:52 -0700 (PDT) Received: by mail-wr1-x42c.google.com with SMTP id q29so1398689wrc.3 for ; Sat, 08 Apr 2023 14:40:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680990050; x=1683582050; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kRycuVvLu0FkrLWlckqGOADLOPTqKb//lDD/m9QYnxI=; b=eHWiOnWqTiDBxdLm+rSazg5o38dSGAdN9YVcI/rftvX55OiVwRxGrh57YvtIpsX8yE d4NB8kcX+L6F3WEEfmPa5QNyXSvc85cuCune/ssovN++g5tEPH+mHOgtm6zIofFVCyS3 yWSHMylIUvq7F/pG/dgjCw8uDQBhVF/1yQ28p8SUR5L8/Ca4z94PWVy6k2troGMVIslt U6Vr01bhXFArfJbgxFzDznCftfPhPf9QGaZfej9MWwAAaR0+HMmaDcp+vw/IKxb4BO14 MpnjyJG6jQvpDjWAbyDbh+gGEcdJig4KzbqE9ktBev7sgII4/ORphJfW8MWa6y+OHVZE dR5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680990050; x=1683582050; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kRycuVvLu0FkrLWlckqGOADLOPTqKb//lDD/m9QYnxI=; b=4Y/oJ6DnzWrB2ZgvZfjUGj+WV5DkB5wpar/QdEGlEuLQCsBmoX3C6UAhF1dmwvkrng 4Yz7Hbx7s0nq5yykhaCByW7a9k5qiFYDdENR2bD2w5XDDERCtFacJrB/3juKpyJIV7Xr AUlHl4Pn8TnZtNVTpaFb8amW+te0N292NXnoJG+ohDvNNvs3jsYzNXwg6ab/EEOeVTnX rrtLjsKakBO9cE5y+TYBpOaPKadwTOQiwpy4V+g8eL+2QHMCPxZ3GOWfXu2LmKGnjdZb dY71eWp2x+/PbMZY2bzNV6Jx5IEuKK/g0i7CGYyGp3NMwBELwpIFOBBrQbn8PFrZyTZ9 L6zw== X-Gm-Message-State: AAQBX9dd+AFMCnwj3ogyszt5hqfiDon5NePU8GdXNjdi2lbmRdRlWU1E DFKQQ9rpO9k0JnyC8tcfn/8rJg== X-Google-Smtp-Source: AKy350bUr+v4qxTh5qs6y77Qm8ssQS8oooW/CvbF7Ld9zCrimdVIL+WNcg/15Ar1dpyR/AtGkeFaNg== X-Received: by 2002:adf:f446:0:b0:2ce:da65:12d9 with SMTP id f6-20020adff446000000b002ceda6512d9mr4004628wrp.15.1680990050284; Sat, 08 Apr 2023 14:40:50 -0700 (PDT) Received: from localhost.localdomain ([188.25.26.161]) by smtp.gmail.com with ESMTPSA id s6-20020a5d4ec6000000b002efb6e0c495sm3061377wrv.91.2023.04.08.14.40.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 08 Apr 2023 14:40:49 -0700 (PDT) From: Abel Vesa To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Konrad Dybcio , Manivannan Sadhasivam , Alim Akhtar , Avri Altman , Bart Van Assche , Adrian Hunter , "James E . J . Bottomley" , "Martin K . Petersen" , Herbert Xu , "David S . Miller" , Eric Biggers Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, Linux Kernel Mailing List , linux-arm-msm@vger.kernel.org, linux-crypto@vger.kernel.org, linux-scsi@vger.kernel.org Subject: [PATCH v7 2/3] scsi: ufs: ufs-qcom: Switch to the new ICE API Date: Sun, 9 Apr 2023 00:40:40 +0300 Message-Id: <20230408214041.533749-3-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230408214041.533749-1-abel.vesa@linaro.org> References: <20230408214041.533749-1-abel.vesa@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Now that there is a new dedicated ICE driver, drop the ufs-qcom-ice and use the new ICE api provided by the Qualcomm soc driver ice. The platforms that already have ICE support will use the API as library since there will not be a devicetree node, but instead they have reg range. In this case, the of_qcom_ice_get will return an ICE instance created for the consumer's device. But if there are platforms that do not have ice reg in the consumer devicetree node and instead provide a dedicated ICE devicetree node, the of_qcom_ice_get will look up the device based on qcom,ice property and will get the ICE instance registered by the probe function of the ice driver. The ICE clock is now handle by the new driver. This is done by enabling it on the creation of the ICE instance and then enabling/disabling it on UFS runtime resume/suspend. Signed-off-by: Abel Vesa --- The v6 is here: https://lore.kernel.org/all/20230407105029.2274111-5-abel.vesa@linaro.org/ Changes since v6: * none Changes since v5: * Reworded the commit message to add information about what happens with the ICE clock and who handles it. * Added temp ice variable to avoid setting the host ice to any value until a valid one is provided. Changes since v4: * moved the setting of the UFSHCD_CAP_CRYPTO in the ufs_qcom_ice_init Changes since v3: * since ufs-qcom-ice is being dropped, switch back to single file for CONFIG_SCSI_UFS_QCOM * handle properly the not-supported error returned by of_qcom_ice_get * drop cfg->crypto_cap_idx argument from qcom_ice_program_key call * added back the clearing of UFSHCD_CAP_CRYPTO and its checks in resume and enable Changes since v2: * added the suspend API call for ICE * kept old wrappers over ICE API in Changes since v1: * Added a check for supported algorithm and key size and passed the ICE defined values for algorithm and key size * Added call to evict function drivers/ufs/host/Kconfig | 2 +- drivers/ufs/host/Makefile | 4 +- drivers/ufs/host/ufs-qcom-ice.c | 244 -------------------------------- drivers/ufs/host/ufs-qcom.c | 99 ++++++++++++- drivers/ufs/host/ufs-qcom.h | 32 +---- 5 files changed, 104 insertions(+), 277 deletions(-) delete mode 100644 drivers/ufs/host/ufs-qcom-ice.c diff --git a/drivers/ufs/host/Kconfig b/drivers/ufs/host/Kconfig index 8793e3433580..16624ba08050 100644 --- a/drivers/ufs/host/Kconfig +++ b/drivers/ufs/host/Kconfig @@ -59,7 +59,7 @@ config SCSI_UFS_QCOM depends on SCSI_UFSHCD_PLATFORM && ARCH_QCOM depends on GENERIC_MSI_IRQ depends on RESET_CONTROLLER - select QCOM_SCM if SCSI_UFS_CRYPTO + select QCOM_INLINE_CRYPTO_ENGINE if SCSI_UFS_CRYPTO help This selects the QCOM specific additions to UFSHCD platform driver. UFS host on QCOM needs some vendor specific configuration before diff --git a/drivers/ufs/host/Makefile b/drivers/ufs/host/Makefile index d7c5bf7fa512..4573aead02eb 100644 --- a/drivers/ufs/host/Makefile +++ b/drivers/ufs/host/Makefile @@ -3,9 +3,7 @@ obj-$(CONFIG_SCSI_UFS_DWC_TC_PCI) += tc-dwc-g210-pci.o ufshcd-dwc.o tc-dwc-g210.o obj-$(CONFIG_SCSI_UFS_DWC_TC_PLATFORM) += tc-dwc-g210-pltfrm.o ufshcd-dwc.o tc-dwc-g210.o obj-$(CONFIG_SCSI_UFS_CDNS_PLATFORM) += cdns-pltfrm.o -obj-$(CONFIG_SCSI_UFS_QCOM) += ufs_qcom.o -ufs_qcom-y += ufs-qcom.o -ufs_qcom-$(CONFIG_SCSI_UFS_CRYPTO) += ufs-qcom-ice.o +obj-$(CONFIG_SCSI_UFS_QCOM) += ufs-qcom.o obj-$(CONFIG_SCSI_UFS_EXYNOS) += ufs-exynos.o obj-$(CONFIG_SCSI_UFSHCD_PCI) += ufshcd-pci.o obj-$(CONFIG_SCSI_UFSHCD_PLATFORM) += ufshcd-pltfrm.o diff --git a/drivers/ufs/host/ufs-qcom-ice.c b/drivers/ufs/host/ufs-qcom-ice.c deleted file mode 100644 index 453978877ae9..000000000000 --- a/drivers/ufs/host/ufs-qcom-ice.c +++ /dev/null @@ -1,244 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Qualcomm ICE (Inline Crypto Engine) support. - * - * Copyright (c) 2014-2019, The Linux Foundation. All rights reserved. - * Copyright 2019 Google LLC - */ - -#include -#include -#include - -#include "ufs-qcom.h" - -#define AES_256_XTS_KEY_SIZE 64 - -/* QCOM ICE registers */ - -#define QCOM_ICE_REG_CONTROL 0x0000 -#define QCOM_ICE_REG_RESET 0x0004 -#define QCOM_ICE_REG_VERSION 0x0008 -#define QCOM_ICE_REG_FUSE_SETTING 0x0010 -#define QCOM_ICE_REG_PARAMETERS_1 0x0014 -#define QCOM_ICE_REG_PARAMETERS_2 0x0018 -#define QCOM_ICE_REG_PARAMETERS_3 0x001C -#define QCOM_ICE_REG_PARAMETERS_4 0x0020 -#define QCOM_ICE_REG_PARAMETERS_5 0x0024 - -/* QCOM ICE v3.X only */ -#define QCOM_ICE_GENERAL_ERR_STTS 0x0040 -#define QCOM_ICE_INVALID_CCFG_ERR_STTS 0x0030 -#define QCOM_ICE_GENERAL_ERR_MASK 0x0044 - -/* QCOM ICE v2.X only */ -#define QCOM_ICE_REG_NON_SEC_IRQ_STTS 0x0040 -#define QCOM_ICE_REG_NON_SEC_IRQ_MASK 0x0044 - -#define QCOM_ICE_REG_NON_SEC_IRQ_CLR 0x0048 -#define QCOM_ICE_REG_STREAM1_ERROR_SYNDROME1 0x0050 -#define QCOM_ICE_REG_STREAM1_ERROR_SYNDROME2 0x0054 -#define QCOM_ICE_REG_STREAM2_ERROR_SYNDROME1 0x0058 -#define QCOM_ICE_REG_STREAM2_ERROR_SYNDROME2 0x005C -#define QCOM_ICE_REG_STREAM1_BIST_ERROR_VEC 0x0060 -#define QCOM_ICE_REG_STREAM2_BIST_ERROR_VEC 0x0064 -#define QCOM_ICE_REG_STREAM1_BIST_FINISH_VEC 0x0068 -#define QCOM_ICE_REG_STREAM2_BIST_FINISH_VEC 0x006C -#define QCOM_ICE_REG_BIST_STATUS 0x0070 -#define QCOM_ICE_REG_BYPASS_STATUS 0x0074 -#define QCOM_ICE_REG_ADVANCED_CONTROL 0x1000 -#define QCOM_ICE_REG_ENDIAN_SWAP 0x1004 -#define QCOM_ICE_REG_TEST_BUS_CONTROL 0x1010 -#define QCOM_ICE_REG_TEST_BUS_REG 0x1014 - -/* BIST ("built-in self-test"?) status flags */ -#define QCOM_ICE_BIST_STATUS_MASK 0xF0000000 - -#define QCOM_ICE_FUSE_SETTING_MASK 0x1 -#define QCOM_ICE_FORCE_HW_KEY0_SETTING_MASK 0x2 -#define QCOM_ICE_FORCE_HW_KEY1_SETTING_MASK 0x4 - -#define qcom_ice_writel(host, val, reg) \ - writel((val), (host)->ice_mmio + (reg)) -#define qcom_ice_readl(host, reg) \ - readl((host)->ice_mmio + (reg)) - -static bool qcom_ice_supported(struct ufs_qcom_host *host) -{ - struct device *dev = host->hba->dev; - u32 regval = qcom_ice_readl(host, QCOM_ICE_REG_VERSION); - int major = regval >> 24; - int minor = (regval >> 16) & 0xFF; - int step = regval & 0xFFFF; - - /* For now this driver only supports ICE version 3. */ - if (major != 3) { - dev_warn(dev, "Unsupported ICE version: v%d.%d.%d\n", - major, minor, step); - return false; - } - - dev_info(dev, "Found QC Inline Crypto Engine (ICE) v%d.%d.%d\n", - major, minor, step); - - /* If fuses are blown, ICE might not work in the standard way. */ - regval = qcom_ice_readl(host, QCOM_ICE_REG_FUSE_SETTING); - if (regval & (QCOM_ICE_FUSE_SETTING_MASK | - QCOM_ICE_FORCE_HW_KEY0_SETTING_MASK | - QCOM_ICE_FORCE_HW_KEY1_SETTING_MASK)) { - dev_warn(dev, "Fuses are blown; ICE is unusable!\n"); - return false; - } - return true; -} - -int ufs_qcom_ice_init(struct ufs_qcom_host *host) -{ - struct ufs_hba *hba = host->hba; - struct device *dev = hba->dev; - struct platform_device *pdev = to_platform_device(dev); - struct resource *res; - int err; - - if (!(ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES) & - MASK_CRYPTO_SUPPORT)) - return 0; - - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ice"); - if (!res) { - dev_warn(dev, "ICE registers not found\n"); - goto disable; - } - - if (!qcom_scm_ice_available()) { - dev_warn(dev, "ICE SCM interface not found\n"); - goto disable; - } - - host->ice_mmio = devm_ioremap_resource(dev, res); - if (IS_ERR(host->ice_mmio)) { - err = PTR_ERR(host->ice_mmio); - return err; - } - - if (!qcom_ice_supported(host)) - goto disable; - - return 0; - -disable: - dev_warn(dev, "Disabling inline encryption support\n"); - hba->caps &= ~UFSHCD_CAP_CRYPTO; - return 0; -} - -static void qcom_ice_low_power_mode_enable(struct ufs_qcom_host *host) -{ - u32 regval; - - regval = qcom_ice_readl(host, QCOM_ICE_REG_ADVANCED_CONTROL); - /* - * Enable low power mode sequence - * [0]-0, [1]-0, [2]-0, [3]-E, [4]-0, [5]-0, [6]-0, [7]-0 - */ - regval |= 0x7000; - qcom_ice_writel(host, regval, QCOM_ICE_REG_ADVANCED_CONTROL); -} - -static void qcom_ice_optimization_enable(struct ufs_qcom_host *host) -{ - u32 regval; - - /* ICE Optimizations Enable Sequence */ - regval = qcom_ice_readl(host, QCOM_ICE_REG_ADVANCED_CONTROL); - regval |= 0xD807100; - /* ICE HPG requires delay before writing */ - udelay(5); - qcom_ice_writel(host, regval, QCOM_ICE_REG_ADVANCED_CONTROL); - udelay(5); -} - -int ufs_qcom_ice_enable(struct ufs_qcom_host *host) -{ - if (!(host->hba->caps & UFSHCD_CAP_CRYPTO)) - return 0; - qcom_ice_low_power_mode_enable(host); - qcom_ice_optimization_enable(host); - return ufs_qcom_ice_resume(host); -} - -/* Poll until all BIST bits are reset */ -static int qcom_ice_wait_bist_status(struct ufs_qcom_host *host) -{ - int count; - u32 reg; - - for (count = 0; count < 100; count++) { - reg = qcom_ice_readl(host, QCOM_ICE_REG_BIST_STATUS); - if (!(reg & QCOM_ICE_BIST_STATUS_MASK)) - break; - udelay(50); - } - if (reg) - return -ETIMEDOUT; - return 0; -} - -int ufs_qcom_ice_resume(struct ufs_qcom_host *host) -{ - int err; - - if (!(host->hba->caps & UFSHCD_CAP_CRYPTO)) - return 0; - - err = qcom_ice_wait_bist_status(host); - if (err) { - dev_err(host->hba->dev, "BIST status error (%d)\n", err); - return err; - } - return 0; -} - -/* - * Program a key into a QC ICE keyslot, or evict a keyslot. QC ICE requires - * vendor-specific SCM calls for this; it doesn't support the standard way. - */ -int ufs_qcom_ice_program_key(struct ufs_hba *hba, - const union ufs_crypto_cfg_entry *cfg, int slot) -{ - union ufs_crypto_cap_entry cap; - union { - u8 bytes[AES_256_XTS_KEY_SIZE]; - u32 words[AES_256_XTS_KEY_SIZE / sizeof(u32)]; - } key; - int i; - int err; - - if (!(cfg->config_enable & UFS_CRYPTO_CONFIGURATION_ENABLE)) - return qcom_scm_ice_invalidate_key(slot); - - /* Only AES-256-XTS has been tested so far. */ - cap = hba->crypto_cap_array[cfg->crypto_cap_idx]; - if (cap.algorithm_id != UFS_CRYPTO_ALG_AES_XTS || - cap.key_size != UFS_CRYPTO_KEY_SIZE_256) { - dev_err_ratelimited(hba->dev, - "Unhandled crypto capability; algorithm_id=%d, key_size=%d\n", - cap.algorithm_id, cap.key_size); - return -EINVAL; - } - - memcpy(key.bytes, cfg->crypto_key, AES_256_XTS_KEY_SIZE); - - /* - * The SCM call byte-swaps the 32-bit words of the key. So we have to - * do the same, in order for the final key be correct. - */ - for (i = 0; i < ARRAY_SIZE(key.words); i++) - __cpu_to_be32s(&key.words[i]); - - err = qcom_scm_ice_set_key(slot, key.bytes, AES_256_XTS_KEY_SIZE, - QCOM_SCM_ICE_CIPHER_AES_256_XTS, - cfg->data_unit_size); - memzero_explicit(&key, sizeof(key)); - return err; -} diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index 82d02e7f3b4f..e3c2b5c868c7 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -15,6 +15,8 @@ #include #include +#include + #include #include "ufshcd-pltfrm.h" #include @@ -55,6 +57,100 @@ static struct ufs_qcom_host *rcdev_to_ufs_host(struct reset_controller_dev *rcd) return container_of(rcd, struct ufs_qcom_host, rcdev); } +#ifdef CONFIG_SCSI_UFS_CRYPTO + +static inline void ufs_qcom_ice_enable(struct ufs_qcom_host *host) +{ + if (host->hba->caps & UFSHCD_CAP_CRYPTO) + qcom_ice_enable(host->ice); +} + +static int ufs_qcom_ice_init(struct ufs_qcom_host *host) +{ + struct ufs_hba *hba = host->hba; + struct device *dev = hba->dev; + struct qcom_ice *ice; + + ice = of_qcom_ice_get(dev); + if (ice == ERR_PTR(-EOPNOTSUPP)) { + dev_warn(dev, "Disabling inline encryption support\n"); + ice = NULL; + } + + if (IS_ERR_OR_NULL(ice)) + return PTR_ERR_OR_ZERO(ice); + + host->ice = ice; + hba->caps |= UFSHCD_CAP_CRYPTO; + + return 0; +} + +static inline int ufs_qcom_ice_resume(struct ufs_qcom_host *host) +{ + if (host->hba->caps & UFSHCD_CAP_CRYPTO) + return qcom_ice_resume(host->ice); + + return 0; +} + +static inline int ufs_qcom_ice_suspend(struct ufs_qcom_host *host) +{ + if (host->hba->caps & UFSHCD_CAP_CRYPTO) + return qcom_ice_suspend(host->ice); + + return 0; +} + +static int ufs_qcom_ice_program_key(struct ufs_hba *hba, + const union ufs_crypto_cfg_entry *cfg, + int slot) +{ + struct ufs_qcom_host *host = ufshcd_get_variant(hba); + union ufs_crypto_cap_entry cap; + bool config_enable = + cfg->config_enable & UFS_CRYPTO_CONFIGURATION_ENABLE; + + /* Only AES-256-XTS has been tested so far. */ + cap = hba->crypto_cap_array[cfg->crypto_cap_idx]; + if (cap.algorithm_id != UFS_CRYPTO_ALG_AES_XTS || + cap.key_size != UFS_CRYPTO_KEY_SIZE_256) + return -EINVAL; + + if (config_enable) + return qcom_ice_program_key(host->ice, + QCOM_ICE_CRYPTO_ALG_AES_XTS, + QCOM_ICE_CRYPTO_KEY_SIZE_256, + cfg->crypto_key, + cfg->data_unit_size, slot); + else + return qcom_ice_evict_key(host->ice, slot); +} + +#else + +#define ufs_qcom_ice_program_key NULL + +static inline void ufs_qcom_ice_enable(struct ufs_qcom_host *host) +{ +} + +static int ufs_qcom_ice_init(struct ufs_qcom_host *host) +{ + return 0; +} + +static inline int ufs_qcom_ice_resume(struct ufs_qcom_host *host) +{ + return 0; +} + +static inline int ufs_qcom_ice_suspend(struct ufs_qcom_host *host) +{ + return 0; +} +#endif + static int ufs_qcom_host_clk_get(struct device *dev, const char *name, struct clk **clk_out, bool optional) { @@ -607,7 +703,7 @@ static int ufs_qcom_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op, ufs_qcom_disable_lane_clks(host); } - return 0; + return ufs_qcom_ice_suspend(host); } static int ufs_qcom_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op) @@ -853,7 +949,6 @@ static void ufs_qcom_set_caps(struct ufs_hba *hba) hba->caps |= UFSHCD_CAP_CLK_SCALING | UFSHCD_CAP_WB_WITH_CLK_SCALING; hba->caps |= UFSHCD_CAP_AUTO_BKOPS_SUSPEND; hba->caps |= UFSHCD_CAP_WB_EN; - hba->caps |= UFSHCD_CAP_CRYPTO; hba->caps |= UFSHCD_CAP_AGGR_POWER_COLLAPSE; hba->caps |= UFSHCD_CAP_RPM_AUTOSUSPEND; diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h index 39e774254fb2..6289ad5a42d0 100644 --- a/drivers/ufs/host/ufs-qcom.h +++ b/drivers/ufs/host/ufs-qcom.h @@ -7,6 +7,7 @@ #include #include +#include #include #define MAX_UFS_QCOM_HOSTS 1 @@ -205,12 +206,13 @@ struct ufs_qcom_host { struct clk *tx_l1_sync_clk; bool is_lane_clks_enabled; +#ifdef CONFIG_SCSI_UFS_CRYPTO + struct qcom_ice *ice; +#endif + void __iomem *dev_ref_clk_ctrl_mmio; bool is_dev_ref_clk_enabled; struct ufs_hw_version hw_ver; -#ifdef CONFIG_SCSI_UFS_CRYPTO - void __iomem *ice_mmio; -#endif u32 dev_ref_clk_en_mask; @@ -248,28 +250,4 @@ static inline bool ufs_qcom_cap_qunipro(struct ufs_qcom_host *host) return host->caps & UFS_QCOM_CAP_QUNIPRO; } -/* ufs-qcom-ice.c */ - -#ifdef CONFIG_SCSI_UFS_CRYPTO -int ufs_qcom_ice_init(struct ufs_qcom_host *host); -int ufs_qcom_ice_enable(struct ufs_qcom_host *host); -int ufs_qcom_ice_resume(struct ufs_qcom_host *host); -int ufs_qcom_ice_program_key(struct ufs_hba *hba, - const union ufs_crypto_cfg_entry *cfg, int slot); -#else -static inline int ufs_qcom_ice_init(struct ufs_qcom_host *host) -{ - return 0; -} -static inline int ufs_qcom_ice_enable(struct ufs_qcom_host *host) -{ - return 0; -} -static inline int ufs_qcom_ice_resume(struct ufs_qcom_host *host) -{ - return 0; -} -#define ufs_qcom_ice_program_key NULL -#endif /* !CONFIG_SCSI_UFS_CRYPTO */ - #endif /* UFS_QCOM_H_ */ From patchwork Sat Apr 8 21:40:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 671677 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C105DC77B6C for ; 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Sat, 08 Apr 2023 14:40:51 -0700 (PDT) From: Abel Vesa To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Konrad Dybcio , Manivannan Sadhasivam , Alim Akhtar , Avri Altman , Bart Van Assche , Adrian Hunter , "James E . J . Bottomley" , "Martin K . Petersen" , Herbert Xu , "David S . Miller" , Eric Biggers Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, Linux Kernel Mailing List , linux-arm-msm@vger.kernel.org, linux-crypto@vger.kernel.org, linux-scsi@vger.kernel.org Subject: [PATCH v7 3/3] mmc: sdhci-msm: Switch to the new ICE API Date: Sun, 9 Apr 2023 00:40:41 +0300 Message-Id: <20230408214041.533749-4-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230408214041.533749-1-abel.vesa@linaro.org> References: <20230408214041.533749-1-abel.vesa@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Now that there is a new dedicated ICE driver, drop the sdhci-msm ICE implementation and use the new ICE api provided by the Qualcomm soc driver ice. The platforms that already have ICE support will use the API as library since there will not be a devicetree node, but instead they have reg range. In this case, the of_qcom_ice_get will return an ICE instance created for the consumer's device. But if there are platforms that do not have ice reg in the consumer devicetree node and instead provide a dedicated ICE devicetree node, theof_qcom_ice_get will look up the device based on qcom,ice property and will get the ICE instance registered by the probe function of the ice driver. The ICE clock is now handle by the new driver. This is done by enabling it on the creation of the ICE instance and then enabling/disabling it on SDCC runtime resume/suspend. Signed-off-by: Abel Vesa Acked-by: Adrian Hunter Acked-by: Ulf Hansson --- The v6 is here: https://lore.kernel.org/all/20230407105029.2274111-6-abel.vesa@linaro.org/ Changes since v6: * none Changes since v5: * Reworded the commit message to add information about what happens with the ICE clock and who handles it. * Added temp ice variable to avoid setting the host ice to any value until a valid one is provided. * Dropped the qcom_scm.h include as it is not used anymore now that we moved that to the new ICE driver Changes since v4: * none Changes since v3: * added back the checks for and the setting of MMC_CAP2_CRYPTO * added enable/resume/suspend implementation for !CONFIG_MMC_CRYPTO * dropped cfg->crypto_cap_idx argument from qcom_ice_program_key Changes since v2: * added the suspend API call for ICE * kept old wrappers over ICE API in Changes since v1: * Added a check for supported algorithm and key size and passed the ICE defined values for algorithm and key size * Added call to evict function drivers/mmc/host/Kconfig | 2 +- drivers/mmc/host/sdhci-msm.c | 223 ++++++++--------------------------- 2 files changed, 48 insertions(+), 177 deletions(-) diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index 4745fe217ade..09f837df5435 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -549,7 +549,7 @@ config MMC_SDHCI_MSM depends on MMC_SDHCI_PLTFM select MMC_SDHCI_IO_ACCESSORS select MMC_CQHCI - select QCOM_SCM if MMC_CRYPTO + select QCOM_INLINE_CRYPTO_ENGINE if MMC_CRYPTO help This selects the Secure Digital Host Controller Interface (SDHCI) support present in Qualcomm SOCs. The controller supports diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index 8ac81d57a3df..98171bf5748c 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -13,12 +13,13 @@ #include #include #include -#include #include #include #include #include +#include + #include "sdhci-cqhci.h" #include "sdhci-pltfm.h" #include "cqhci.h" @@ -258,12 +259,14 @@ struct sdhci_msm_variant_info { struct sdhci_msm_host { struct platform_device *pdev; void __iomem *core_mem; /* MSM SDCC mapped address */ - void __iomem *ice_mem; /* MSM ICE mapped address (if available) */ int pwr_irq; /* power irq */ struct clk *bus_clk; /* SDHC bus voter clock */ struct clk *xo_clk; /* TCXO clk needed for FLL feature of cm_dll*/ - /* core, iface, cal, sleep, and ice clocks */ - struct clk_bulk_data bulk_clks[5]; + /* core, iface, cal and sleep clocks */ + struct clk_bulk_data bulk_clks[4]; +#ifdef CONFIG_MMC_CRYPTO + struct qcom_ice *ice; +#endif unsigned long clk_rate; struct mmc_host *mmc; bool use_14lpp_dll_reset; @@ -1804,164 +1807,51 @@ static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock) #ifdef CONFIG_MMC_CRYPTO -#define AES_256_XTS_KEY_SIZE 64 - -/* QCOM ICE registers */ - -#define QCOM_ICE_REG_VERSION 0x0008 - -#define QCOM_ICE_REG_FUSE_SETTING 0x0010 -#define QCOM_ICE_FUSE_SETTING_MASK 0x1 -#define QCOM_ICE_FORCE_HW_KEY0_SETTING_MASK 0x2 -#define QCOM_ICE_FORCE_HW_KEY1_SETTING_MASK 0x4 - -#define QCOM_ICE_REG_BIST_STATUS 0x0070 -#define QCOM_ICE_BIST_STATUS_MASK 0xF0000000 - -#define QCOM_ICE_REG_ADVANCED_CONTROL 0x1000 - -#define sdhci_msm_ice_writel(host, val, reg) \ - writel((val), (host)->ice_mem + (reg)) -#define sdhci_msm_ice_readl(host, reg) \ - readl((host)->ice_mem + (reg)) - -static bool sdhci_msm_ice_supported(struct sdhci_msm_host *msm_host) -{ - struct device *dev = mmc_dev(msm_host->mmc); - u32 regval = sdhci_msm_ice_readl(msm_host, QCOM_ICE_REG_VERSION); - int major = regval >> 24; - int minor = (regval >> 16) & 0xFF; - int step = regval & 0xFFFF; - - /* For now this driver only supports ICE version 3. */ - if (major != 3) { - dev_warn(dev, "Unsupported ICE version: v%d.%d.%d\n", - major, minor, step); - return false; - } - - dev_info(dev, "Found QC Inline Crypto Engine (ICE) v%d.%d.%d\n", - major, minor, step); - - /* If fuses are blown, ICE might not work in the standard way. */ - regval = sdhci_msm_ice_readl(msm_host, QCOM_ICE_REG_FUSE_SETTING); - if (regval & (QCOM_ICE_FUSE_SETTING_MASK | - QCOM_ICE_FORCE_HW_KEY0_SETTING_MASK | - QCOM_ICE_FORCE_HW_KEY1_SETTING_MASK)) { - dev_warn(dev, "Fuses are blown; ICE is unusable!\n"); - return false; - } - return true; -} - -static inline struct clk *sdhci_msm_ice_get_clk(struct device *dev) -{ - return devm_clk_get(dev, "ice"); -} - static int sdhci_msm_ice_init(struct sdhci_msm_host *msm_host, struct cqhci_host *cq_host) { struct mmc_host *mmc = msm_host->mmc; struct device *dev = mmc_dev(mmc); - struct resource *res; + struct qcom_ice *ice; if (!(cqhci_readl(cq_host, CQHCI_CAP) & CQHCI_CAP_CS)) return 0; - res = platform_get_resource_byname(msm_host->pdev, IORESOURCE_MEM, - "ice"); - if (!res) { - dev_warn(dev, "ICE registers not found\n"); - goto disable; - } - - if (!qcom_scm_ice_available()) { - dev_warn(dev, "ICE SCM interface not found\n"); - goto disable; + ice = of_qcom_ice_get(dev); + if (ice == ERR_PTR(-EOPNOTSUPP)) { + dev_warn(dev, "Disabling inline encryption support\n"); + ice = NULL; } - msm_host->ice_mem = devm_ioremap_resource(dev, res); - if (IS_ERR(msm_host->ice_mem)) - return PTR_ERR(msm_host->ice_mem); - - if (!sdhci_msm_ice_supported(msm_host)) - goto disable; + if (IS_ERR_OR_NULL(ice)) + return PTR_ERR_OR_ZERO(ice); + msm_host->ice = ice; mmc->caps2 |= MMC_CAP2_CRYPTO; - return 0; -disable: - dev_warn(dev, "Disabling inline encryption support\n"); return 0; } -static void sdhci_msm_ice_low_power_mode_enable(struct sdhci_msm_host *msm_host) -{ - u32 regval; - - regval = sdhci_msm_ice_readl(msm_host, QCOM_ICE_REG_ADVANCED_CONTROL); - /* - * Enable low power mode sequence - * [0]-0, [1]-0, [2]-0, [3]-E, [4]-0, [5]-0, [6]-0, [7]-0 - */ - regval |= 0x7000; - sdhci_msm_ice_writel(msm_host, regval, QCOM_ICE_REG_ADVANCED_CONTROL); -} - -static void sdhci_msm_ice_optimization_enable(struct sdhci_msm_host *msm_host) +static void sdhci_msm_ice_enable(struct sdhci_msm_host *msm_host) { - u32 regval; - - /* ICE Optimizations Enable Sequence */ - regval = sdhci_msm_ice_readl(msm_host, QCOM_ICE_REG_ADVANCED_CONTROL); - regval |= 0xD807100; - /* ICE HPG requires delay before writing */ - udelay(5); - sdhci_msm_ice_writel(msm_host, regval, QCOM_ICE_REG_ADVANCED_CONTROL); - udelay(5); + if (msm_host->mmc->caps2 & MMC_CAP2_CRYPTO) + qcom_ice_enable(msm_host->ice); } -/* - * Wait until the ICE BIST (built-in self-test) has completed. - * - * This may be necessary before ICE can be used. - * - * Note that we don't really care whether the BIST passed or failed; we really - * just want to make sure that it isn't still running. This is because (a) the - * BIST is a FIPS compliance thing that never fails in practice, (b) ICE is - * documented to reject crypto requests if the BIST fails, so we needn't do it - * in software too, and (c) properly testing storage encryption requires testing - * the full storage stack anyway, and not relying on hardware-level self-tests. - */ -static int sdhci_msm_ice_wait_bist_status(struct sdhci_msm_host *msm_host) +static __maybe_unused int sdhci_msm_ice_resume(struct sdhci_msm_host *msm_host) { - u32 regval; - int err; + if (msm_host->mmc->caps2 & MMC_CAP2_CRYPTO) + return qcom_ice_resume(msm_host->ice); - err = readl_poll_timeout(msm_host->ice_mem + QCOM_ICE_REG_BIST_STATUS, - regval, !(regval & QCOM_ICE_BIST_STATUS_MASK), - 50, 5000); - if (err) - dev_err(mmc_dev(msm_host->mmc), - "Timed out waiting for ICE self-test to complete\n"); - return err; + return 0; } -static void sdhci_msm_ice_enable(struct sdhci_msm_host *msm_host) +static __maybe_unused int sdhci_msm_ice_suspend(struct sdhci_msm_host *msm_host) { - if (!(msm_host->mmc->caps2 & MMC_CAP2_CRYPTO)) - return; - sdhci_msm_ice_low_power_mode_enable(msm_host); - sdhci_msm_ice_optimization_enable(msm_host); - sdhci_msm_ice_wait_bist_status(msm_host); -} + if (msm_host->mmc->caps2 & MMC_CAP2_CRYPTO) + return qcom_ice_suspend(msm_host->ice); -static int __maybe_unused sdhci_msm_ice_resume(struct sdhci_msm_host *msm_host) -{ - if (!(msm_host->mmc->caps2 & MMC_CAP2_CRYPTO)) - return 0; - return sdhci_msm_ice_wait_bist_status(msm_host); + return 0; } /* @@ -1972,48 +1862,28 @@ static int sdhci_msm_program_key(struct cqhci_host *cq_host, const union cqhci_crypto_cfg_entry *cfg, int slot) { - struct device *dev = mmc_dev(cq_host->mmc); + struct sdhci_host *host = mmc_priv(cq_host->mmc); + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); union cqhci_crypto_cap_entry cap; - union { - u8 bytes[AES_256_XTS_KEY_SIZE]; - u32 words[AES_256_XTS_KEY_SIZE / sizeof(u32)]; - } key; - int i; - int err; - - if (!(cfg->config_enable & CQHCI_CRYPTO_CONFIGURATION_ENABLE)) - return qcom_scm_ice_invalidate_key(slot); /* Only AES-256-XTS has been tested so far. */ cap = cq_host->crypto_cap_array[cfg->crypto_cap_idx]; if (cap.algorithm_id != CQHCI_CRYPTO_ALG_AES_XTS || - cap.key_size != CQHCI_CRYPTO_KEY_SIZE_256) { - dev_err_ratelimited(dev, - "Unhandled crypto capability; algorithm_id=%d, key_size=%d\n", - cap.algorithm_id, cap.key_size); + cap.key_size != CQHCI_CRYPTO_KEY_SIZE_256) return -EINVAL; - } - memcpy(key.bytes, cfg->crypto_key, AES_256_XTS_KEY_SIZE); - - /* - * The SCM call byte-swaps the 32-bit words of the key. So we have to - * do the same, in order for the final key be correct. - */ - for (i = 0; i < ARRAY_SIZE(key.words); i++) - __cpu_to_be32s(&key.words[i]); - - err = qcom_scm_ice_set_key(slot, key.bytes, AES_256_XTS_KEY_SIZE, - QCOM_SCM_ICE_CIPHER_AES_256_XTS, - cfg->data_unit_size); - memzero_explicit(&key, sizeof(key)); - return err; + if (cfg->config_enable & CQHCI_CRYPTO_CONFIGURATION_ENABLE) + return qcom_ice_program_key(msm_host->ice, + QCOM_ICE_CRYPTO_ALG_AES_XTS, + QCOM_ICE_CRYPTO_KEY_SIZE_256, + cfg->crypto_key, + cfg->data_unit_size, slot); + else + return qcom_ice_evict_key(msm_host->ice, slot); } + #else /* CONFIG_MMC_CRYPTO */ -static inline struct clk *sdhci_msm_ice_get_clk(struct device *dev) -{ - return NULL; -} static inline int sdhci_msm_ice_init(struct sdhci_msm_host *msm_host, struct cqhci_host *cq_host) @@ -2025,11 +1895,17 @@ static inline void sdhci_msm_ice_enable(struct sdhci_msm_host *msm_host) { } -static inline int __maybe_unused +static inline __maybe_unused int sdhci_msm_ice_resume(struct sdhci_msm_host *msm_host) { return 0; } + +static inline __maybe_unused int +sdhci_msm_ice_suspend(struct sdhci_msm_host *msm_host) +{ + return 0; +} #endif /* !CONFIG_MMC_CRYPTO */ /*****************************************************************************\ @@ -2630,11 +2506,6 @@ static int sdhci_msm_probe(struct platform_device *pdev) clk = NULL; msm_host->bulk_clks[3].clk = clk; - clk = sdhci_msm_ice_get_clk(&pdev->dev); - if (IS_ERR(clk)) - clk = NULL; - msm_host->bulk_clks[4].clk = clk; - ret = clk_bulk_prepare_enable(ARRAY_SIZE(msm_host->bulk_clks), msm_host->bulk_clks); if (ret) @@ -2827,7 +2698,7 @@ static __maybe_unused int sdhci_msm_runtime_suspend(struct device *dev) clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks), msm_host->bulk_clks); - return 0; + return sdhci_msm_ice_suspend(msm_host); } static __maybe_unused int sdhci_msm_runtime_resume(struct device *dev)