From patchwork Sun May 26 01:09:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 165185 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp5434409ili; Sat, 25 May 2019 18:35:23 -0700 (PDT) X-Google-Smtp-Source: APXvYqwOQm9kQf7avLMRtMy6IEEPabiTZp5432xQmKQ8vooRXHZZ0aBKpaHrHfrioOj3AltrsRwx X-Received: by 2002:ab0:13ef:: with SMTP id n44mr9731149uae.4.1558834523174; Sat, 25 May 2019 18:35:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1558834523; cv=none; d=google.com; s=arc-20160816; b=BgovfeVtjFAdM+rEhlL7VwbWYuxXNp8cekRi8tK4m6aCDcwqmx+YkueuCuxgD4Rc5i NJZ3wXMlr9a+BSaY1HewK0iUJQCyj8t2fl3ay+/UefsUVUGlbZ0EKA/x/bLzALaOk5im rP0rLxjnMuNYkBeGzc3ZLK5hXo4ufsdznk7rNo7i9MOMRj82o3t3uK6GWzXJRpo6xwbb F2HdrgMwefQ3cX7FEnuyzdlCuTdu6DM3rj6QkT6E1DSDzEl63at5a9+T73/D/17piUsO yDN5hD93aUaq/CuuiLAPUfAb53cTZc8fkRfCYwtCVE/EjQG8MguBzE8QoIhxtYTx0r7j ZzvA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:to:from :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date; bh=AGynrsN21pUOx1n9WYF4sVDzoqOhDbKXNfRUTxBfjrw=; b=GMsyb0vuVTJubT5QSfDePQRVadNkSvStJv5N/juY4qoO66AvdWY0flKVCGf/erxCTq DVsDLsLP30T2SatVVZvH8DMC4s4difEGX24btJ50T4QUI1no3wWJuzvWR9tEfCoh2/c6 SP815S25SiYMAnaLKPXetdMoWWSGb2yC9Vi/W8qcAtccAhZJCPrpNwAYGLz1nevPxX+v UJeJi6LJQgu/zy1HpIJydoAmzGnu0vjRshSRcq+CSJNi2R4YoHd4s+yHqUXVw1tgYCCf cwIc6axaqHGcQOumCuJocqkpstZ0dGApe1om5RrQWw14GjuTyuttBquSpIKuxN9IWcUx 3c3w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Sat, 25 May 2019 18:10:05 -0700 (PDT) Received: from localhost ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id e123sm6733854pgc.29.2019.05.25.18.10.04 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 25 May 2019 18:10:05 -0700 (PDT) Date: Sat, 25 May 2019 18:09:23 -0700 Message-Id: <20190526010948.3923-5-palmer@sifive.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190526010948.3923-1-palmer@sifive.com> References: <20190526010948.3923-1-palmer@sifive.com> MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.210.193 Subject: [Qemu-devel] [PULL 04/29] target/riscv: Name the argument sets for all of insn32 formats X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , Palmer Dabbelt , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Signed-off-by: Richard Henderson Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- target/riscv/insn32.decode | 10 +++++++--- target/riscv/translate.c | 18 ++++++++++++++++++ 2 files changed, 25 insertions(+), 3 deletions(-) -- 2.21.0 diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 6f3ab7aa52d3..77f794ed703d 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -34,9 +34,13 @@ %imm_u 12:s20 !function=ex_shift_12 # Argument sets: +&empty &b imm rs2 rs1 &i imm rs1 rd +&j imm rd &r rd rs1 rs2 +&s imm rs1 rs2 +&u imm rd &shift shamt rs1 rd &atomic aq rl rs2 rs1 rd @@ -44,9 +48,9 @@ @r ....... ..... ..... ... ..... ....... &r %rs2 %rs1 %rd @i ............ ..... ... ..... ....... &i imm=%imm_i %rs1 %rd @b ....... ..... ..... ... ..... ....... &b imm=%imm_b %rs2 %rs1 -@s ....... ..... ..... ... ..... ....... imm=%imm_s %rs2 %rs1 -@u .................... ..... ....... imm=%imm_u %rd -@j .................... ..... ....... imm=%imm_j %rd +@s ....... ..... ..... ... ..... ....... &s imm=%imm_s %rs2 %rs1 +@u .................... ..... ....... &u imm=%imm_u %rd +@j .................... ..... ....... &j imm=%imm_j %rd @sh ...... ...... ..... ... ..... ....... &shift shamt=%sh10 %rs1 %rd @csr ............ ..... ... ..... ....... %csr %rs1 %rd diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 840ecbef36e7..928374242e83 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -687,11 +687,29 @@ static bool gen_shift(DisasContext *ctx, arg_r *a, #include "insn_trans/trans_rvd.inc.c" #include "insn_trans/trans_privileged.inc.c" +/* + * Auto-generated decoder. + * Note that the 16-bit decoder reuses some of the trans_* functions + * initially declared by the 32-bit decoder, which results in duplicate + * declaration warnings. Suppress them. + */ +#ifdef CONFIG_PRAGMA_DIAGNOSTIC_AVAILABLE +# pragma GCC diagnostic push +# pragma GCC diagnostic ignored "-Wredundant-decls" +# ifdef __clang__ +# pragma GCC diagnostic ignored "-Wtypedef-redefinition" +# endif +#endif + bool decode_insn16(DisasContext *ctx, uint16_t insn); /* auto-generated decoder*/ #include "decode_insn16.inc.c" #include "insn_trans/trans_rvc.inc.c" +#ifdef CONFIG_PRAGMA_DIAGNOSTIC_AVAILABLE +# pragma GCC diagnostic pop +#endif + static void decode_opc(DisasContext *ctx) { /* check for compressed insn */ From patchwork Sun May 26 01:09:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 165191 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp5443926ili; Sat, 25 May 2019 18:51:28 -0700 (PDT) X-Google-Smtp-Source: APXvYqxmz19xRojxwH+yEnVHWjVFJc34NVFrOZTQ5GNShVftWp+9XJwYFPf9oHT1Vy3avGK4qUh9 X-Received: by 2002:a1f:a097:: with SMTP id j145mr13320352vke.18.1558835487948; Sat, 25 May 2019 18:51:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1558835487; cv=none; d=google.com; s=arc-20160816; b=lJQ4QEKUVxXKDim6t/dEP/+Arb4dLYHX3C3N1JZk6fa327r92KY3hnsj66YrRk7JRb OmlblDUTQWX1vj42zIM+rfrYBr9A8z+x6rOc0gKzIc8etH3QAA3v8Xca+Qg8a5eR/UcZ PByQlKWRJpRJku4UxznswPaWRpvGKOb4G6u/vACxqtIcV9SvKSd1HHXTLs3qMsQVo1rB mfV32gKjoLhPZMbpErbE8uwGIWV5Emv6rzyW/p1TQ8ZyYJRYG3RgegxRRAiYvRc1hrAx cfir6lBlQF/vdfiV06xi9ncMi8waFab7r7dD5s+F8UD5VDfWhfXyMJG/Xf3cOAugksc4 0JjA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:to:from :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date; bh=OmquU5pLX4FdtJeBi0sZUSl7FBDLh8w+FhsdYMBvZRk=; b=0Cf+SmjKkY8VoBBN3e/m/VgfwM4OImm5nVPTsVSYajwswJGX8tLU/34r0gPzaqAdZO lxBBFQhmPlvB1O7mFd1Aen2tKyBm+/MedJYcO9y+iMA7GsIZOxwylqByEtF0L608DHeY RBOnShyVMnaDtQvhnXFm5947cwM+aOhQXzbt3tv4DpRUvZIL4skg98H4stY3N9pLQcbo 4D0Bqw+rDl2xKPb9ntddVjU22aIHhoaBuGGkXnt66fkHivcbE6TEHdNw9q+veJzmlbhv uEAXkkgB4f8lWmXwj9n2ZSdn/u7FT9PkX3pbIOIpFkSJ7bulpKdVTouPw+9w0ZdKgZDX Vs9g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id l20si2338665vsj.187.2019.05.25.18.51.27 for (version=TLS1 cipher=AES128-SHA bits=128/128); Sat, 25 May 2019 18:51:27 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([127.0.0.1]:49497 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hUiJr-0006iB-Gy for patch@linaro.org; Sat, 25 May 2019 21:51:27 -0400 Received: from eggs.gnu.org ([209.51.188.92]:53897) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hUhxP-0003HK-PV for qemu-devel@nongnu.org; Sat, 25 May 2019 21:28:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hUhfs-0005o7-HA for qemu-devel@nongnu.org; Sat, 25 May 2019 21:10:09 -0400 Received: from mail-pg1-f196.google.com ([209.85.215.196]:39486) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hUhfs-0005nj-Ab for qemu-devel@nongnu.org; Sat, 25 May 2019 21:10:08 -0400 Received: by mail-pg1-f196.google.com with SMTP id w22so7086073pgi.6 for ; Sat, 25 May 2019 18:10:08 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:cc:from:to; bh=OmquU5pLX4FdtJeBi0sZUSl7FBDLh8w+FhsdYMBvZRk=; b=LtoZgn4O9WBk7B/uvmTB+HfsxMb30Mz+qE78HE1gvNeuBfhLBPZnCKyIZMSGdLUA/5 BNlEkYt7wZEvHs3TQ1y9dn2rb2VKySqRNtdMHOO/84TXV8Enr546rKRFFbsXWxKtsSn8 LGxPJNnnOCPqcFDBLHOh05s99Z/h9EXWjnHywCDNGhkAhni25wxy43zjznqXQ9wTCPsM BYMD4pN0eVWK3AkRUTd5XwgpjIhjqtJuhcUiNzJgbRTCbhztRQuyCFK8lWAqD5rGI0qF ZGKz+FyZ2f2nkyaO2A4FAOJnNV5ITiBhhVYFkaHpnuyEtwIUrbWFcxNDxfzjJxbTHHBy en8w== X-Gm-Message-State: APjAAAWaiXSdQYZ1bgfwWWgauwSewquCi/YS9etdZorfIHoqAKoJTnm1 dOYfJAbFoA8xWjcK4nFnt0e3Ng== X-Received: by 2002:a17:90a:de0e:: with SMTP id m14mr20184255pjv.36.1558833007034; Sat, 25 May 2019 18:10:07 -0700 (PDT) Received: from localhost ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id n2sm6014719pgp.27.2019.05.25.18.10.06 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 25 May 2019 18:10:06 -0700 (PDT) Date: Sat, 25 May 2019 18:09:24 -0700 Message-Id: <20190526010948.3923-6-palmer@sifive.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190526010948.3923-1-palmer@sifive.com> References: <20190526010948.3923-1-palmer@sifive.com> MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.215.196 Subject: [Qemu-devel] [PULL 05/29] target/riscv: Use --static-decode for decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , Palmer Dabbelt , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson The generated functions are only used within translate.c and do not need to be global, or declared. Signed-off-by: Richard Henderson Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- target/riscv/Makefile.objs | 8 ++++---- target/riscv/translate.c | 3 --- 2 files changed, 4 insertions(+), 7 deletions(-) -- 2.21.0 diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs index 9c6c1093271e..c7a1b063edc2 100644 --- a/target/riscv/Makefile.objs +++ b/target/riscv/Makefile.objs @@ -7,14 +7,14 @@ decode32-$(TARGET_RISCV64) += $(SRC_PATH)/target/riscv/insn32-64.decode target/riscv/decode_insn32.inc.c: $(decode32-y) $(DECODETREE) $(call quiet-command, \ - $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn32 $(decode32-y), \ - "GEN", $(TARGET_DIR)$@) + $(PYTHON) $(DECODETREE) -o $@ --static-decode decode_insn32 \ + $(decode32-y), "GEN", $(TARGET_DIR)$@) target/riscv/decode_insn16.inc.c: \ $(SRC_PATH)/target/riscv/insn16.decode $(DECODETREE) $(call quiet-command, \ - $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn16 --insnwidth 16 $<, \ - "GEN", $(TARGET_DIR)$@) + $(PYTHON) $(DECODETREE) -o $@ --static-decode decode_insn16 \ + --insnwidth 16 $<, "GEN", $(TARGET_DIR)$@) target/riscv/translate.o: target/riscv/decode_insn32.inc.c \ target/riscv/decode_insn16.inc.c diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 928374242e83..b09158117f32 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -558,7 +558,6 @@ static int ex_rvc_register(DisasContext *ctx, int reg) return 8 + reg; } -bool decode_insn32(DisasContext *ctx, uint32_t insn); /* Include the auto-generated decoder for 32 bit insn */ #include "decode_insn32.inc.c" @@ -701,8 +700,6 @@ static bool gen_shift(DisasContext *ctx, arg_r *a, # endif #endif -bool decode_insn16(DisasContext *ctx, uint16_t insn); -/* auto-generated decoder*/ #include "decode_insn16.inc.c" #include "insn_trans/trans_rvc.inc.c" From patchwork Sun May 26 01:09:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 165188 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp5440711ili; Sat, 25 May 2019 18:45:51 -0700 (PDT) X-Google-Smtp-Source: APXvYqwNQVSPf5rNdSqIkcDfFi2Zr9jh9fDJZ16IE6VykwLyVZ/OSlb1R1PzQUniOAtzTTv0UwAf X-Received: by 2002:a67:fd93:: with SMTP id k19mr46923459vsq.45.1558835150942; Sat, 25 May 2019 18:45:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1558835150; cv=none; d=google.com; s=arc-20160816; b=XbaJE9EL9hzoRJfYGPeiftTNSmtfsxoddcwSR5aN5T/OGe3w+lfwn1B7zJ6gfPTLuy 3y0574sl5U28h7ZPGdg7swWq1pnd6VoANrKnJPtP1VjtOw6N1OkcPeoX52us4hYpYUSA sL3ruCAwXWGNKQXZ/zdoLQZuY4zwkFqXGFihB8jQDylQsM3Ca56f06MPnoQCkwKDVYOG 6EvGzkwN4u/A0Ddk4Zsi4isouZ9QSgyGm5spkL22DDl9cRWKvNFDdOFCUJFbZRRGT7rs KenHw8gkoP6tE0h1n3wHD7rq0+VcCLGCqvElcwJFXaD8Zb3nQXD4rBVjbYty6apeLCAs +AKQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:to:from :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date; bh=jF0PA9R8NUiDGAz7tTfjlDMUwsEMu8tQxUWNp2LZs14=; b=IW8MRuHX3bgre/WzfoSrlhWQImEGVhSa2Hx9Z13oHZ3kmf6/gMz5TtsSJF/S8rEX0d /N473YUWlNWWxjhpmv5HJJ9wV6gfX3jAB6XRXpoehlsf7/EgbM2ZjkHFRBpHJdyEj1pM Su6L1FGW9Zae05SdHHun7h7jjx2G+VN9Dctoz+GH4t1YHZqoQFzj9XqYVbTnBD6RlW48 rk60yFuoJfqHhVllMD9jfwhzq2oH1HygHgCoDbucTDkqGCGMdLDhMIIk9maN04tsrdTN n/Cv9fUd7+X2BP6RtGz4JSBZEESOJXmAPzvCf0MIhtREOao4Nn44ulelJhfrpBEZt2t7 w/JA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id r13si2713400ual.194.2019.05.25.18.45.50 for (version=TLS1 cipher=AES128-SHA bits=128/128); Sat, 25 May 2019 18:45:50 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([127.0.0.1]:49405 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hUiEQ-00021X-Dm for patch@linaro.org; Sat, 25 May 2019 21:45:50 -0400 Received: from eggs.gnu.org ([209.51.188.92]:54116) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hUhxO-0003S6-Sl for qemu-devel@nongnu.org; Sat, 25 May 2019 21:28:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hUhfx-0005pj-14 for qemu-devel@nongnu.org; Sat, 25 May 2019 21:10:16 -0400 Received: from mail-pg1-f194.google.com ([209.85.215.194]:42328) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hUhfu-0005oR-Lb for qemu-devel@nongnu.org; Sat, 25 May 2019 21:10:11 -0400 Received: by mail-pg1-f194.google.com with SMTP id 33so4123101pgv.9 for ; Sat, 25 May 2019 18:10:09 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:cc:from:to; bh=jF0PA9R8NUiDGAz7tTfjlDMUwsEMu8tQxUWNp2LZs14=; b=i8ujr4Eq88dk3phWrpT4Eb+MNqwnzGUWN8tuP1SGNKr5skjKEgFRmLBQXDLrW/K0m8 z1lPo8Q4btue+arSnRAyzTY0edM12fpUKjFnr+dAEg7GMS+jMJLBucBUS6gjvHJfo7J8 n/Y7Hn+KugiCPT2GrX8e+vZvcHeKm4cY7f8bjfjrCa4Y7Q7Bzaimd6y1p6mz7Np7Pfxz CzBEuCkwHyZzmRO7f7ImzP7OKQGN7WZC/s9tzvqSOQu3eMV6e7UbULmYAf1ZR/BpkFJ5 ls+mzfo1FYMY4EtJSm6CtpuwbuSrxtpwnVYEzoNagry3CQB32VXTP5u156sWpXXp2fKq VqOg== X-Gm-Message-State: APjAAAXAJuQ62puD9jH1sBTqYJOf2VT5C0dvdiC0DIsuVv+9WhrhZksA Dv2jtSlcNHKnog6Z+oRSn2/U2Q== X-Received: by 2002:a63:1e62:: with SMTP id p34mr29943143pgm.49.1558833008421; Sat, 25 May 2019 18:10:08 -0700 (PDT) Received: from localhost ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id v93sm6522367pjb.6.2019.05.25.18.10.07 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 25 May 2019 18:10:07 -0700 (PDT) Date: Sat, 25 May 2019 18:09:25 -0700 Message-Id: <20190526010948.3923-7-palmer@sifive.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190526010948.3923-1-palmer@sifive.com> References: <20190526010948.3923-1-palmer@sifive.com> MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.215.194 Subject: [Qemu-devel] [PULL 06/29] target/riscv: Merge argument sets for insn32 and insn16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , Palmer Dabbelt , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson In some cases this allows us to directly use the insn32 translator function. In some cases we still need a shim. Signed-off-by: Richard Henderson Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- target/riscv/insn16.decode | 84 ++++++++------ target/riscv/insn_trans/trans_rvc.inc.c | 144 ++---------------------- 2 files changed, 58 insertions(+), 170 deletions(-) -- 2.21.0 diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode index 17cc52cf2ac2..d0cc778bc923 100644 --- a/target/riscv/insn16.decode +++ b/target/riscv/insn16.decode @@ -40,17 +40,24 @@ %imm_lui 12:s1 2:5 !function=ex_shift_12 +# Argument sets imported from insn32.decode: +&empty !extern +&r rd rs1 rs2 !extern +&i imm rs1 rd !extern +&s imm rs1 rs2 !extern +&j imm rd !extern +&b imm rs2 rs1 !extern +&u imm rd !extern +&shift shamt rs1 rd !extern # Argument sets: &cl rs1 rd &cl_dw uimm rs1 rd -&ci imm rd &ciw nzuimm rd &cs rs1 rs2 &cs_dw uimm rs1 rs2 &cb imm rs1 &cr rd rs2 -&cj imm &c_shift shamt rd &c_ld uimm rd @@ -61,23 +68,24 @@ &cfswsp_sdsp uimm_fswsp uimm_sdsp rs2 # Formats 16: -@cr .... ..... ..... .. &cr rs2=%rs2_5 %rd -@ci ... . ..... ..... .. &ci imm=%imm_ci %rd +@cr .... ..... ..... .. &r rs2=%rs2_5 rs1=%rd %rd +@ci ... . ..... ..... .. &i imm=%imm_ci rs1=%rd %rd @ciw ... ........ ... .. &ciw nzuimm=%nzuimm_ciw rd=%rs2_3 -@cl_d ... ... ... .. ... .. &cl_dw uimm=%uimm_cl_d rs1=%rs1_3 rd=%rs2_3 -@cl_w ... ... ... .. ... .. &cl_dw uimm=%uimm_cl_w rs1=%rs1_3 rd=%rs2_3 +@cl_d ... ... ... .. ... .. &i imm=%uimm_cl_d rs1=%rs1_3 rd=%rs2_3 +@cl_w ... ... ... .. ... .. &i imm=%uimm_cl_w rs1=%rs1_3 rd=%rs2_3 @cl ... ... ... .. ... .. &cl rs1=%rs1_3 rd=%rs2_3 @cs ... ... ... .. ... .. &cs rs1=%rs1_3 rs2=%rs2_3 -@cs_2 ... ... ... .. ... .. &cr rd=%rs1_3 rs2=%rs2_3 -@cs_d ... ... ... .. ... .. &cs_dw uimm=%uimm_cl_d rs1=%rs1_3 rs2=%rs2_3 -@cs_w ... ... ... .. ... .. &cs_dw uimm=%uimm_cl_w rs1=%rs1_3 rs2=%rs2_3 -@cb ... ... ... .. ... .. &cb imm=%imm_cb rs1=%rs1_3 -@cj ... ........... .. &cj imm=%imm_cj - -@c_ld ... . ..... ..... .. &c_ld uimm=%uimm_6bit_ld %rd -@c_lw ... . ..... ..... .. &c_ld uimm=%uimm_6bit_lw %rd -@c_sd ... . ..... ..... .. &c_sd uimm=%uimm_6bit_sd rs2=%rs2_5 -@c_sw ... . ..... ..... .. &c_sd uimm=%uimm_6bit_sw rs2=%rs2_5 +@cs_2 ... ... ... .. ... .. &r rs2=%rs2_3 rs1=%rs1_3 rd=%rs1_3 +@cs_d ... ... ... .. ... .. &s imm=%uimm_cl_d rs1=%rs1_3 rs2=%rs2_3 +@cs_w ... ... ... .. ... .. &s imm=%uimm_cl_w rs1=%rs1_3 rs2=%rs2_3 +@cj ... ........... .. &j imm=%imm_cj +@cb_z ... ... ... .. ... .. &b imm=%imm_cb rs1=%rs1_3 rs2=0 + +@c_ldsp ... . ..... ..... .. &i imm=%uimm_6bit_ld rs1=2 %rd +@c_lwsp ... . ..... ..... .. &i imm=%uimm_6bit_lw rs1=2 %rd +@c_sdsp ... . ..... ..... .. &s imm=%uimm_6bit_sd rs1=2 rs2=%rs2_5 +@c_swsp ... . ..... ..... .. &s imm=%uimm_6bit_sw rs1=2 rs2=%rs2_5 +@c_li ... . ..... ..... .. &i imm=%imm_ci rs1=0 %rd @c_addi16sp_lui ... . ..... ..... .. &caddi16sp_lui %imm_lui %imm_addi16sp %rd @c_flwsp_ldsp ... . ..... ..... .. &cflwsp_ldsp uimm_flwsp=%uimm_6bit_lw \ @@ -85,45 +93,47 @@ @c_fswsp_sdsp ... . ..... ..... .. &cfswsp_sdsp uimm_fswsp=%uimm_6bit_sw \ uimm_sdsp=%uimm_6bit_sd rs2=%rs2_5 -@c_shift ... . .. ... ..... .. &c_shift rd=%rs1_3 shamt=%nzuimm_6bit -@c_shift2 ... . .. ... ..... .. &c_shift rd=%rd shamt=%nzuimm_6bit +@c_shift ... . .. ... ..... .. \ + &shift rd=%rs1_3 rs1=%rs1_3 shamt=%nzuimm_6bit +@c_shift2 ... . .. ... ..... .. \ + &shift rd=%rd rs1=%rd shamt=%nzuimm_6bit -@c_andi ... . .. ... ..... .. &ci imm=%imm_ci rd=%rs1_3 +@c_andi ... . .. ... ..... .. &i imm=%imm_ci rs1=%rs1_3 rd=%rs1_3 # *** RV64C Standard Extension (Quadrant 0) *** c_addi4spn 000 ........ ... 00 @ciw -c_fld 001 ... ... .. ... 00 @cl_d -c_lw 010 ... ... .. ... 00 @cl_w +fld 001 ... ... .. ... 00 @cl_d +lw 010 ... ... .. ... 00 @cl_w c_flw_ld 011 --- ... -- ... 00 @cl #Note: Must parse uimm manually -c_fsd 101 ... ... .. ... 00 @cs_d -c_sw 110 ... ... .. ... 00 @cs_w +fsd 101 ... ... .. ... 00 @cs_d +sw 110 ... ... .. ... 00 @cs_w c_fsw_sd 111 --- ... -- ... 00 @cs #Note: Must parse uimm manually # *** RV64C Standard Extension (Quadrant 1) *** -c_addi 000 . ..... ..... 01 @ci +addi 000 . ..... ..... 01 @ci c_jal_addiw 001 . ..... ..... 01 @ci #Note: parse rd and/or imm manually -c_li 010 . ..... ..... 01 @ci +addi 010 . ..... ..... 01 @c_li c_addi16sp_lui 011 . ..... ..... 01 @c_addi16sp_lui # shares opc with C.LUI c_srli 100 . 00 ... ..... 01 @c_shift c_srai 100 . 01 ... ..... 01 @c_shift -c_andi 100 . 10 ... ..... 01 @c_andi -c_sub 100 0 11 ... 00 ... 01 @cs_2 -c_xor 100 0 11 ... 01 ... 01 @cs_2 -c_or 100 0 11 ... 10 ... 01 @cs_2 -c_and 100 0 11 ... 11 ... 01 @cs_2 +andi 100 . 10 ... ..... 01 @c_andi +sub 100 0 11 ... 00 ... 01 @cs_2 +xor 100 0 11 ... 01 ... 01 @cs_2 +or 100 0 11 ... 10 ... 01 @cs_2 +and 100 0 11 ... 11 ... 01 @cs_2 c_subw 100 1 11 ... 00 ... 01 @cs_2 c_addw 100 1 11 ... 01 ... 01 @cs_2 -c_j 101 ........... 01 @cj -c_beqz 110 ... ... ..... 01 @cb -c_bnez 111 ... ... ..... 01 @cb +jal 101 ........... 01 @cj rd=0 # C.J +beq 110 ... ... ..... 01 @cb_z +bne 111 ... ... ..... 01 @cb_z # *** RV64C Standard Extension (Quadrant 2) *** c_slli 000 . ..... ..... 10 @c_shift2 -c_fldsp 001 . ..... ..... 10 @c_ld -c_lwsp 010 . ..... ..... 10 @c_lw +fld 001 . ..... ..... 10 @c_ldsp +lw 010 . ..... ..... 10 @c_lwsp c_flwsp_ldsp 011 . ..... ..... 10 @c_flwsp_ldsp #C.LDSP:RV64;C.FLWSP:RV32 c_jr_mv 100 0 ..... ..... 10 @cr c_ebreak_jalr_add 100 1 ..... ..... 10 @cr -c_fsdsp 101 ...... ..... 10 @c_sd -c_swsp 110 . ..... ..... 10 @c_sw +fsd 101 ...... ..... 10 @c_sdsp +sw 110 . ..... ..... 10 @c_swsp c_fswsp_sdsp 111 . ..... ..... 10 @c_fswsp_sdsp #C.SDSP:RV64;C.FSWSP:RV32 diff --git a/target/riscv/insn_trans/trans_rvc.inc.c b/target/riscv/insn_trans/trans_rvc.inc.c index 3e5d6fd5eaf9..e840ac40dfe2 100644 --- a/target/riscv/insn_trans/trans_rvc.inc.c +++ b/target/riscv/insn_trans/trans_rvc.inc.c @@ -28,18 +28,6 @@ static bool trans_c_addi4spn(DisasContext *ctx, arg_c_addi4spn *a) return trans_addi(ctx, &arg); } -static bool trans_c_fld(DisasContext *ctx, arg_c_fld *a) -{ - arg_fld arg = { .rd = a->rd, .rs1 = a->rs1, .imm = a->uimm }; - return trans_fld(ctx, &arg); -} - -static bool trans_c_lw(DisasContext *ctx, arg_c_lw *a) -{ - arg_lw arg = { .rd = a->rd, .rs1 = a->rs1, .imm = a->uimm }; - return trans_lw(ctx, &arg); -} - static bool trans_c_flw_ld(DisasContext *ctx, arg_c_flw_ld *a) { #ifdef TARGET_RISCV32 @@ -47,31 +35,17 @@ static bool trans_c_flw_ld(DisasContext *ctx, arg_c_flw_ld *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); - arg_c_lw tmp; - decode_insn16_extract_cl_w(ctx, &tmp, ctx->opcode); - arg_flw arg = { .rd = tmp.rd, .rs1 = tmp.rs1, .imm = tmp.uimm }; + arg_i arg; + decode_insn16_extract_cl_w(ctx, &arg, ctx->opcode); return trans_flw(ctx, &arg); #else /* C.LD ( RV64C/RV128C-only ) */ - arg_c_fld tmp; - decode_insn16_extract_cl_d(ctx, &tmp, ctx->opcode); - arg_ld arg = { .rd = tmp.rd, .rs1 = tmp.rs1, .imm = tmp.uimm }; + arg_i arg; + decode_insn16_extract_cl_d(ctx, &arg, ctx->opcode); return trans_ld(ctx, &arg); #endif } -static bool trans_c_fsd(DisasContext *ctx, arg_c_fsd *a) -{ - arg_fsd arg = { .rs1 = a->rs1, .rs2 = a->rs2, .imm = a->uimm }; - return trans_fsd(ctx, &arg); -} - -static bool trans_c_sw(DisasContext *ctx, arg_c_sw *a) -{ - arg_sw arg = { .rs1 = a->rs1, .rs2 = a->rs2, .imm = a->uimm }; - return trans_sw(ctx, &arg); -} - static bool trans_c_fsw_sd(DisasContext *ctx, arg_c_fsw_sd *a) { #ifdef TARGET_RISCV32 @@ -79,34 +53,22 @@ static bool trans_c_fsw_sd(DisasContext *ctx, arg_c_fsw_sd *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); - arg_c_sw tmp; - decode_insn16_extract_cs_w(ctx, &tmp, ctx->opcode); - arg_fsw arg = { .rs1 = tmp.rs1, .rs2 = tmp.rs2, .imm = tmp.uimm }; + arg_s arg; + decode_insn16_extract_cs_w(ctx, &arg, ctx->opcode); return trans_fsw(ctx, &arg); #else /* C.SD ( RV64C/RV128C-only ) */ - arg_c_fsd tmp; - decode_insn16_extract_cs_d(ctx, &tmp, ctx->opcode); - arg_sd arg = { .rs1 = tmp.rs1, .rs2 = tmp.rs2, .imm = tmp.uimm }; + arg_s arg; + decode_insn16_extract_cs_d(ctx, &arg, ctx->opcode); return trans_sd(ctx, &arg); #endif } -static bool trans_c_addi(DisasContext *ctx, arg_c_addi *a) -{ - if (a->imm == 0) { - /* Hint: insn is valid but does not affect state */ - return true; - } - arg_addi arg = { .rd = a->rd, .rs1 = a->rd, .imm = a->imm }; - return trans_addi(ctx, &arg); -} - static bool trans_c_jal_addiw(DisasContext *ctx, arg_c_jal_addiw *a) { #ifdef TARGET_RISCV32 /* C.JAL */ - arg_c_j tmp; + arg_j tmp; decode_insn16_extract_cj(ctx, &tmp, ctx->opcode); arg_jal arg = { .rd = 1, .imm = tmp.imm }; return trans_jal(ctx, &arg); @@ -117,16 +79,6 @@ static bool trans_c_jal_addiw(DisasContext *ctx, arg_c_jal_addiw *a) #endif } -static bool trans_c_li(DisasContext *ctx, arg_c_li *a) -{ - if (a->rd == 0) { - /* Hint: insn is valid but does not affect state */ - return true; - } - arg_addi arg = { .rd = a->rd, .rs1 = 0, .imm = a->imm }; - return trans_addi(ctx, &arg); -} - static bool trans_c_addi16sp_lui(DisasContext *ctx, arg_c_addi16sp_lui *a) { if (a->rd == 2) { @@ -177,41 +129,10 @@ static bool trans_c_srai(DisasContext *ctx, arg_c_srai *a) return trans_srai(ctx, &arg); } -static bool trans_c_andi(DisasContext *ctx, arg_c_andi *a) -{ - arg_andi arg = { .rd = a->rd, .rs1 = a->rd, .imm = a->imm }; - return trans_andi(ctx, &arg); -} - -static bool trans_c_sub(DisasContext *ctx, arg_c_sub *a) -{ - arg_sub arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 }; - return trans_sub(ctx, &arg); -} - -static bool trans_c_xor(DisasContext *ctx, arg_c_xor *a) -{ - arg_xor arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 }; - return trans_xor(ctx, &arg); -} - -static bool trans_c_or(DisasContext *ctx, arg_c_or *a) -{ - arg_or arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 }; - return trans_or(ctx, &arg); -} - -static bool trans_c_and(DisasContext *ctx, arg_c_and *a) -{ - arg_and arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 }; - return trans_and(ctx, &arg); -} - static bool trans_c_subw(DisasContext *ctx, arg_c_subw *a) { #ifdef TARGET_RISCV64 - arg_subw arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 }; - return trans_subw(ctx, &arg); + return trans_subw(ctx, a); #else return false; #endif @@ -220,31 +141,12 @@ static bool trans_c_subw(DisasContext *ctx, arg_c_subw *a) static bool trans_c_addw(DisasContext *ctx, arg_c_addw *a) { #ifdef TARGET_RISCV64 - arg_addw arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 }; - return trans_addw(ctx, &arg); + return trans_addw(ctx, a); #else return false; #endif } -static bool trans_c_j(DisasContext *ctx, arg_c_j *a) -{ - arg_jal arg = { .rd = 0, .imm = a->imm }; - return trans_jal(ctx, &arg); -} - -static bool trans_c_beqz(DisasContext *ctx, arg_c_beqz *a) -{ - arg_beq arg = { .rs1 = a->rs1, .rs2 = 0, .imm = a->imm }; - return trans_beq(ctx, &arg); -} - -static bool trans_c_bnez(DisasContext *ctx, arg_c_bnez *a) -{ - arg_bne arg = { .rs1 = a->rs1, .rs2 = 0, .imm = a->imm }; - return trans_bne(ctx, &arg); -} - static bool trans_c_slli(DisasContext *ctx, arg_c_slli *a) { int shamt = a->shamt; @@ -261,18 +163,6 @@ static bool trans_c_slli(DisasContext *ctx, arg_c_slli *a) return trans_slli(ctx, &arg); } -static bool trans_c_fldsp(DisasContext *ctx, arg_c_fldsp *a) -{ - arg_fld arg = { .rd = a->rd, .rs1 = 2, .imm = a->uimm }; - return trans_fld(ctx, &arg); -} - -static bool trans_c_lwsp(DisasContext *ctx, arg_c_lwsp *a) -{ - arg_lw arg = { .rd = a->rd, .rs1 = 2, .imm = a->uimm }; - return trans_lw(ctx, &arg); -} - static bool trans_c_flwsp_ldsp(DisasContext *ctx, arg_c_flwsp_ldsp *a) { #ifdef TARGET_RISCV32 @@ -321,18 +211,6 @@ static bool trans_c_ebreak_jalr_add(DisasContext *ctx, arg_c_ebreak_jalr_add *a) return false; } -static bool trans_c_fsdsp(DisasContext *ctx, arg_c_fsdsp *a) -{ - arg_fsd arg = { .rs1 = 2, .rs2 = a->rs2, .imm = a->uimm }; - return trans_fsd(ctx, &arg); -} - -static bool trans_c_swsp(DisasContext *ctx, arg_c_swsp *a) -{ - arg_sw arg = { .rs1 = 2, .rs2 = a->rs2, .imm = a->uimm }; - return trans_sw(ctx, &arg); -} - static bool trans_c_fswsp_sdsp(DisasContext *ctx, arg_c_fswsp_sdsp *a) { #ifdef TARGET_RISCV32 From patchwork Sun May 26 01:09:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 165190 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp5441917ili; Sat, 25 May 2019 18:47:54 -0700 (PDT) X-Google-Smtp-Source: APXvYqy5soqWptqPgiR1d0GRpW5shanZnj9PHYIy671YxWHC+gog8vpXLDhj0b/lGPPUuhMKTf6F X-Received: by 2002:ab0:2395:: with SMTP id b21mr21143574uan.108.1558835274273; Sat, 25 May 2019 18:47:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1558835274; cv=none; d=google.com; s=arc-20160816; b=LafW45Ykq0ANiMFpHVG7PcC/zUAQhUbINRFne+5UHPzurhkmYW0qC9NhbKAfGOqVaG kCWBC0v1MHJgkX2wXud4KRGzXDH2YO5gOdeB/it801XBjZ/af2PnalKGEeedkYesho+D gAW+Lw1rX+aaSYoXhAOqgJqy2623GmIC7zrWpmWWb1WU1wYSNULEt/cXyQCzZLrDFC9S IQ0WLRgLoVxO8Iv2gBqmPwb10dJ2CmGX3Ppl1gsZBdpdFC9GgBEnI9RyX9CLu5JJaQD4 XZvxR6HmPtwOqSUbqFGdAO9OyBoMcu4bH0e60Ftq9jWXKAAfoYFLpHkC3WOHY/+itKz1 rR7w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:to:from :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date; bh=ytTW1+TTg5W28dEVYeOyH5hBZS9j7YYQ7XabUrTBVLA=; b=SI2TFlwvQV1ZtTJD2LNzlIq1K3qyhBybJHp6A1HYsnhiu2QHH0c0+unAkfPiWSK1DT nqoT7a1NUwQayplYjIkIDuKJNJp44cXkqgZ1VemzYI5uF//DzpAhtwBK17hrssRRr21X PxymOrC7S5/WOSPLSdRkvNPC7g3D1E6z1lIEP40cWx+RC+qfx5rz67JfH5KPehfHVr4C vT+4veXFyTuIwDyq7r5wgqQcI5T5QS7hsNSpXL43u+j0H5Xq2Q9t3WErlXfu/U6UCv/t Ppc+56NpCBTuLFV35qU3UkGqMuYJ1y1jekuHIez4D/sptj9Ifx1b2urrp9JWkpEZjJ8Q +kZg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id p16si1011042uao.159.2019.05.25.18.47.54 for (version=TLS1 cipher=AES128-SHA bits=128/128); Sat, 25 May 2019 18:47:54 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([127.0.0.1]:49419 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hUiGP-0003of-PE for patch@linaro.org; Sat, 25 May 2019 21:47:53 -0400 Received: from eggs.gnu.org ([209.51.188.92]:53756) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hUhxP-0003GC-I3 for qemu-devel@nongnu.org; Sat, 25 May 2019 21:28:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hUhfy-0005qJ-AN for qemu-devel@nongnu.org; Sat, 25 May 2019 21:10:16 -0400 Received: from mail-pg1-f193.google.com ([209.85.215.193]:40136) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hUhfw-0005p1-EY for qemu-devel@nongnu.org; Sat, 25 May 2019 21:10:13 -0400 Received: by mail-pg1-f193.google.com with SMTP id d30so7080817pgm.7 for ; Sat, 25 May 2019 18:10:11 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:cc:from:to; bh=ytTW1+TTg5W28dEVYeOyH5hBZS9j7YYQ7XabUrTBVLA=; b=qEgfadZW6IfMployi46wC92Q+b60eujNL2VHnPYKiZ0qQ/LSMszUBHvGNwUplzvK3F scyLgHRfef/5HS2jFa56L9k7CYeDdQih1h0uFPxhc5xfhPBx2gc9ijzzS5BSMtG7shqk cXyL71p2drU3zc3pPiSXa1l/P5d1r/P+jTjkbjgHFTmvwCAwIe0LfkS6BH/lVkd9RbtT M9nTf8iz8K0WV4k0maRXQOhqq4DTrm2fc3Bv9tYiOm60eEMtzSDmbuirQEyO+O8/V2Y2 h/7Qp2AkUTFlDD7QrsQ8w6IL0Cg+ZvVol3JyAsoXAM+5tT8+4udLfD/TdZue8L0bcBKi IlIg== X-Gm-Message-State: APjAAAVQfWsAswTvWk9CDAsZzywfFP5jYYYHkH2mE8PvD1EvVu90VTDp gV+REk1n7BpwUIKLN5Rk9109Dw== X-Received: by 2002:a63:a449:: with SMTP id c9mr27145842pgp.149.1558833010301; Sat, 25 May 2019 18:10:10 -0700 (PDT) Received: from localhost ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id f38sm5276375pgm.85.2019.05.25.18.10.08 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 25 May 2019 18:10:09 -0700 (PDT) Date: Sat, 25 May 2019 18:09:26 -0700 Message-Id: <20190526010948.3923-8-palmer@sifive.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190526010948.3923-1-palmer@sifive.com> References: <20190526010948.3923-1-palmer@sifive.com> MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.215.193 Subject: [Qemu-devel] [PULL 07/29] target/riscv: Merge argument decode for RVC shifti X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , Palmer Dabbelt , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Special handling for IMM==0 is the only difference between RVC shifti and RVI shifti. This can be handled with !function. Signed-off-by: Richard Henderson Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- target/riscv/insn16.decode | 12 +++---- target/riscv/insn_trans/trans_rvc.inc.c | 47 ------------------------- target/riscv/translate.c | 6 ++++ 3 files changed, 12 insertions(+), 53 deletions(-) -- 2.21.0 diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode index d0cc778bc923..add9cf3923a1 100644 --- a/target/riscv/insn16.decode +++ b/target/riscv/insn16.decode @@ -30,7 +30,7 @@ %imm_cb 12:s1 5:2 2:1 10:2 3:2 !function=ex_shift_1 %imm_cj 12:s1 8:1 9:2 6:1 7:1 2:1 11:1 3:3 !function=ex_shift_1 -%nzuimm_6bit 12:1 2:5 +%shimm_6bit 12:1 2:5 !function=ex_rvc_shifti %uimm_6bit_ld 2:3 12:1 5:2 !function=ex_shift_3 %uimm_6bit_lw 2:2 12:1 4:3 !function=ex_shift_2 %uimm_6bit_sd 7:3 10:3 !function=ex_shift_3 @@ -94,9 +94,9 @@ uimm_sdsp=%uimm_6bit_sd rs2=%rs2_5 @c_shift ... . .. ... ..... .. \ - &shift rd=%rs1_3 rs1=%rs1_3 shamt=%nzuimm_6bit + &shift rd=%rs1_3 rs1=%rs1_3 shamt=%shimm_6bit @c_shift2 ... . .. ... ..... .. \ - &shift rd=%rd rs1=%rd shamt=%nzuimm_6bit + &shift rd=%rd rs1=%rd shamt=%shimm_6bit @c_andi ... . .. ... ..... .. &i imm=%imm_ci rs1=%rs1_3 rd=%rs1_3 @@ -114,8 +114,8 @@ addi 000 . ..... ..... 01 @ci c_jal_addiw 001 . ..... ..... 01 @ci #Note: parse rd and/or imm manually addi 010 . ..... ..... 01 @c_li c_addi16sp_lui 011 . ..... ..... 01 @c_addi16sp_lui # shares opc with C.LUI -c_srli 100 . 00 ... ..... 01 @c_shift -c_srai 100 . 01 ... ..... 01 @c_shift +srli 100 . 00 ... ..... 01 @c_shift +srai 100 . 01 ... ..... 01 @c_shift andi 100 . 10 ... ..... 01 @c_andi sub 100 0 11 ... 00 ... 01 @cs_2 xor 100 0 11 ... 01 ... 01 @cs_2 @@ -128,7 +128,7 @@ beq 110 ... ... ..... 01 @cb_z bne 111 ... ... ..... 01 @cb_z # *** RV64C Standard Extension (Quadrant 2) *** -c_slli 000 . ..... ..... 10 @c_shift2 +slli 000 . ..... ..... 10 @c_shift2 fld 001 . ..... ..... 10 @c_ldsp lw 010 . ..... ..... 10 @c_lwsp c_flwsp_ldsp 011 . ..... ..... 10 @c_flwsp_ldsp #C.LDSP:RV64;C.FLWSP:RV32 diff --git a/target/riscv/insn_trans/trans_rvc.inc.c b/target/riscv/insn_trans/trans_rvc.inc.c index e840ac40dfe2..dbe9624e324b 100644 --- a/target/riscv/insn_trans/trans_rvc.inc.c +++ b/target/riscv/insn_trans/trans_rvc.inc.c @@ -97,37 +97,6 @@ static bool trans_c_addi16sp_lui(DisasContext *ctx, arg_c_addi16sp_lui *a) return false; } -static bool trans_c_srli(DisasContext *ctx, arg_c_srli *a) -{ - int shamt = a->shamt; - if (shamt == 0) { - /* For RV128 a shamt of 0 means a shift by 64 */ - shamt = 64; - } - /* Ensure, that shamt[5] is zero for RV32 */ - if (shamt >= TARGET_LONG_BITS) { - return false; - } - - arg_srli arg = { .rd = a->rd, .rs1 = a->rd, .shamt = a->shamt }; - return trans_srli(ctx, &arg); -} - -static bool trans_c_srai(DisasContext *ctx, arg_c_srai *a) -{ - int shamt = a->shamt; - if (shamt == 0) { - /* For RV128 a shamt of 0 means a shift by 64 */ - shamt = 64; - } - /* Ensure, that shamt[5] is zero for RV32 */ - if (shamt >= TARGET_LONG_BITS) { - return false; - } - - arg_srai arg = { .rd = a->rd, .rs1 = a->rd, .shamt = a->shamt }; - return trans_srai(ctx, &arg); -} static bool trans_c_subw(DisasContext *ctx, arg_c_subw *a) { @@ -147,22 +116,6 @@ static bool trans_c_addw(DisasContext *ctx, arg_c_addw *a) #endif } -static bool trans_c_slli(DisasContext *ctx, arg_c_slli *a) -{ - int shamt = a->shamt; - if (shamt == 0) { - /* For RV128 a shamt of 0 means a shift by 64 */ - shamt = 64; - } - /* Ensure, that shamt[5] is zero for RV32 */ - if (shamt >= TARGET_LONG_BITS) { - return false; - } - - arg_slli arg = { .rd = a->rd, .rs1 = a->rd, .shamt = a->shamt }; - return trans_slli(ctx, &arg); -} - static bool trans_c_flwsp_ldsp(DisasContext *ctx, arg_c_flwsp_ldsp *a) { #ifdef TARGET_RISCV32 diff --git a/target/riscv/translate.c b/target/riscv/translate.c index b09158117f32..4cdffb23a475 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -558,6 +558,12 @@ static int ex_rvc_register(DisasContext *ctx, int reg) return 8 + reg; } +static int ex_rvc_shifti(DisasContext *ctx, int imm) +{ + /* For RV128 a shamt of 0 means a shift by 64. */ + return imm ? imm : 64; +} + /* Include the auto-generated decoder for 32 bit insn */ #include "decode_insn32.inc.c" From patchwork Sun May 26 01:09:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 165184 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp5434103ili; Sat, 25 May 2019 18:34:52 -0700 (PDT) X-Google-Smtp-Source: APXvYqy01wkgtL506z7FcCaYnG+QdyohmnL+k0dMYcnPI0oCm8uOZChhCIa/uQSy9X4lzqxg9LR3 X-Received: by 2002:a67:1205:: with SMTP id 5mr25533367vss.156.1558834492746; Sat, 25 May 2019 18:34:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1558834492; cv=none; d=google.com; s=arc-20160816; b=TPwYYhhXatyV7Qic6LEx1+/BA0TKWbBQ1HS9SHmRqrU2baoXuldcWkdlupmned5HCW BN+Fb4X1/11sL96s7D9Nk1t1sp0RrAG3WFXSOs6w9lxboKzYrOwI1ncp/7XlyyTOD5Yf HJRPTdiyc9ueLELujl5GXZ23wOI0HuR2zf+VItB9SJBiDuraG++JTGRft7TG80J90fhN d2idvEZ+PiQ49cJqi3LGWw0EAILDOq2prO+QoWtwYPXbi1/6f1LW9SC9cAUKE2EHHQsm c7DZgZg7fROAtCCWWV666pbmTQKITqRUO5ugbkIuo/S9zJGZDQf1RNl9IacN7P2VFGjs UhMQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:to:from :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date; bh=eOXAXFFSJfATTExwJ4CqguE04SpAoRo5k7qmw0rhDJQ=; b=RmSjtPZRPsxqlTB0bgafM9zFTkiaRuThd7/o/tPRk9Yzo1TZaO72oMxnhs/STonzWJ 9WD7Q4FRSqMMuUSgftCEDgyBRUNY1oxc+2EBpH3ye0yks+7AFbZrGHgDekAI3CbLrW5w h85wVybo0H+LhlDb1LcM5BXl0BQOU0PLHrXDJwEULMPBg/qPbKhlMYj08asOrcyZ/rdv DCgta5Xa9Dc+XH5lB5baQr0NlnLMV1Vt26uCydfc1puxgRg46m3gJp8ORQEcBihonHqQ EeriW9hMvDfbT2kYAQaIP4ynaw6sSGFb4h7lXw3aj0ebcoH6i+ZKeF7J64ExzTP4tmRL QsUg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id c9si2659951uaq.246.2019.05.25.18.34.52 for (version=TLS1 cipher=AES128-SHA bits=128/128); Sat, 25 May 2019 18:34:52 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([127.0.0.1]:49179 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hUi3o-000141-8l for patch@linaro.org; Sat, 25 May 2019 21:34:52 -0400 Received: from eggs.gnu.org ([209.51.188.92]:53756) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hUhxN-0003GC-S2 for qemu-devel@nongnu.org; Sat, 25 May 2019 21:28:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hUhg2-0005sH-4i for qemu-devel@nongnu.org; Sat, 25 May 2019 21:10:20 -0400 Received: from mail-pg1-f195.google.com ([209.85.215.195]:38104) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hUhfy-0005pW-Bm for qemu-devel@nongnu.org; Sat, 25 May 2019 21:10:16 -0400 Received: by mail-pg1-f195.google.com with SMTP id v11so7092029pgl.5 for ; Sat, 25 May 2019 18:10:12 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:cc:from:to; bh=eOXAXFFSJfATTExwJ4CqguE04SpAoRo5k7qmw0rhDJQ=; b=DKkVtZoBd+afWyilmZbJHHXfna/c5Nhd9u4veLfWqyEKMQq/3iGPJuYFYx2Q7cuHgS InMXOTBzua4+uPIV1OomIubqs5vzjsN0zj+kwsSr6W4Be6xTZsFg2oQDgSv6qBC2uPft ll+DmMfALDa8Bm9ARJKHnM7AdJnb51qyOuxQN3xQ0NOOpDiPfXei/XfyvA9bqr00qNQu DnP94c4gsNHrLSUcTrkj58Ag3lwqBnrMmgiHsIqE96u1hPq33m/2liUiqX/oMeKSp5eU MjH/lW5yK/deqV3DgMtq5RNwro1tmhItpD0LrqX4w/kzzNcbSiMHduhPTA7iOM/VtJmR tNrw== X-Gm-Message-State: APjAAAUgVrcJkUT1Qhq5GipGBH+0fRdSe9+FM4Fz/ry+n5BTu6M/StyT 0hXkHHc+DGCB2xSFyk05ILrDtg== X-Received: by 2002:a62:1990:: with SMTP id 138mr26327169pfz.133.1558833011593; Sat, 25 May 2019 18:10:11 -0700 (PDT) Received: from localhost ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id 206sm5605493pfy.90.2019.05.25.18.10.10 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 25 May 2019 18:10:10 -0700 (PDT) Date: Sat, 25 May 2019 18:09:27 -0700 Message-Id: <20190526010948.3923-9-palmer@sifive.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190526010948.3923-1-palmer@sifive.com> References: <20190526010948.3923-1-palmer@sifive.com> MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.215.195 Subject: [Qemu-devel] [PULL 08/29] target/riscv: Use pattern groups in insn16.decode X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , Palmer Dabbelt , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson This eliminates about half of the complicated decode bits within insn_trans/trans_rvc.inc.c. Signed-off-by: Richard Henderson Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- target/riscv/insn16.decode | 29 +++++++++--- target/riscv/insn_trans/trans_rvc.inc.c | 63 ------------------------- target/riscv/insn_trans/trans_rvi.inc.c | 6 +++ 3 files changed, 29 insertions(+), 69 deletions(-) -- 2.21.0 diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode index add9cf3923a1..3c79edf1c996 100644 --- a/target/riscv/insn16.decode +++ b/target/riscv/insn16.decode @@ -70,7 +70,6 @@ # Formats 16: @cr .... ..... ..... .. &r rs2=%rs2_5 rs1=%rd %rd @ci ... . ..... ..... .. &i imm=%imm_ci rs1=%rd %rd -@ciw ... ........ ... .. &ciw nzuimm=%nzuimm_ciw rd=%rs2_3 @cl_d ... ... ... .. ... .. &i imm=%uimm_cl_d rs1=%rs1_3 rd=%rs2_3 @cl_w ... ... ... .. ... .. &i imm=%uimm_cl_w rs1=%rs1_3 rd=%rs2_3 @cl ... ... ... .. ... .. &cl rs1=%rs1_3 rd=%rs2_3 @@ -86,8 +85,12 @@ @c_sdsp ... . ..... ..... .. &s imm=%uimm_6bit_sd rs1=2 rs2=%rs2_5 @c_swsp ... . ..... ..... .. &s imm=%uimm_6bit_sw rs1=2 rs2=%rs2_5 @c_li ... . ..... ..... .. &i imm=%imm_ci rs1=0 %rd +@c_lui ... . ..... ..... .. &u imm=%imm_lui %rd +@c_jalr ... . ..... ..... .. &i imm=0 rs1=%rd +@c_mv ... . ..... ..... .. &i imm=0 rs1=%rs2_5 %rd -@c_addi16sp_lui ... . ..... ..... .. &caddi16sp_lui %imm_lui %imm_addi16sp %rd +@c_addi4spn ... . ..... ..... .. &i imm=%nzuimm_ciw rs1=2 rd=%rs2_3 +@c_addi16sp ... . ..... ..... .. &i imm=%imm_addi16sp rs1=2 rd=2 @c_flwsp_ldsp ... . ..... ..... .. &cflwsp_ldsp uimm_flwsp=%uimm_6bit_lw \ uimm_ldsp=%uimm_6bit_ld %rd @c_fswsp_sdsp ... . ..... ..... .. &cfswsp_sdsp uimm_fswsp=%uimm_6bit_sw \ @@ -101,7 +104,11 @@ @c_andi ... . .. ... ..... .. &i imm=%imm_ci rs1=%rs1_3 rd=%rs1_3 # *** RV64C Standard Extension (Quadrant 0) *** -c_addi4spn 000 ........ ... 00 @ciw +{ + # Opcode of all zeros is illegal; rd != 0, nzuimm == 0 is reserved. + illegal 000 000 000 00 --- 00 + addi 000 ... ... .. ... 00 @c_addi4spn +} fld 001 ... ... .. ... 00 @cl_d lw 010 ... ... .. ... 00 @cl_w c_flw_ld 011 --- ... -- ... 00 @cl #Note: Must parse uimm manually @@ -113,7 +120,10 @@ c_fsw_sd 111 --- ... -- ... 00 @cs #Note: Must parse uimm manually addi 000 . ..... ..... 01 @ci c_jal_addiw 001 . ..... ..... 01 @ci #Note: parse rd and/or imm manually addi 010 . ..... ..... 01 @c_li -c_addi16sp_lui 011 . ..... ..... 01 @c_addi16sp_lui # shares opc with C.LUI +{ + addi 011 . 00010 ..... 01 @c_addi16sp + lui 011 . ..... ..... 01 @c_lui +} srli 100 . 00 ... ..... 01 @c_shift srai 100 . 01 ... ..... 01 @c_shift andi 100 . 10 ... ..... 01 @c_andi @@ -132,8 +142,15 @@ slli 000 . ..... ..... 10 @c_shift2 fld 001 . ..... ..... 10 @c_ldsp lw 010 . ..... ..... 10 @c_lwsp c_flwsp_ldsp 011 . ..... ..... 10 @c_flwsp_ldsp #C.LDSP:RV64;C.FLWSP:RV32 -c_jr_mv 100 0 ..... ..... 10 @cr -c_ebreak_jalr_add 100 1 ..... ..... 10 @cr +{ + jalr 100 0 ..... 00000 10 @c_jalr rd=0 # C.JR + addi 100 0 ..... ..... 10 @c_mv +} +{ + ebreak 100 1 00000 00000 10 + jalr 100 1 ..... 00000 10 @c_jalr rd=1 # C.JALR + add 100 1 ..... ..... 10 @cr +} fsd 101 ...... ..... 10 @c_sdsp sw 110 . ..... ..... 10 @c_swsp c_fswsp_sdsp 111 . ..... ..... 10 @c_fswsp_sdsp #C.SDSP:RV64;C.FSWSP:RV32 diff --git a/target/riscv/insn_trans/trans_rvc.inc.c b/target/riscv/insn_trans/trans_rvc.inc.c index dbe9624e324b..3fe6ad9d4592 100644 --- a/target/riscv/insn_trans/trans_rvc.inc.c +++ b/target/riscv/insn_trans/trans_rvc.inc.c @@ -18,16 +18,6 @@ * this program. If not, see . */ -static bool trans_c_addi4spn(DisasContext *ctx, arg_c_addi4spn *a) -{ - if (a->nzuimm == 0) { - /* Reserved in ISA */ - return false; - } - arg_addi arg = { .rd = a->rd, .rs1 = 2, .imm = a->nzuimm }; - return trans_addi(ctx, &arg); -} - static bool trans_c_flw_ld(DisasContext *ctx, arg_c_flw_ld *a) { #ifdef TARGET_RISCV32 @@ -79,25 +69,6 @@ static bool trans_c_jal_addiw(DisasContext *ctx, arg_c_jal_addiw *a) #endif } -static bool trans_c_addi16sp_lui(DisasContext *ctx, arg_c_addi16sp_lui *a) -{ - if (a->rd == 2) { - /* C.ADDI16SP */ - arg_addi arg = { .rd = 2, .rs1 = 2, .imm = a->imm_addi16sp }; - return trans_addi(ctx, &arg); - } else if (a->imm_lui != 0) { - /* C.LUI */ - if (a->rd == 0) { - /* Hint: insn is valid but does not affect state */ - return true; - } - arg_lui arg = { .rd = a->rd, .imm = a->imm_lui }; - return trans_lui(ctx, &arg); - } - return false; -} - - static bool trans_c_subw(DisasContext *ctx, arg_c_subw *a) { #ifdef TARGET_RISCV64 @@ -130,40 +101,6 @@ static bool trans_c_flwsp_ldsp(DisasContext *ctx, arg_c_flwsp_ldsp *a) return false; } -static bool trans_c_jr_mv(DisasContext *ctx, arg_c_jr_mv *a) -{ - if (a->rd != 0 && a->rs2 == 0) { - /* C.JR */ - arg_jalr arg = { .rd = 0, .rs1 = a->rd, .imm = 0 }; - return trans_jalr(ctx, &arg); - } else if (a->rd != 0 && a->rs2 != 0) { - /* C.MV */ - arg_add arg = { .rd = a->rd, .rs1 = 0, .rs2 = a->rs2 }; - return trans_add(ctx, &arg); - } - return false; -} - -static bool trans_c_ebreak_jalr_add(DisasContext *ctx, arg_c_ebreak_jalr_add *a) -{ - if (a->rd == 0 && a->rs2 == 0) { - /* C.EBREAK */ - arg_ebreak arg = { }; - return trans_ebreak(ctx, &arg); - } else if (a->rd != 0) { - if (a->rs2 == 0) { - /* C.JALR */ - arg_jalr arg = { .rd = 1, .rs1 = a->rd, .imm = 0 }; - return trans_jalr(ctx, &arg); - } else { - /* C.ADD */ - arg_add arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 }; - return trans_add(ctx, &arg); - } - } - return false; -} - static bool trans_c_fswsp_sdsp(DisasContext *ctx, arg_c_fswsp_sdsp *a) { #ifdef TARGET_RISCV32 diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c index 37b0b9dd198e..b5a5b4a199f8 100644 --- a/target/riscv/insn_trans/trans_rvi.inc.c +++ b/target/riscv/insn_trans/trans_rvi.inc.c @@ -18,6 +18,12 @@ * this program. If not, see . */ +static bool trans_illegal(DisasContext *ctx, arg_empty *a) +{ + gen_exception_illegal(ctx); + return true; +} + static bool trans_lui(DisasContext *ctx, arg_lui *a) { if (a->rd != 0) { From patchwork Sun May 26 01:09:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 165187 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp5440475ili; Sat, 25 May 2019 18:45:29 -0700 (PDT) X-Google-Smtp-Source: APXvYqyjnqojxcwzxJh9kbwO6shDieLBYFJ6jpUu4o0P8k8q/AB+T7RzICrg73arkoFKQkwRBv2F X-Received: by 2002:a1f:174d:: with SMTP id 74mr13199128vkx.39.1558835129075; Sat, 25 May 2019 18:45:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1558835129; cv=none; d=google.com; s=arc-20160816; b=mKFzD4ip0wtM81nzIrkBD8JkrvLg0uu87wJP2nJB6HP8TwPhZm8lMLOnC1E/PrGEt5 k1vGps6e6elYZVWp8ntpma83W4tJvQoSkk4IRBYM9PpKh9NqX7Oq3+RGrfFBhU0xU/t4 7uztpS1VCQ7QePhLk1FZ1sOClhzWDmNQF+SihNmzvWKFsveBWuCvUbpUdPjC+/xRfRpD IYWol+fsoi4ykMo1HRJ66KH6fFf7TqB9xv0ojfHUT5X3DUnfawf9YFpr9lOrf6htRwIF LeKHBfduJYSNHV/qUoLKCVBdgzYjbIrBuy621rCxhVflf4bO96swZoJYyeMCu5E4rwAe 3DGw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:to:from :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date; bh=TIaBbwyzuMcSLzuMAKVEHd8Cem6BcGVf0J9D6QhrDNU=; b=rXnzmp8EtqDMPTNMy4mECFCR/t9oYaT0ySmCakHo282oriO4AWXSNyQOImTVndW9a/ FgRO9TE3T7H2KFJHgdG4p3/SBJkQwkE79m604ZCzhiQ72vx7ia8mVCAIlaqwRUAN8YNc +aJkswWMCCk7++WDTyOxADWLoq4LzKRNlLmKUBn8rxzAFPgZiavjnnHf8LvEQKEwV1Hn 1w+bMQ97g3xxpbvE9eBCWiwfg5iPyU2hSzYjStFgOpz0mDy+kcarbbUvDYa0EZQlPI3X VR48EZGipCIQpEfJ9jIFrZOEpwra7FIKrhAzEkgxu+FfCW6vOZKXey++cawTbOxPBgrz yipg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id m5si2577159ual.214.2019.05.25.18.45.28 for (version=TLS1 cipher=AES128-SHA bits=128/128); Sat, 25 May 2019 18:45:29 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([127.0.0.1]:49402 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hUiE4-0001yC-Hg for patch@linaro.org; Sat, 25 May 2019 21:45:28 -0400 Received: from eggs.gnu.org ([209.51.188.92]:53938) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hUhxN-0003Hg-BZ for qemu-devel@nongnu.org; Sat, 25 May 2019 21:28:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hUhg4-0005ws-4z for qemu-devel@nongnu.org; Sat, 25 May 2019 21:10:23 -0400 Received: from mail-pg1-f194.google.com ([209.85.215.194]:44761) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hUhg2-0005qF-2c for qemu-devel@nongnu.org; Sat, 25 May 2019 21:10:20 -0400 Received: by mail-pg1-f194.google.com with SMTP id n2so7074081pgp.11 for ; Sat, 25 May 2019 18:10:14 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:cc:from:to; bh=TIaBbwyzuMcSLzuMAKVEHd8Cem6BcGVf0J9D6QhrDNU=; b=iX+D22WILg22Rr2jnCpMwXLioXlG5aV11pTq5qzXO3dHvC5b79cjELgWuqfOyJDwFY lYDi6OrVD2o9950YBx8YB19skxoOzsJkqMC+d9QctQqmaP4lqmrNtCPn+3FY+Cgdw1fl yJjnI/PHRZAaA15UP+ixzTvzGtLLUnb8XV/OePJRMgtgJDSG4vMeUIFSlinW2DgEsGVh zpXu90MBoxBLySGLGoLRdpdxKmoWoIcFAhBHV3CdoycNSMXwSDRIHzo9mfmU9Y1B/DmE rpPbF7LN1fkqyNokSDep6B8tNCI61w65SMOsIAygX6OT3qEXKUsLuG3NARVzLtYgQ3wK yA2Q== X-Gm-Message-State: APjAAAXv5GBkzAfprwATlbtDfdWd7ddrCeC0vtt11Tj7jC68SQnWodxm Egol5LvxsA8eUWcst/N3H8475Q== X-Received: by 2002:a17:90a:350d:: with SMTP id q13mr20448242pjb.20.1558833013351; Sat, 25 May 2019 18:10:13 -0700 (PDT) Received: from localhost ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id f11sm5425875pjg.1.2019.05.25.18.10.12 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 25 May 2019 18:10:12 -0700 (PDT) Date: Sat, 25 May 2019 18:09:28 -0700 Message-Id: <20190526010948.3923-10-palmer@sifive.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190526010948.3923-1-palmer@sifive.com> References: <20190526010948.3923-1-palmer@sifive.com> MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.215.194 Subject: [Qemu-devel] [PULL 09/29] target/riscv: Split RVC32 and RVC64 insns into separate files X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , Palmer Dabbelt , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson This eliminates all functions in insn_trans/trans_rvc.inc.c, so the entire file can be removed. Signed-off-by: Richard Henderson Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- target/riscv/Makefile.objs | 9 +- target/riscv/insn16-32.decode | 28 ++++++ target/riscv/insn16-64.decode | 30 +++++++ target/riscv/insn16.decode | 35 +------- target/riscv/insn_trans/trans_rvc.inc.c | 115 ------------------------ target/riscv/translate.c | 1 - 6 files changed, 67 insertions(+), 151 deletions(-) create mode 100644 target/riscv/insn16-32.decode create mode 100644 target/riscv/insn16-64.decode delete mode 100644 target/riscv/insn_trans/trans_rvc.inc.c -- 2.21.0 diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs index c7a1b063edc2..b1c79bc1d172 100644 --- a/target/riscv/Makefile.objs +++ b/target/riscv/Makefile.objs @@ -5,16 +5,19 @@ DECODETREE = $(SRC_PATH)/scripts/decodetree.py decode32-y = $(SRC_PATH)/target/riscv/insn32.decode decode32-$(TARGET_RISCV64) += $(SRC_PATH)/target/riscv/insn32-64.decode +decode16-y = $(SRC_PATH)/target/riscv/insn16.decode +decode16-$(TARGET_RISCV32) += $(SRC_PATH)/target/riscv/insn16-32.decode +decode16-$(TARGET_RISCV64) += $(SRC_PATH)/target/riscv/insn16-64.decode + target/riscv/decode_insn32.inc.c: $(decode32-y) $(DECODETREE) $(call quiet-command, \ $(PYTHON) $(DECODETREE) -o $@ --static-decode decode_insn32 \ $(decode32-y), "GEN", $(TARGET_DIR)$@) -target/riscv/decode_insn16.inc.c: \ - $(SRC_PATH)/target/riscv/insn16.decode $(DECODETREE) +target/riscv/decode_insn16.inc.c: $(decode16-y) $(DECODETREE) $(call quiet-command, \ $(PYTHON) $(DECODETREE) -o $@ --static-decode decode_insn16 \ - --insnwidth 16 $<, "GEN", $(TARGET_DIR)$@) + --insnwidth 16 $(decode16-y), "GEN", $(TARGET_DIR)$@) target/riscv/translate.o: target/riscv/decode_insn32.inc.c \ target/riscv/decode_insn16.inc.c diff --git a/target/riscv/insn16-32.decode b/target/riscv/insn16-32.decode new file mode 100644 index 000000000000..0819b17028ef --- /dev/null +++ b/target/riscv/insn16-32.decode @@ -0,0 +1,28 @@ +# +# RISC-V translation routines for the RVXI Base Integer Instruction Set. +# +# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de +# Bastian Koppelmann, kbastian@mail.uni-paderborn.de +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2 or later, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. +# +# You should have received a copy of the GNU General Public License along with +# this program. If not, see . + +# *** RV32C Standard Extension (Quadrant 0) *** +flw 011 ... ... .. ... 00 @cl_w +fsw 111 ... ... .. ... 00 @cs_w + +# *** RV32C Standard Extension (Quadrant 1) *** +jal 001 ........... 01 @cj rd=1 # C.JAL + +# *** RV32C Standard Extension (Quadrant 2) *** +flw 011 . ..... ..... 10 @c_lwsp +fsw 111 . ..... ..... 10 @c_swsp diff --git a/target/riscv/insn16-64.decode b/target/riscv/insn16-64.decode new file mode 100644 index 000000000000..055859d29f61 --- /dev/null +++ b/target/riscv/insn16-64.decode @@ -0,0 +1,30 @@ +# +# RISC-V translation routines for the RVXI Base Integer Instruction Set. +# +# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de +# Bastian Koppelmann, kbastian@mail.uni-paderborn.de +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2 or later, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. +# +# You should have received a copy of the GNU General Public License along with +# this program. If not, see . + +# *** RV64C Standard Extension (Quadrant 0) *** +ld 011 ... ... .. ... 00 @cl_d +sd 111 ... ... .. ... 00 @cs_d + +# *** RV64C Standard Extension (Quadrant 1) *** +addiw 001 . ..... ..... 01 @ci +subw 100 1 11 ... 00 ... 01 @cs_2 +addw 100 1 11 ... 01 ... 01 @cs_2 + +# *** RV64C Standard Extension (Quadrant 2) *** +ld 011 . ..... ..... 10 @c_ldsp +sd 111 . ..... ..... 10 @c_sdsp diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode index 3c79edf1c996..433c0e8c6861 100644 --- a/target/riscv/insn16.decode +++ b/target/riscv/insn16.decode @@ -50,30 +50,12 @@ &u imm rd !extern &shift shamt rs1 rd !extern -# Argument sets: -&cl rs1 rd -&cl_dw uimm rs1 rd -&ciw nzuimm rd -&cs rs1 rs2 -&cs_dw uimm rs1 rs2 -&cb imm rs1 -&cr rd rs2 -&c_shift shamt rd - -&c_ld uimm rd -&c_sd uimm rs2 - -&caddi16sp_lui imm_lui imm_addi16sp rd -&cflwsp_ldsp uimm_flwsp uimm_ldsp rd -&cfswsp_sdsp uimm_fswsp uimm_sdsp rs2 # Formats 16: @cr .... ..... ..... .. &r rs2=%rs2_5 rs1=%rd %rd @ci ... . ..... ..... .. &i imm=%imm_ci rs1=%rd %rd @cl_d ... ... ... .. ... .. &i imm=%uimm_cl_d rs1=%rs1_3 rd=%rs2_3 @cl_w ... ... ... .. ... .. &i imm=%uimm_cl_w rs1=%rs1_3 rd=%rs2_3 -@cl ... ... ... .. ... .. &cl rs1=%rs1_3 rd=%rs2_3 -@cs ... ... ... .. ... .. &cs rs1=%rs1_3 rs2=%rs2_3 @cs_2 ... ... ... .. ... .. &r rs2=%rs2_3 rs1=%rs1_3 rd=%rs1_3 @cs_d ... ... ... .. ... .. &s imm=%uimm_cl_d rs1=%rs1_3 rs2=%rs2_3 @cs_w ... ... ... .. ... .. &s imm=%uimm_cl_w rs1=%rs1_3 rs2=%rs2_3 @@ -91,10 +73,6 @@ @c_addi4spn ... . ..... ..... .. &i imm=%nzuimm_ciw rs1=2 rd=%rs2_3 @c_addi16sp ... . ..... ..... .. &i imm=%imm_addi16sp rs1=2 rd=2 -@c_flwsp_ldsp ... . ..... ..... .. &cflwsp_ldsp uimm_flwsp=%uimm_6bit_lw \ - uimm_ldsp=%uimm_6bit_ld %rd -@c_fswsp_sdsp ... . ..... ..... .. &cfswsp_sdsp uimm_fswsp=%uimm_6bit_sw \ - uimm_sdsp=%uimm_6bit_sd rs2=%rs2_5 @c_shift ... . .. ... ..... .. \ &shift rd=%rs1_3 rs1=%rs1_3 shamt=%shimm_6bit @@ -103,7 +81,7 @@ @c_andi ... . .. ... ..... .. &i imm=%imm_ci rs1=%rs1_3 rd=%rs1_3 -# *** RV64C Standard Extension (Quadrant 0) *** +# *** RV32/64C Standard Extension (Quadrant 0) *** { # Opcode of all zeros is illegal; rd != 0, nzuimm == 0 is reserved. illegal 000 000 000 00 --- 00 @@ -111,14 +89,11 @@ } fld 001 ... ... .. ... 00 @cl_d lw 010 ... ... .. ... 00 @cl_w -c_flw_ld 011 --- ... -- ... 00 @cl #Note: Must parse uimm manually fsd 101 ... ... .. ... 00 @cs_d sw 110 ... ... .. ... 00 @cs_w -c_fsw_sd 111 --- ... -- ... 00 @cs #Note: Must parse uimm manually -# *** RV64C Standard Extension (Quadrant 1) *** +# *** RV32/64C Standard Extension (Quadrant 1) *** addi 000 . ..... ..... 01 @ci -c_jal_addiw 001 . ..... ..... 01 @ci #Note: parse rd and/or imm manually addi 010 . ..... ..... 01 @c_li { addi 011 . 00010 ..... 01 @c_addi16sp @@ -131,17 +106,14 @@ sub 100 0 11 ... 00 ... 01 @cs_2 xor 100 0 11 ... 01 ... 01 @cs_2 or 100 0 11 ... 10 ... 01 @cs_2 and 100 0 11 ... 11 ... 01 @cs_2 -c_subw 100 1 11 ... 00 ... 01 @cs_2 -c_addw 100 1 11 ... 01 ... 01 @cs_2 jal 101 ........... 01 @cj rd=0 # C.J beq 110 ... ... ..... 01 @cb_z bne 111 ... ... ..... 01 @cb_z -# *** RV64C Standard Extension (Quadrant 2) *** +# *** RV32/64C Standard Extension (Quadrant 2) *** slli 000 . ..... ..... 10 @c_shift2 fld 001 . ..... ..... 10 @c_ldsp lw 010 . ..... ..... 10 @c_lwsp -c_flwsp_ldsp 011 . ..... ..... 10 @c_flwsp_ldsp #C.LDSP:RV64;C.FLWSP:RV32 { jalr 100 0 ..... 00000 10 @c_jalr rd=0 # C.JR addi 100 0 ..... ..... 10 @c_mv @@ -153,4 +125,3 @@ c_flwsp_ldsp 011 . ..... ..... 10 @c_flwsp_ldsp #C.LDSP:RV64;C.FLWSP:RV32 } fsd 101 ...... ..... 10 @c_sdsp sw 110 . ..... ..... 10 @c_swsp -c_fswsp_sdsp 111 . ..... ..... 10 @c_fswsp_sdsp #C.SDSP:RV64;C.FSWSP:RV32 diff --git a/target/riscv/insn_trans/trans_rvc.inc.c b/target/riscv/insn_trans/trans_rvc.inc.c deleted file mode 100644 index 3fe6ad9d4592..000000000000 --- a/target/riscv/insn_trans/trans_rvc.inc.c +++ /dev/null @@ -1,115 +0,0 @@ -/* - * RISC-V translation routines for the RVC Compressed Instruction Set. - * - * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu - * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de - * Bastian Koppelmann, kbastian@mail.uni-paderborn.de - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2 or later, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see . - */ - -static bool trans_c_flw_ld(DisasContext *ctx, arg_c_flw_ld *a) -{ -#ifdef TARGET_RISCV32 - /* C.FLW ( RV32FC-only ) */ - REQUIRE_FPU; - REQUIRE_EXT(ctx, RVF); - - arg_i arg; - decode_insn16_extract_cl_w(ctx, &arg, ctx->opcode); - return trans_flw(ctx, &arg); -#else - /* C.LD ( RV64C/RV128C-only ) */ - arg_i arg; - decode_insn16_extract_cl_d(ctx, &arg, ctx->opcode); - return trans_ld(ctx, &arg); -#endif -} - -static bool trans_c_fsw_sd(DisasContext *ctx, arg_c_fsw_sd *a) -{ -#ifdef TARGET_RISCV32 - /* C.FSW ( RV32FC-only ) */ - REQUIRE_FPU; - REQUIRE_EXT(ctx, RVF); - - arg_s arg; - decode_insn16_extract_cs_w(ctx, &arg, ctx->opcode); - return trans_fsw(ctx, &arg); -#else - /* C.SD ( RV64C/RV128C-only ) */ - arg_s arg; - decode_insn16_extract_cs_d(ctx, &arg, ctx->opcode); - return trans_sd(ctx, &arg); -#endif -} - -static bool trans_c_jal_addiw(DisasContext *ctx, arg_c_jal_addiw *a) -{ -#ifdef TARGET_RISCV32 - /* C.JAL */ - arg_j tmp; - decode_insn16_extract_cj(ctx, &tmp, ctx->opcode); - arg_jal arg = { .rd = 1, .imm = tmp.imm }; - return trans_jal(ctx, &arg); -#else - /* C.ADDIW */ - arg_addiw arg = { .rd = a->rd, .rs1 = a->rd, .imm = a->imm }; - return trans_addiw(ctx, &arg); -#endif -} - -static bool trans_c_subw(DisasContext *ctx, arg_c_subw *a) -{ -#ifdef TARGET_RISCV64 - return trans_subw(ctx, a); -#else - return false; -#endif -} - -static bool trans_c_addw(DisasContext *ctx, arg_c_addw *a) -{ -#ifdef TARGET_RISCV64 - return trans_addw(ctx, a); -#else - return false; -#endif -} - -static bool trans_c_flwsp_ldsp(DisasContext *ctx, arg_c_flwsp_ldsp *a) -{ -#ifdef TARGET_RISCV32 - /* C.FLWSP */ - arg_flw arg_flw = { .rd = a->rd, .rs1 = 2, .imm = a->uimm_flwsp }; - return trans_flw(ctx, &arg_flw); -#else - /* C.LDSP */ - arg_ld arg_ld = { .rd = a->rd, .rs1 = 2, .imm = a->uimm_ldsp }; - return trans_ld(ctx, &arg_ld); -#endif - return false; -} - -static bool trans_c_fswsp_sdsp(DisasContext *ctx, arg_c_fswsp_sdsp *a) -{ -#ifdef TARGET_RISCV32 - /* C.FSWSP */ - arg_fsw a_fsw = { .rs1 = 2, .rs2 = a->rs2, .imm = a->uimm_fswsp }; - return trans_fsw(ctx, &a_fsw); -#else - /* C.SDSP */ - arg_sd a_sd = { .rs1 = 2, .rs2 = a->rs2, .imm = a->uimm_sdsp }; - return trans_sd(ctx, &a_sd); -#endif -} diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 4cdffb23a475..8b37e0928f50 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -707,7 +707,6 @@ static bool gen_shift(DisasContext *ctx, arg_r *a, #endif #include "decode_insn16.inc.c" -#include "insn_trans/trans_rvc.inc.c" #ifdef CONFIG_PRAGMA_DIAGNOSTIC_AVAILABLE # pragma GCC diagnostic pop From patchwork Sun May 26 01:09:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 165189 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp5441339ili; Sat, 25 May 2019 18:46:52 -0700 (PDT) X-Google-Smtp-Source: APXvYqxyY1BYAr/Az2NmACwGuT3FWZGFNguTxGvsPoaDh+MH3xAL+/8jP8vshtZhTEewAarR6y05 X-Received: by 2002:a67:e905:: with SMTP id c5mr6437773vso.97.1558835212691; Sat, 25 May 2019 18:46:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1558835212; cv=none; d=google.com; s=arc-20160816; b=MQdV/saw+VjspG7kMQlMswj6X6wjxzoQoNkUzlO6IbrPdLAaH3zwcAYoER1OV2y0ON yuXHH670k+9PdS4I07QRu2H4cJXDX/0lRD2B8vbYJaAesHzT5NlGf9NjfQi2CZ5hKkK4 bVoUQytqudwl/GdroJJZYzBF+rd5jUJSaBY7V3ILT5NlLtMS6sE3PTMHVU1NToboJzFL qMCYO96gybkELEqsmgLeoz7eAPV+6XD0JwtuuBT7uS4tf0Oy/oG3YTLZnNnKmHtRn165 HszjHQk81MBkK7epHLAt0XSzBIY/IvNXqOIv8IYtf0bbs3nMv0Pne3V1CrKVQJVoefEW fAag== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:to:from :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date; bh=OmSQFZO3wBvDnHuwPuCqP/gKDSGfC6OxGSJhMV+r43c=; b=vt8058tjKR/dtV0IcaMiiF1+XKPsR0C19tLpSUm9l9jo5O1TWNkuaJjVTKl4vHkU1O bN+BYv3onn8glgBjKHAEjKeBZ7r5QoR18p/C224oQgMuQlHDMQVejDMoxx1b4feYt4Cq a6wzNeSQ/eNVZFYnKNxZgHHFPPNPRX9vIMroHHSJAyOy/NsOZO50p09EOCThckusZkAN 2KHzu7emfdGUDeZVKgewiGMnmsMnoS/gLhhSkM1QvWfcSF6hwDkb/z/k4IMJzzfMaN0F ke4+KlWUITv6+8wQaWrELslRrZFe9Fn426SUcp6NvtFHUbEgxc+f1vsIal0cXF5ChbhG IEyQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id l23si2362253vso.71.2019.05.25.18.46.52 for (version=TLS1 cipher=AES128-SHA bits=128/128); Sat, 25 May 2019 18:46:52 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([127.0.0.1]:49411 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hUiFQ-0002qt-8f for patch@linaro.org; Sat, 25 May 2019 21:46:52 -0400 Received: from eggs.gnu.org ([209.51.188.92]:53756) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hUhxM-0003GC-Jx for qemu-devel@nongnu.org; Sat, 25 May 2019 21:28:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hUhg6-0005zu-1w for qemu-devel@nongnu.org; Sat, 25 May 2019 21:10:23 -0400 Received: from mail-pg1-f193.google.com ([209.85.215.193]:36186) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hUhg5-0005qv-A3 for qemu-devel@nongnu.org; Sat, 25 May 2019 21:10:21 -0400 Received: by mail-pg1-f193.google.com with SMTP id a3so7092626pgb.3 for ; Sat, 25 May 2019 18:10:16 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:cc:from:to; bh=OmSQFZO3wBvDnHuwPuCqP/gKDSGfC6OxGSJhMV+r43c=; b=oVU2f3jQ9M6Oo24orfHDo3nkp/qL2Bp2YAAyYXMLEO1GMKrFgY7qmI6D/8EFhCc+QO V8LUOGwEpgNrohcKWx0+SMVmh4PT8NP3/ceCw+OuLpa8/XhmNULqBVznulThRtVdQljx RK9g2jZS0XWiNxLSYVofyJcCG0nwuTzEZ4ik6Mq09vpFSAmNiIIPJHNbA1S2GCTS77PM K6jlLMZPxdhMgtmoVOZuWcI7gOUsOrq49dP6Ovz/DNsFGB6ntHGwmrqIVtlSeQvu6Z2O z/KT4kirMBi6/x1GhQOgUrONZEn361Hef8zhc8w2bMqg+j2snnTXFDzvhZxr8j6vjA9b AmBg== X-Gm-Message-State: APjAAAUjN7LABPrKpIcpIT2M0yA3uQs2R0EdxN8fxJVDQ7EFk2oJXMqu pMf+IADKCeZxU2WzsoBa2c07yg== X-Received: by 2002:aa7:9a99:: with SMTP id w25mr31312977pfi.249.1558833015176; Sat, 25 May 2019 18:10:15 -0700 (PDT) Received: from localhost ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id p90sm17592187pfa.18.2019.05.25.18.10.13 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 25 May 2019 18:10:14 -0700 (PDT) Date: Sat, 25 May 2019 18:09:29 -0700 Message-Id: <20190526010948.3923-11-palmer@sifive.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190526010948.3923-1-palmer@sifive.com> References: <20190526010948.3923-1-palmer@sifive.com> MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.215.193 Subject: [Qemu-devel] [PULL 10/29] target/riscv: Split gen_arith_imm into functional and temp X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , Palmer Dabbelt , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson The tcg_gen_fooi_tl functions have some immediate constant folding built in, which match up with some of the riscv asm builtin macros, like mv and not. Signed-off-by: Richard Henderson Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- target/riscv/insn_trans/trans_rvi.inc.c | 14 +++++++------- target/riscv/translate.c | 19 +++++++++++++++++-- 2 files changed, 24 insertions(+), 9 deletions(-) -- 2.21.0 diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c index b5a5b4a199f8..6cda078ed6ba 100644 --- a/target/riscv/insn_trans/trans_rvi.inc.c +++ b/target/riscv/insn_trans/trans_rvi.inc.c @@ -223,7 +223,7 @@ static bool trans_sd(DisasContext *ctx, arg_sd *a) static bool trans_addi(DisasContext *ctx, arg_addi *a) { - return gen_arith_imm(ctx, a, &tcg_gen_add_tl); + return gen_arith_imm_fn(ctx, a, &tcg_gen_addi_tl); } static void gen_slt(TCGv ret, TCGv s1, TCGv s2) @@ -239,25 +239,25 @@ static void gen_sltu(TCGv ret, TCGv s1, TCGv s2) static bool trans_slti(DisasContext *ctx, arg_slti *a) { - return gen_arith_imm(ctx, a, &gen_slt); + return gen_arith_imm_tl(ctx, a, &gen_slt); } static bool trans_sltiu(DisasContext *ctx, arg_sltiu *a) { - return gen_arith_imm(ctx, a, &gen_sltu); + return gen_arith_imm_tl(ctx, a, &gen_sltu); } static bool trans_xori(DisasContext *ctx, arg_xori *a) { - return gen_arith_imm(ctx, a, &tcg_gen_xor_tl); + return gen_arith_imm_fn(ctx, a, &tcg_gen_xori_tl); } static bool trans_ori(DisasContext *ctx, arg_ori *a) { - return gen_arith_imm(ctx, a, &tcg_gen_or_tl); + return gen_arith_imm_fn(ctx, a, &tcg_gen_ori_tl); } static bool trans_andi(DisasContext *ctx, arg_andi *a) { - return gen_arith_imm(ctx, a, &tcg_gen_and_tl); + return gen_arith_imm_fn(ctx, a, &tcg_gen_andi_tl); } static bool trans_slli(DisasContext *ctx, arg_slli *a) { @@ -364,7 +364,7 @@ static bool trans_and(DisasContext *ctx, arg_and *a) #ifdef TARGET_RISCV64 static bool trans_addiw(DisasContext *ctx, arg_addiw *a) { - return gen_arith_imm(ctx, a, &gen_addw); + return gen_arith_imm_tl(ctx, a, &gen_addw); } static bool trans_slliw(DisasContext *ctx, arg_slliw *a) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 8b37e0928f50..313c27b70073 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -567,8 +567,23 @@ static int ex_rvc_shifti(DisasContext *ctx, int imm) /* Include the auto-generated decoder for 32 bit insn */ #include "decode_insn32.inc.c" -static bool gen_arith_imm(DisasContext *ctx, arg_i *a, - void(*func)(TCGv, TCGv, TCGv)) +static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a, + void (*func)(TCGv, TCGv, target_long)) +{ + TCGv source1; + source1 = tcg_temp_new(); + + gen_get_gpr(source1, a->rs1); + + (*func)(source1, source1, a->imm); + + gen_set_gpr(a->rd, source1); + tcg_temp_free(source1); + return true; +} + +static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, + void (*func)(TCGv, TCGv, TCGv)) { TCGv source1, source2; source1 = tcg_temp_new(); From patchwork Sun May 26 01:09:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 165186 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp5439870ili; Sat, 25 May 2019 18:44:33 -0700 (PDT) X-Google-Smtp-Source: APXvYqzTvzHji0kHzJqj1xsqr4wN2CCJjAP6lFGNV0z/dI1edRziReKkhGmS+sGoXNFW5akoeY1z X-Received: by 2002:a67:2c51:: with SMTP id s78mr38615709vss.114.1558835072947; Sat, 25 May 2019 18:44:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1558835072; cv=none; d=google.com; s=arc-20160816; b=BEZjxF8Pl7D0dGjVlg6avwQnT10z2lmGrIShpTRcluHj89E75aZXNYJpxcs+9U3Ai5 /owYhSA9yk3sM6+VPZRnF9Fl1eiN39Oayiv0nvQ9HHsAD4mrAZA2zHXGIIJCWh2XfIHR PEaH5B5Z+I2N18ZhDxn8qoYvDLo1NbAJuDT1n08wYCHzlrNnV9ibcgDq6UGo33fh7Ijk 4DRf76Dw8xHR9Rp+E1VJHC/vmMGwAWzVKGDy/20U0SAtT8DvoeoTUl1TPS4CFvfmzFtZ k63wkFj/bRRkH2S/XpFMTY7Kb5tZiXtO1E5kKs7CbJeVNfWLgVhsgzLQWI5I4mq2XD51 cQlQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:to:from :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date; bh=wFaos8LfgCUNeyF5mCTB+VZebrOrlkwKLg03H+AhURg=; b=N1DaYEwzjtpumbndYNQ01jutWyEj68VhnhjuGxpMfQu2gUaYVtp5JBSlkNRTu5TK29 5boLM5ZsnulTYLflA+gD5Cs7lznP4ZDyqiS1F1WC9Cgwuu5Uv7zMY4YUw68M+mDZgy7m 59H2wxlb4H0cBqzQR2ST/AbY1iVK89LIiN7CnQxueJl+wXZtI2Zi5M3L39foMcOr4g1I hCs1yhV5YHaLgJE8N7lHrkt0F6C0RvYwXR3k291tgwn4lk3TguxzT4SPrRMQOAk4hPXU GRfNnGmNx0sqGHV0ynd/AOSswMf610+O+K3rqyMM2q4o9XdHuYQF1FOi45yQUaSRLB+5 JNMQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id u22si2470194vsp.51.2019.05.25.18.44.32 for (version=TLS1 cipher=AES128-SHA bits=128/128); Sat, 25 May 2019 18:44:32 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([127.0.0.1]:49359 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hUiDA-0000wz-FY for patch@linaro.org; Sat, 25 May 2019 21:44:32 -0400 Received: from eggs.gnu.org ([209.51.188.92]:53897) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hUhxM-0003HK-Ef for qemu-devel@nongnu.org; Sat, 25 May 2019 21:28:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hUhg6-0005zq-1x for qemu-devel@nongnu.org; Sat, 25 May 2019 21:10:23 -0400 Received: from mail-pf1-f178.google.com ([209.85.210.178]:41330) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hUhg4-0005rT-36 for qemu-devel@nongnu.org; Sat, 25 May 2019 21:10:21 -0400 Received: by mail-pf1-f178.google.com with SMTP id q17so2651154pfq.8 for ; Sat, 25 May 2019 18:10:18 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:cc:from:to; bh=wFaos8LfgCUNeyF5mCTB+VZebrOrlkwKLg03H+AhURg=; b=M5R0jxQjooNt1DqR/qWIA9cy/FrIrfLhS4OoeStCY8V4cpPzYGeb+KajdlnSpjOt0G u70BD0Ed1KAHQLfWeTzEQamrk/RlUtXsgEJFhWMOG/I5eAM7sieTiBbFfbzXLjmroLJX 222l8NVFnxH87eaTYevFzfab5pciWupcV4yBtOl3c44xkR+QidCd/dsq5f9X3nEFALaq +YshDsX70oFXyhYXcD9Kiy9GkehJaoCq6nifJb54v/dLNgUcAXEwDcjtW1lgpR5cbo2U RFugR3oYVTDtFqLdrWDjdgJwaXZzEYuKMtAdCOCAW6u+vAQGm9Ql1al3+2P//eG894Y2 5UqQ== X-Gm-Message-State: APjAAAV4IQ+joKbXyrAAGayxPRSUhAAMXAdWKfPJrbuTXM5VubpKmfEd L1RYr8DMGrRyZ+KxS5iXIP8qnA== X-Received: by 2002:a63:2c4a:: with SMTP id s71mr99074975pgs.343.1558833016754; Sat, 25 May 2019 18:10:16 -0700 (PDT) Received: from localhost ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id x7sm6918429pfm.82.2019.05.25.18.10.15 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 25 May 2019 18:10:15 -0700 (PDT) Date: Sat, 25 May 2019 18:09:30 -0700 Message-Id: <20190526010948.3923-12-palmer@sifive.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190526010948.3923-1-palmer@sifive.com> References: <20190526010948.3923-1-palmer@sifive.com> MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.210.178 Subject: [Qemu-devel] [PULL 11/29] target/riscv: Remove spaces from register names X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , Palmer Dabbelt , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson These extra spaces make the "-d op" dump look weird. Signed-off-by: Richard Henderson Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- target/riscv/cpu.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) -- 2.21.0 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index b7675707e0fe..6a58bc9e9d90 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -30,17 +30,17 @@ static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG"; const char * const riscv_int_regnames[] = { - "zero", "ra ", "sp ", "gp ", "tp ", "t0 ", "t1 ", "t2 ", - "s0 ", "s1 ", "a0 ", "a1 ", "a2 ", "a3 ", "a4 ", "a5 ", - "a6 ", "a7 ", "s2 ", "s3 ", "s4 ", "s5 ", "s6 ", "s7 ", - "s8 ", "s9 ", "s10 ", "s11 ", "t3 ", "t4 ", "t5 ", "t6 " + "zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", + "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", + "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", + "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6" }; const char * const riscv_fpr_regnames[] = { - "ft0 ", "ft1 ", "ft2 ", "ft3 ", "ft4 ", "ft5 ", "ft6 ", "ft7 ", - "fs0 ", "fs1 ", "fa0 ", "fa1 ", "fa2 ", "fa3 ", "fa4 ", "fa5 ", - "fa6 ", "fa7 ", "fs2 ", "fs3 ", "fs4 ", "fs5 ", "fs6 ", "fs7 ", - "fs8 ", "fs9 ", "fs10", "fs11", "ft8 ", "ft9 ", "ft10", "ft11" + "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7", + "fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5", + "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7", + "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11" }; const char * const riscv_excp_names[] = { From patchwork Sun May 26 01:09:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 165183 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp5430099ili; Sat, 25 May 2019 18:28:42 -0700 (PDT) X-Google-Smtp-Source: APXvYqyaQUM7L5JWl/MuGO4U4mpI6Exs4sR1BfFK8udNRSOgsCIP2erCHYzOIofW/hdu3KPd1qvr X-Received: by 2002:a67:ec42:: with SMTP id z2mr24396095vso.30.1558834122098; Sat, 25 May 2019 18:28:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1558834122; cv=none; d=google.com; s=arc-20160816; b=TPEHaJtiiGEqn0HZPEIvUHld59iQbSWyXQQYoWEHwp9was6M02dce0PV6/9PIQDi8R orhZ/wff/HtzkgxrbaImbU3DFwRDb9xYxR/HDwzT6RqvY59lR832ArBa3W1S/YB3qupH JUZiRtQg0fvpI2PaR7yx5vMcFhWo9ZWPdVrPAAv1yREMA1OjzHwpn9WGg8NOwqjR6K4C Ll63UVyMc05H/5spD9LLwiCau2CjDLlU8d6LKh7Tfwp+QQbmM6POqBPlmVf9F60CX1UR ZMnJhjViEX9YFsYMdm1n0wWCu87PsEg3NmiLw+xa7q6gEK6TYVP+rqD2aGyf+OPURdZJ je6g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:to:from :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date; bh=niN4BQwRj/iTWl309DyTteKW5yqNgmgqemJXUQlVM6Q=; b=o+p5X20hUjg2UMYle6/eQYT1BJdAwZG0U94cERZQnx+SoM077JByvmwIV39GSEQvgr q3mG9d4fR+ENY0S2UzMPZtWfyS1WT6tie3E1SImwwQS0DnZHT2GDNkS3rRfL4xAFloCX jbsx6ZPUVoM9g302uhPBC9Xub+3fOgaqhgPdqbM4vqXnmgc64r0BnUNmV+rmhSdP65L7 zW5zUkDW9Ry8HBBEFWNjuvQ23WqsQDGIGuUEpeDhbiVnrzQe8b0uxAjYM/gTxAbXSFzX MR27lGTBnVLhdKNTdt0C/4TFAwjvx+5SQXewNS/SHsHrse/+8v38u01N99EWuquRieOb v2mg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id j4si2387855vso.419.2019.05.25.18.28.41 for (version=TLS1 cipher=AES128-SHA bits=128/128); Sat, 25 May 2019 18:28:42 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([127.0.0.1]:49062 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hUhxp-0003gq-Gy for patch@linaro.org; Sat, 25 May 2019 21:28:41 -0400 Received: from eggs.gnu.org ([209.51.188.92]:53938) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hUhxC-0003Hg-Hv for qemu-devel@nongnu.org; Sat, 25 May 2019 21:28:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hUhgN-0006UX-Un for qemu-devel@nongnu.org; Sat, 25 May 2019 21:10:40 -0400 Received: from mail-pf1-f173.google.com ([209.85.210.173]:44180) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hUhgN-0006U6-OK for qemu-devel@nongnu.org; Sat, 25 May 2019 21:10:39 -0400 Received: by mail-pf1-f173.google.com with SMTP id g9so7487399pfo.11 for ; Sat, 25 May 2019 18:10:39 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:cc:from:to; bh=niN4BQwRj/iTWl309DyTteKW5yqNgmgqemJXUQlVM6Q=; b=tfB02dBStjAMSB1j+6UK3wyLDCfe9xWewMIHl5uElucL5MQk5d3LyP2/em1ehjIHCz SKxkHgD9Q8956fpKmiUgg/AbngXsu0zo0+YabFg9VzCEWQSmKpAVKh9mZpJebsKzZAPG DOG8n4M+KVtp+ydPhPQZURngDCcKnb6aRM5btjLKDOkAjze8HIUgb2tD9okgJGAQQioA 8PgjtOXVL4Azgv0arRS1KxTwgoO5feFfnlqZ2uQR8xVTNiG8pExqNyXaVLnquHRqL8kG x1Ijmp+kJue/Lh/0DD8Rwe7LMxeGgwadkq5bBBGoIIp6CuRvoDdTnqeVJDF0HcU8ZBQZ gL7Q== X-Gm-Message-State: APjAAAWMT0i09lT5vonYnUhS97j21YgfialrumGMcRQpWlZK7phqpOss wNEM7ecCTe0uIY5odjU19S3BIA== X-Received: by 2002:a63:1224:: with SMTP id h36mr24384550pgl.9.1558833038226; Sat, 25 May 2019 18:10:38 -0700 (PDT) Received: from localhost ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id a11sm6828548pff.128.2019.05.25.18.10.37 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 25 May 2019 18:10:37 -0700 (PDT) Date: Sat, 25 May 2019 18:09:46 -0700 Message-Id: <20190526010948.3923-28-palmer@sifive.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190526010948.3923-1-palmer@sifive.com> References: <20190526010948.3923-1-palmer@sifive.com> MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.210.173 Subject: [Qemu-devel] [PULL 27/29] target/riscv: Add checks for several RVC reserved operands X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , Palmer Dabbelt , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson C.ADDI16SP, C.LWSP, C.JR, C.ADDIW, C.LDSP all have reserved operands that were not diagnosed. Signed-off-by: Richard Henderson Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- target/riscv/insn16-64.decode | 10 ++++++++-- target/riscv/insn16.decode | 7 ++++++- 2 files changed, 14 insertions(+), 3 deletions(-) -- 2.21.0 diff --git a/target/riscv/insn16-64.decode b/target/riscv/insn16-64.decode index 055859d29f61..672e1e916f6b 100644 --- a/target/riscv/insn16-64.decode +++ b/target/riscv/insn16-64.decode @@ -21,10 +21,16 @@ ld 011 ... ... .. ... 00 @cl_d sd 111 ... ... .. ... 00 @cs_d # *** RV64C Standard Extension (Quadrant 1) *** -addiw 001 . ..... ..... 01 @ci +{ + illegal 001 - 00000 ----- 01 # c.addiw, RES rd=0 + addiw 001 . ..... ..... 01 @ci +} subw 100 1 11 ... 00 ... 01 @cs_2 addw 100 1 11 ... 01 ... 01 @cs_2 # *** RV64C Standard Extension (Quadrant 2) *** -ld 011 . ..... ..... 10 @c_ldsp +{ + illegal 011 - 00000 ----- 10 # c.ldsp, RES rd=0 + ld 011 . ..... ..... 10 @c_ldsp +} sd 111 . ..... ..... 10 @c_sdsp diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode index 433c0e8c6861..1cb93876fe0f 100644 --- a/target/riscv/insn16.decode +++ b/target/riscv/insn16.decode @@ -96,6 +96,7 @@ sw 110 ... ... .. ... 00 @cs_w addi 000 . ..... ..... 01 @ci addi 010 . ..... ..... 01 @c_li { + illegal 011 0 ----- 00000 01 # c.addi16sp and c.lui, RES nzimm=0 addi 011 . 00010 ..... 01 @c_addi16sp lui 011 . ..... ..... 01 @c_lui } @@ -113,8 +114,12 @@ bne 111 ... ... ..... 01 @cb_z # *** RV32/64C Standard Extension (Quadrant 2) *** slli 000 . ..... ..... 10 @c_shift2 fld 001 . ..... ..... 10 @c_ldsp -lw 010 . ..... ..... 10 @c_lwsp { + illegal 010 - 00000 ----- 10 # c.lwsp, RES rd=0 + lw 010 . ..... ..... 10 @c_lwsp +} +{ + illegal 100 0 00000 00000 10 # c.jr, RES rs1=0 jalr 100 0 ..... 00000 10 @c_jalr rd=0 # C.JR addi 100 0 ..... ..... 10 @c_mv }