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[176.184.52.81]) by smtp.gmail.com with ESMTPSA id f16-20020adffcd0000000b002d5a8d8442asm14561130wrs.37.2023.04.05.03.08.56 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 05 Apr 2023 03:08:59 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-arm@nongnu.org, Peter Maydell , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 1/2] target/arm: Remove KVM AArch32 CPU definitions Date: Wed, 5 Apr 2023 12:08:47 +0200 Message-Id: <20230405100848.76145-2-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230405100848.76145-1-philmd@linaro.org> References: <20230405100848.76145-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=philmd@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Missed in commit 80485d88f9 ("target/arm: Restrict v7A TCG cpus to TCG accel"). Signed-off-by: Philippe Mathieu-Daudé --- target/arm/kvm-consts.h | 9 +++------ target/arm/cpu_tcg.c | 2 -- 2 files changed, 3 insertions(+), 8 deletions(-) diff --git a/target/arm/kvm-consts.h b/target/arm/kvm-consts.h index 09967ec5e6..7c6adc14f6 100644 --- a/target/arm/kvm-consts.h +++ b/target/arm/kvm-consts.h @@ -124,13 +124,10 @@ MISMATCH_CHECK(QEMU_PSCI_RET_INTERNAL_FAILURE, PSCI_RET_INTERNAL_FAILURE); MISMATCH_CHECK(QEMU_PSCI_RET_NOT_PRESENT, PSCI_RET_NOT_PRESENT); MISMATCH_CHECK(QEMU_PSCI_RET_DISABLED, PSCI_RET_DISABLED); -/* Note that KVM uses overlapping values for AArch32 and AArch64 - * target CPU numbers. AArch32 targets: +/* + * Note that KVM uses overlapping values for AArch32 and AArch64 + * target CPU numbers. AArch64 targets: */ -#define QEMU_KVM_ARM_TARGET_CORTEX_A15 0 -#define QEMU_KVM_ARM_TARGET_CORTEX_A7 1 - -/* AArch64 targets: */ #define QEMU_KVM_ARM_TARGET_AEM_V8 0 #define QEMU_KVM_ARM_TARGET_FOUNDATION_V8 1 #define QEMU_KVM_ARM_TARGET_CORTEX_A57 2 diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index df0c45e523..1911d7ec47 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -546,7 +546,6 @@ static void cortex_a7_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_EL2); set_feature(&cpu->env, ARM_FEATURE_EL3); set_feature(&cpu->env, ARM_FEATURE_PMU); - cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7; cpu->midr = 0x410fc075; cpu->reset_fpsid = 0x41023075; cpu->isar.mvfr0 = 0x10110222; @@ -595,7 +594,6 @@ static void cortex_a15_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_EL2); set_feature(&cpu->env, ARM_FEATURE_EL3); set_feature(&cpu->env, ARM_FEATURE_PMU); - cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15; /* r4p0 cpu, not requiring expensive tlb flush errata */ cpu->midr = 0x414fc0f0; cpu->revidr = 0x0; From patchwork Wed Apr 5 10:08:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 670302 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d08:0:0:0:0:0 with SMTP id z8csp183075wrt; Wed, 5 Apr 2023 03:09:33 -0700 (PDT) X-Google-Smtp-Source: AKy350ZXrVbk1Grngynp5A6pHG1rpVCvbFTkwJsH46mDooa0pNsnBVCSoO9lBcybVdjgSHkCixxh X-Received: by 2002:ad4:5b87:0:b0:5e2:1381:6105 with SMTP id 7-20020ad45b87000000b005e213816105mr7638344qvp.18.1680689373395; Wed, 05 Apr 2023 03:09:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680689373; cv=none; d=google.com; s=arc-20160816; b=ZOJn/alwtWiRxGyTlXyPbBn+Ceb1duS8zU0kzLrw3M3hTjnK5fEWLqQaKII4aog5KF 1MSxas79UoKYUniy2BS7jKifPwPS/ujfRjOiYTtVdybIwN8Wvinz29y8Twqh989v9JwV 0aZPSeqGhxL5ScUF/pvVBz0V5azHSCdr4+dqmc3OmQjL5m2fflpAZCLOwFcVfCaORRhz YPu+XPDSKaxEeyLKEb60ZVv2hGaDzTEesp7wsfDy921wBDBdpPxO37ttCP64o9xr3cxZ GOccJoFEARBoyaPzEEndCExC+HWp7zvl3+l2V/5emLdYtM2qNjhnl5aa58hAwkwMFweX +DbQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=hOIUAejMDgPGNri6CTMX+NYmgz2rO96F3gJmXNOLJxs=; b=Fih3RYUqn7HrXbj6luahAZcRhbqKrhHTM0wzwRJe/qmV0ddibzzFmA+cprcBcrsVvk Yq4eJOEM50uMarY4nM+wBZYG8znHo5mozjILdbYeqhSk5FMaGCmEKRvDq6jczzobitew rCVeYYNzGlcpZoBZhmRBTpVBzclrvq1wNlwGRb3jkFmBFYOHnt4KN0NaX7b4dBmYfYpi DhLOcN18wMSqcYECfLa0xl46+R5QAGExdB/U7dhb9YuelVVpAbxKQVTDevM23K8KGGtP LpXklqtZbuLHwjqhujl+pGZp0HyZFH8pLuf7R8mEvx6Ee7YnlgOIUiEF00o4EzZfDX0s X45Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="S/sJ8y4f"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.184.52.81]) by smtp.gmail.com with ESMTPSA id m19-20020a7bce13000000b003ee1acdb036sm1700160wmc.17.2023.04.05.03.09.04 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 05 Apr 2023 03:09:06 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-arm@nongnu.org, Peter Maydell , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 2/2] hw/arm/virt: Restrict Cortex-A7 check to TCG Date: Wed, 5 Apr 2023 12:08:48 +0200 Message-Id: <20230405100848.76145-3-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230405100848.76145-1-philmd@linaro.org> References: <20230405100848.76145-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The Cortex-A7 core is only available when TCG is enabled (see commit 80485d88f9 "target/arm: Restrict v7A TCG cpus to TCG accel"). Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/virt.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index ac626b3bef..1fe39c6683 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -204,7 +204,9 @@ static const int a15irqmap[] = { }; static const char *valid_cpus[] = { +#ifdef CONFIG_TCG ARM_CPU_TYPE_NAME("cortex-a7"), +#endif ARM_CPU_TYPE_NAME("cortex-a15"), ARM_CPU_TYPE_NAME("cortex-a35"), ARM_CPU_TYPE_NAME("cortex-a53"),