From patchwork Tue Apr 4 23:56:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jessica Zhang X-Patchwork-Id: 670464 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 78563C761A6 for ; Tue, 4 Apr 2023 23:56:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236647AbjDDX4z (ORCPT ); Tue, 4 Apr 2023 19:56:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60912 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236661AbjDDX4w (ORCPT ); Tue, 4 Apr 2023 19:56:52 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E988C44A3 for ; Tue, 4 Apr 2023 16:56:50 -0700 (PDT) Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 334Nimwt023903; Tue, 4 Apr 2023 23:56:43 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : date : subject : mime-version : content-type : content-transfer-encoding : message-id : references : in-reply-to : to : cc; s=qcppdkim1; bh=YfBpptkCkCXkMvYpslBde/rTOT8AjTZ/UPveNTU7WTg=; b=DAmNr9BqEmnDbiXn/V7EWPJT46WHW5LUjUQOfJ1Rvs5MhPF0rih7LdKcCXEOtm1IYjXv vU30lzy8NOwgOGJGWiZqfgd3npHCmmqOdKAmdh6dIv4xpy01tAtIZXA+tweMdGrGKMS9 5QVgTednrWybdc4T+fDcvY5U4UxT9gOXze4bFTKIziw+pjdb8Xqy2laOew03o1/aR1Gg e5K6SiK63VWD8rcSJHxjA0T5ssVbG/bsTy0GJmvKWmnp4f8Y+gWLH5c6N6gRrXjTB4T9 G0wBqcGcccbcMW0Pj7nGzYuHTEkmsOYK+LLGMOJyMqNp20gSfBObYGjXDo0zSnr2S4I9 JA== Received: from nasanppmta02.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3prppuh4s6-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 04 Apr 2023 23:56:43 +0000 Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 334NugrN022576 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 4 Apr 2023 23:56:42 GMT Received: from jesszhan-linux.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Tue, 4 Apr 2023 16:56:42 -0700 From: Jessica Zhang Date: Tue, 4 Apr 2023 16:56:13 -0700 Subject: [PATCH v3 1/6] drm/msm: Add MSM-specific DSC helper methods MIME-Version: 1.0 Message-ID: <20230329-rfc-msm-dsc-helper-v3-1-6bec0d277a83@quicinc.com> References: <20230329-rfc-msm-dsc-helper-v3-0-6bec0d277a83@quicinc.com> In-Reply-To: <20230329-rfc-msm-dsc-helper-v3-0-6bec0d277a83@quicinc.com> To: CC: Marijn Suijten , Konrad Dybcio , Daniel Vetter , Rob Clark , Abhinav Kumar , "Dmitry Baryshkov" , Sean Paul , , , "Jessica Zhang" X-Mailer: b4 0.13-dev-00303 X-Developer-Signature: v=1; a=ed25519-sha256; t=1680652601; l=6218; i=quic_jesszhan@quicinc.com; s=20230329; h=from:subject:message-id; bh=20I+Sr/QtdAmk7Pm6M9KB6TaVI2G3rBb0RYY8TRUsno=; b=lMvABP/Ltli0I3bkE/MQ+GO3oRa0Ua1UXKzHG0ibT0qB7k5UZOjv8JzNFVnL4hdrZ7m4EdkTa BpMDCxhhTWSCNkwu0j6/DBOsmWZdEsJSfVV3lIsT4Pg1MkzMSS/bNOq X-Developer-Key: i=quic_jesszhan@quicinc.com; a=ed25519; pk=gAUCgHZ6wTJOzQa3U0GfeCDH7iZLlqIEPo4rrjfDpWE= X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 9iBoR6aSaTEUoFaZvPv4_zNE7uYm3EBy X-Proofpoint-ORIG-GUID: 9iBoR6aSaTEUoFaZvPv4_zNE7uYm3EBy X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-04-04_12,2023-04-04_05,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 lowpriorityscore=0 clxscore=1015 malwarescore=0 suspectscore=0 adultscore=0 mlxlogscore=650 phishscore=0 bulkscore=0 priorityscore=1501 mlxscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2304040217 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Introduce MSM-specific DSC helper methods, as some calculations are common between DP and DSC. Changes in v2: - Moved files up to msm/ directory - Dropped get_comp_ratio() helper - Used drm_int2fixp() to convert to integers to fp - Style changes to improve readability - Dropped unused bpp variable in msm_dsc_get_dce_bytes_per_line() - Changed msm_dsc_get_slice_per_intf() to a static inline method - Dropped last division step of msm_dsc_get_pclk_per_line() and changed method name accordingly - Changed DSC_BPP macro to drm_dsc_get_bpp_int() helper method - Fixed some math issues caused by passing in incorrect types to drm_fixed methods in get_bytes_per_soft_slice() Changes in v3: - Dropped src_bpp parameter from all methods -- src_bpp can be calculated as dsc->bits_per_component * 3 - Dropped intf_width parameter from get_bytes_per_soft_slice() - Moved dsc->bits_per_component to numerator calculation in get_bytes_per_soft_slice() - Renamed msm_dsc_get_uncompressed_pclk_per_line to *_get_uncompressed_pclk_per_intf() - Removed dsc->slice_width check from msm_dsc_get_uncompressed_pclk_per_intf() - Made get_bytes_per_soft_slice() a public method (this will be called later to help calculate DP pclk params) - Added documentation in comments - Moved extra_eol_bytes math out of msm_dsc_get_eol_byte_num() and renamed msm_dsc_get_eol_byte_num to *_get_bytes_per_intf. Signed-off-by: Jessica Zhang --- drivers/gpu/drm/msm/Makefile | 1 + drivers/gpu/drm/msm/msm_dsc_helper.c | 47 ++++++++++++++++++++++++ drivers/gpu/drm/msm/msm_dsc_helper.h | 70 ++++++++++++++++++++++++++++++++++++ 3 files changed, 118 insertions(+) diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile index 7274c41228ed..b814fc80e2d5 100644 --- a/drivers/gpu/drm/msm/Makefile +++ b/drivers/gpu/drm/msm/Makefile @@ -94,6 +94,7 @@ msm-y += \ msm_atomic_tracepoints.o \ msm_debugfs.o \ msm_drv.o \ + msm_dsc_helper.o \ msm_fb.o \ msm_fence.o \ msm_gem.o \ diff --git a/drivers/gpu/drm/msm/msm_dsc_helper.c b/drivers/gpu/drm/msm/msm_dsc_helper.c new file mode 100644 index 000000000000..c8c530211f50 --- /dev/null +++ b/drivers/gpu/drm/msm/msm_dsc_helper.c @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved + */ + +#include +#include +#include + +#include "msm_drv.h" +#include "msm_dsc_helper.h" + +s64 get_bytes_per_soft_slice(struct drm_dsc_config *dsc) +{ + int bpp = msm_dsc_get_bpp_int(dsc); + s64 numerator_fp, denominator_fp; + s64 comp_ratio_fp = drm_fixp_from_fraction(dsc->bits_per_component * 3, bpp); + + numerator_fp = drm_int2fixp(dsc->slice_width * 3 * dsc->bits_per_component); + denominator_fp = drm_fixp_mul(comp_ratio_fp, drm_int2fixp(8)); + + return drm_fixp_div(numerator_fp, denominator_fp); +} + +u32 msm_dsc_get_bytes_per_intf(struct drm_dsc_config *dsc, int intf_width) +{ + u32 bytes_per_soft_slice, bytes_per_intf; + s64 bytes_per_soft_slice_fp; + int slice_per_intf = msm_dsc_get_slice_per_intf(dsc, intf_width); + + bytes_per_soft_slice_fp = get_bytes_per_soft_slice(dsc); + bytes_per_soft_slice = drm_fixp2int_ceil(bytes_per_soft_slice_fp); + + bytes_per_intf = bytes_per_soft_slice * slice_per_intf; + + return bytes_per_intf; +} + +int msm_dsc_get_uncompressed_pclk_per_intf(struct drm_dsc_config *dsc) +{ + s64 data_width; + + data_width = drm_fixp_mul(drm_int2fixp(dsc->slice_count), + get_bytes_per_soft_slice(dsc)); + + return drm_fixp2int_ceil(data_width); +} diff --git a/drivers/gpu/drm/msm/msm_dsc_helper.h b/drivers/gpu/drm/msm/msm_dsc_helper.h new file mode 100644 index 000000000000..5ee972eb247c --- /dev/null +++ b/drivers/gpu/drm/msm/msm_dsc_helper.h @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved + */ + +#ifndef MSM_DSC_HELPER_H_ +#define MSM_DSC_HELPER_H_ + +#include +#include + +/* + * Helper methods for MSM specific DSC calculations that are common between timing engine, + * DSI, and DP. + */ + +/** + * msm_dsc_get_bpp_int - get bits per pixel integer value + * @dsc: Pointer to drm dsc config struct + */ +static inline int msm_dsc_get_bpp_int(struct drm_dsc_config *dsc) +{ + WARN_ON_ONCE(dsc->bits_per_pixel & 0xf); + return dsc->bits_per_pixel >> 4; +} + +/** + * msm_dsc_get_slice_per_intf - get number of slices per interface + * @dsc: Pointer to drm dsc config struct + * @intf_width: interface width + */ +static inline int msm_dsc_get_slice_per_intf(struct drm_dsc_config *dsc, int intf_width) +{ + return DIV_ROUND_UP(intf_width, dsc->slice_width); +} + +/** + * msm_dsc_get_dce_bytes_per_line - get bytes per line to help calculate data width + * when configuring the timing engine + * @dsc: Pointer to drm dsc config struct + * @intf_width: interface width + */ +static inline u32 msm_dsc_get_dce_bytes_per_line(struct drm_dsc_config *dsc, int intf_width) +{ + return DIV_ROUND_UP(msm_dsc_get_bpp_int(dsc) * intf_width, 8); +} + +/** + * get_bytes_per_soft_slice - get size of each soft slice for dsc + * @dsc: Pointer to drm dsc config struct + */ +s64 get_bytes_per_soft_slice(struct drm_dsc_config *dsc); + +/** + * msm_dsc_get_bytes_per_intf - get total bytes per interface + * @dsc: Pointer to drm dsc config struct + * @intf_width: interface width + */ +u32 msm_dsc_get_bytes_per_intf(struct drm_dsc_config *dsc, int intf_width); + +/** + * msm_dsc_get_uncompressed_pclk_per_intf - Calculate uncompressed pclk per line. + * @dsc: Pointer to drm dsc config struct + * + * Note: This value will then be passed along to DSI and DP to calculate pclk_per_intf. + * This is because DSI and DP divide the uncompressed pclk_per_intf by different + * values depending on if widebus is enabled. + */ +int msm_dsc_get_uncompressed_pclk_per_intf(struct drm_dsc_config *dsc); +#endif /* MSM_DSC_HELPER_H_ */ From patchwork Tue Apr 4 23:56:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jessica Zhang X-Patchwork-Id: 670087 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8897CC77B6E for ; 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Tue, 4 Apr 2023 16:56:42 -0700 From: Jessica Zhang Date: Tue, 4 Apr 2023 16:56:14 -0700 Subject: [PATCH v3 2/6] drm/msm/dpu: Use DRM DSC helper for det_thresh_flatness MIME-Version: 1.0 Message-ID: <20230329-rfc-msm-dsc-helper-v3-2-6bec0d277a83@quicinc.com> References: <20230329-rfc-msm-dsc-helper-v3-0-6bec0d277a83@quicinc.com> In-Reply-To: <20230329-rfc-msm-dsc-helper-v3-0-6bec0d277a83@quicinc.com> To: CC: Marijn Suijten , Konrad Dybcio , Daniel Vetter , Rob Clark , Abhinav Kumar , "Dmitry Baryshkov" , Sean Paul , , , "Jessica Zhang" X-Mailer: b4 0.13-dev-00303 X-Developer-Signature: v=1; a=ed25519-sha256; t=1680652601; l=1282; i=quic_jesszhan@quicinc.com; s=20230329; h=from:subject:message-id; bh=miwaTqKJX3w3HDahg7jImz20J6rL9IpfTJm6EPOS6AI=; b=Qx28JE4tJBMyw0ppp+CxWRhmv89wkEH6WteWGe0LqPGDPaoZgdnKuROowHdqi2o5Bw26ka299 SNmdCCSNd3yBs+PNo9cpWYc/mpxORmwa93HI0y5Yt0xVBWbGF03J2VZ X-Developer-Key: i=quic_jesszhan@quicinc.com; a=ed25519; pk=gAUCgHZ6wTJOzQa3U0GfeCDH7iZLlqIEPo4rrjfDpWE= X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: MYEUanb3O6-PjSplZVnSOMe_zA310MWu X-Proofpoint-GUID: MYEUanb3O6-PjSplZVnSOMe_zA310MWu X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-04-04_12,2023-04-04_05,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 lowpriorityscore=0 mlxlogscore=713 bulkscore=0 impostorscore=0 spamscore=0 clxscore=1015 adultscore=0 mlxscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2304040217 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Use the DRM DSC helper for det_thresh_flatness to match downstream implementation and the DSC spec. Changes in V2: - Added a Fixes tag Fixes: c110cfd1753e ("drm/msm/disp/dpu1: Add support for DSC") Signed-off-by: Jessica Zhang Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c index 619926da1441..b952f7d2b7f5 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c @@ -3,6 +3,8 @@ * Copyright (c) 2020-2022, Linaro Limited */ +#include + #include "dpu_kms.h" #include "dpu_hw_catalog.h" #include "dpu_hwio.h" @@ -102,7 +104,7 @@ static void dpu_hw_dsc_config(struct dpu_hw_dsc *hw_dsc, data |= dsc->final_offset; DPU_REG_WRITE(c, DSC_DSC_OFFSET, data); - det_thresh_flatness = 7 + 2 * (dsc->bits_per_component - 8); + det_thresh_flatness = drm_dsc_calculate_flatness_det_thresh(dsc); data = det_thresh_flatness << 10; data |= dsc->flatness_max_qp << 5; data |= dsc->flatness_min_qp; From patchwork Tue Apr 4 23:56:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jessica Zhang X-Patchwork-Id: 670466 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E1604C761A6 for ; Tue, 4 Apr 2023 23:56:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236663AbjDDX4w (ORCPT ); Tue, 4 Apr 2023 19:56:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60876 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236551AbjDDX4v (ORCPT ); Tue, 4 Apr 2023 19:56:51 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 825CE4224 for ; Tue, 4 Apr 2023 16:56:50 -0700 (PDT) Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 334Lg9FE029884; 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Tue, 4 Apr 2023 23:56:43 GMT Received: from jesszhan-linux.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Tue, 4 Apr 2023 16:56:42 -0700 From: Jessica Zhang Date: Tue, 4 Apr 2023 16:56:15 -0700 Subject: [PATCH v3 3/6] drm/msm/dpu: Fix slice_last_group_size calculation MIME-Version: 1.0 Message-ID: <20230329-rfc-msm-dsc-helper-v3-3-6bec0d277a83@quicinc.com> References: <20230329-rfc-msm-dsc-helper-v3-0-6bec0d277a83@quicinc.com> In-Reply-To: <20230329-rfc-msm-dsc-helper-v3-0-6bec0d277a83@quicinc.com> To: CC: Marijn Suijten , Konrad Dybcio , Daniel Vetter , Rob Clark , Abhinav Kumar , "Dmitry Baryshkov" , Sean Paul , , , "Jessica Zhang" X-Mailer: b4 0.13-dev-00303 X-Developer-Signature: v=1; a=ed25519-sha256; t=1680652601; l=1191; i=quic_jesszhan@quicinc.com; s=20230329; h=from:subject:message-id; bh=626UczrBvbBXHAzAtCtgR6FxGBdQQBWmOE/OfL7f5Vw=; b=hdw+qnZb11dWIGFOj8laB4OXit+w7SsZCY2c2LJwHAVY/O+fjsldvwvaiBX0Y3iosrKpySfJV N8oQk13GAaRBJIfAbn98Zp+aE0Z3rFbJWlOAqH4+BXWTQAVL4Jizar2 X-Developer-Key: i=quic_jesszhan@quicinc.com; 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Changes in v3: - Reworded slice_last_group_size calculation to `(dsc->slice_width + 2) % 3` Fixes: c110cfd1753e ("drm/msm/disp/dpu1: Add support for DSC") Signed-off-by: Jessica Zhang --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c index b952f7d2b7f5..ff1c8f92fb20 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c @@ -56,9 +56,10 @@ static void dpu_hw_dsc_config(struct dpu_hw_dsc *hw_dsc, if (is_cmd_mode) initial_lines += 1; - slice_last_group_size = 3 - (dsc->slice_width % 3); + slice_last_group_size = (dsc->slice_width + 2) % 3; + data = (initial_lines << 20); - data |= ((slice_last_group_size - 1) << 18); + data |= (slice_last_group_size << 18); /* bpp is 6.4 format, 4 LSBs bits are for fractional part */ data |= (dsc->bits_per_pixel << 8); data |= (dsc->block_pred_enable << 7); From patchwork Tue Apr 4 23:56:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jessica Zhang X-Patchwork-Id: 670465 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AEE13C6FD1D for ; Tue, 4 Apr 2023 23:56:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236551AbjDDX4y (ORCPT ); Tue, 4 Apr 2023 19:56:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60896 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236655AbjDDX4w (ORCPT ); Tue, 4 Apr 2023 19:56:52 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8012340E0 for ; Tue, 4 Apr 2023 16:56:50 -0700 (PDT) Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 334NEHfF002118; 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Tue, 4 Apr 2023 23:56:43 GMT Received: from jesszhan-linux.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Tue, 4 Apr 2023 16:56:43 -0700 From: Jessica Zhang Date: Tue, 4 Apr 2023 16:56:16 -0700 Subject: [PATCH v3 4/6] drm/msm/dsi: Use MSM and DRM DSC helper methods MIME-Version: 1.0 Message-ID: <20230329-rfc-msm-dsc-helper-v3-4-6bec0d277a83@quicinc.com> References: <20230329-rfc-msm-dsc-helper-v3-0-6bec0d277a83@quicinc.com> In-Reply-To: <20230329-rfc-msm-dsc-helper-v3-0-6bec0d277a83@quicinc.com> To: CC: Marijn Suijten , Konrad Dybcio , Daniel Vetter , Rob Clark , Abhinav Kumar , "Dmitry Baryshkov" , Sean Paul , , , "Jessica Zhang" X-Mailer: b4 0.13-dev-00303 X-Developer-Signature: v=1; a=ed25519-sha256; t=1680652601; l=2639; i=quic_jesszhan@quicinc.com; s=20230329; h=from:subject:message-id; bh=dH3XUkqf2TvirMUJs2NzdNoHIMpmtMKoXzWAeCxfQ0Y=; b=lTO6EsQhH/i1i21ZUxiGbAxVGmv4j72FgZgVkwnFEHSRuBnpY1dXSRHuJQyruzN0nHxPokfEU AT7z2PNGXm3BDzjam7Zt3YhYcdB2Lq5Noc1pf29+dg36oOvpvyuyccg X-Developer-Key: i=quic_jesszhan@quicinc.com; a=ed25519; pk=gAUCgHZ6wTJOzQa3U0GfeCDH7iZLlqIEPo4rrjfDpWE= X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: iGtRlQmgrioeCJCo1QYhz57fq0O0KqBC X-Proofpoint-ORIG-GUID: iGtRlQmgrioeCJCo1QYhz57fq0O0KqBC X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-04-04_12,2023-04-04_05,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 suspectscore=0 malwarescore=0 phishscore=0 priorityscore=1501 bulkscore=0 mlxlogscore=770 adultscore=0 lowpriorityscore=0 mlxscore=0 spamscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2304040217 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Use MSM and DRM DSC helper methods to configure DSC for DSI. Changes in V2: - *_calculate_initial_scale_value --> *_set_initial_scale_value - Split pkt_per_line and eol_byte_num changes to a separate patch - Moved pclk_per_line calculation to hdisplay adjustment in `if (dsc)` block of dsi_update_dsc_timing() Changes in v3: - Split pclk_per_intf calculation into a separate patch - Added slice_width check to dsi_timing_setup - Used MSM DSC helper to calculate total_bytes_per_intf Signed-off-by: Jessica Zhang --- drivers/gpu/drm/msm/dsi/dsi_host.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index 74d38f90398a..6a6218a9655f 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -28,6 +28,7 @@ #include "dsi.xml.h" #include "sfpb.xml.h" #include "dsi_cfg.h" +#include "msm_dsc_helper.h" #include "msm_kms.h" #include "msm_gem.h" #include "phy/dsi_phy.h" @@ -848,7 +849,7 @@ static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mod /* first calculate dsc parameters and then program * compress mode registers */ - slice_per_intf = DIV_ROUND_UP(hdisplay, dsc->slice_width); + slice_per_intf = msm_dsc_get_slice_per_intf(dsc, hdisplay); /* * If slice_count is greater than slice_per_intf @@ -858,7 +859,7 @@ static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mod if (dsc->slice_count > slice_per_intf) dsc->slice_count = 1; - total_bytes_per_intf = dsc->slice_chunk_size * slice_per_intf; + total_bytes_per_intf = msm_dsc_get_bytes_per_intf(dsc, hdisplay); eol_byte_num = total_bytes_per_intf % 3; pkt_per_line = slice_per_intf / dsc->slice_count; @@ -936,6 +937,12 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi) return; } + if (!dsc->slice_width || (mode->hdisplay < dsc->slice_width)) { + pr_err("DSI: invalid slice width %d (pic_width: %d)\n", + dsc->slice_width, mode->hdisplay); + return; + } + dsc->pic_width = mode->hdisplay; dsc->pic_height = mode->vdisplay; DBG("Mode %dx%d\n", dsc->pic_width, dsc->pic_height); @@ -1759,7 +1766,7 @@ static int dsi_populate_dsc_params(struct msm_dsi_host *msm_host, struct drm_dsc return ret; } - dsc->initial_scale_value = 32; + drm_dsc_set_initial_scale_value(dsc); dsc->line_buf_depth = dsc->bits_per_component + 1; return drm_dsc_compute_rc_parameters(dsc); From patchwork Tue Apr 4 23:56:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jessica Zhang X-Patchwork-Id: 670088 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C9D94C77B6C for ; Tue, 4 Apr 2023 23:56:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236656AbjDDX44 (ORCPT ); Tue, 4 Apr 2023 19:56:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60916 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236662AbjDDX4w (ORCPT ); Tue, 4 Apr 2023 19:56:52 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 431A844AB for ; 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Tue, 04 Apr 2023 23:56:44 +0000 Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 334NuhEU015907 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 4 Apr 2023 23:56:43 GMT Received: from jesszhan-linux.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Tue, 4 Apr 2023 16:56:43 -0700 From: Jessica Zhang Date: Tue, 4 Apr 2023 16:56:17 -0700 Subject: [PATCH v3 5/6] drm/msm/dsi: update hdisplay calculation for dsi_timing_setup MIME-Version: 1.0 Message-ID: <20230329-rfc-msm-dsc-helper-v3-5-6bec0d277a83@quicinc.com> References: <20230329-rfc-msm-dsc-helper-v3-0-6bec0d277a83@quicinc.com> In-Reply-To: <20230329-rfc-msm-dsc-helper-v3-0-6bec0d277a83@quicinc.com> To: CC: Marijn Suijten , Konrad Dybcio , Daniel Vetter , Rob Clark , Abhinav Kumar , "Dmitry Baryshkov" , Sean Paul , , , "Jessica Zhang" X-Mailer: b4 0.13-dev-00303 X-Developer-Signature: v=1; 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Thus, use MSM DSC helper to calculate hdisplay for dsi_timing_setup instead of directly using mode->hdisplay. Changes in v3: - Split from previous patch - Initialized hdisplay as uncompressed pclk per line at the beginning of dsi_timing_setup as to not break dual DSI calculations Signed-off-by: Jessica Zhang --- drivers/gpu/drm/msm/dsi/dsi_host.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index 6a6218a9655f..9c33060e4c29 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -912,6 +912,9 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi) DBG(""); + if (msm_host->dsc) + hdisplay = msm_dsc_get_uncompressed_pclk_per_intf(msm_host->dsc); + /* * For bonded DSI mode, the current DRM mode has * the complete width of the panel. Since, the complete From patchwork Tue Apr 4 23:56:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jessica Zhang X-Patchwork-Id: 670090 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CFCA1C76188 for ; Tue, 4 Apr 2023 23:56:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236659AbjDDX4w (ORCPT ); Tue, 4 Apr 2023 19:56:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60874 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236647AbjDDX4v (ORCPT ); Tue, 4 Apr 2023 19:56:51 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 801E2421E for ; Tue, 4 Apr 2023 16:56:50 -0700 (PDT) Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 334Nscc0014157; Tue, 4 Apr 2023 23:56:44 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : date : subject : mime-version : content-type : content-transfer-encoding : message-id : references : in-reply-to : to : cc; s=qcppdkim1; bh=Icc6wVh+ZJmnYZWZNKuLidi1abjkDN1Zre33wc2idbw=; b=X2lIvfhrFUCkhbCxePo4/G7zUxvpf24GfiBV0JlWGIdq6iRqFxNUUo6f6nudCyU04vtq 1b805b2UdHdGLcPgz8X1b6wRnNgyGGi0h69CxktM/jvYSubWxW+uKW+gfcpSRncSt5Vl UyvOuQZ4fDnaszVOZUUJurmgFOVcrZSZJIub9BQlwt9esTKZea5ArlGo/METU3K1Wmrl DkGXuYzYgw/M+Yprz+EhCGbllgwPE+u3HyKU7BssbPoI2HH2MsL7Cl6MTWi4YVf7gnhB gt+ERhlKz9q3RkQboBxF+lPatzsAYWpWtfR+AMbA99remzlaoXkU3ULMabbP34N/aJF/ dw== Received: from nasanppmta04.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3prppuh4s7-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 04 Apr 2023 23:56:44 +0000 Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 334Nui1t026083 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 4 Apr 2023 23:56:44 GMT Received: from jesszhan-linux.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Tue, 4 Apr 2023 16:56:43 -0700 From: Jessica Zhang Date: Tue, 4 Apr 2023 16:56:18 -0700 Subject: [PATCH v3 6/6] drm/msm/dsi: Fix calculations pkt_per_line MIME-Version: 1.0 Message-ID: <20230329-rfc-msm-dsc-helper-v3-6-6bec0d277a83@quicinc.com> References: <20230329-rfc-msm-dsc-helper-v3-0-6bec0d277a83@quicinc.com> In-Reply-To: <20230329-rfc-msm-dsc-helper-v3-0-6bec0d277a83@quicinc.com> To: CC: Marijn Suijten , Konrad Dybcio , Daniel Vetter , Rob Clark , Abhinav Kumar , "Dmitry Baryshkov" , Sean Paul , , , "Jessica Zhang" X-Mailer: b4 0.13-dev-00303 X-Developer-Signature: v=1; a=ed25519-sha256; t=1680652602; l=1392; i=quic_jesszhan@quicinc.com; s=20230329; h=from:subject:message-id; bh=2TKG2xYMbG8LqkA7aO6gj6ecJQyGibncAAOn1PaWFJk=; b=++DZmqNOTEhTPKmJkWrB5ZG7508UX7LwPDl+zQA6Lt46uVbJ8q1ULMEsihu14hUr4vTFq24tq ZOAHW8kJUfgA/ZakAAYgaY9klu1b5OW4JZ1PMyMOQuE6XdbEcmPCPgI X-Developer-Key: i=quic_jesszhan@quicinc.com; a=ed25519; pk=gAUCgHZ6wTJOzQa3U0GfeCDH7iZLlqIEPo4rrjfDpWE= X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: vLMpSrchOVbQ6254_WUueq0_flMwELgy X-Proofpoint-ORIG-GUID: vLMpSrchOVbQ6254_WUueq0_flMwELgy X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-04-04_12,2023-04-04_05,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 lowpriorityscore=0 clxscore=1015 malwarescore=0 suspectscore=0 adultscore=0 mlxlogscore=940 phishscore=0 bulkscore=0 priorityscore=1501 mlxscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2304040217 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Currently, pkt_per_line is calculated by dividing slice_per_intf by slice_count. This is incorrect, as slice_per_intf should be divided by slice_per_pkt, which is not always equivalent to slice_count as it is possible for there to be multiple soft slices per interface even though a panel only specifies one slice per packet. Fixes: 08802f515c3c ("drm/msm/dsi: Add support for DSC configuration") Signed-off-by: Jessica Zhang Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dsi/dsi_host.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index 9c33060e4c29..d888978926da 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -862,7 +862,11 @@ static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mod total_bytes_per_intf = msm_dsc_get_bytes_per_intf(dsc, hdisplay); eol_byte_num = total_bytes_per_intf % 3; - pkt_per_line = slice_per_intf / dsc->slice_count; + + /* Default to 1 slice_per_pkt, so pkt_per_line will be equal to + * slice per intf. + */ + pkt_per_line = slice_per_intf; if (is_cmd_mode) /* packet data type */ reg = DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_DATATYPE(MIPI_DSI_DCS_LONG_WRITE);