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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id p1-20020a5d68c1000000b002c59f18674asm10088668wrw.22.2023.04.03.09.01.18 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Apr 2023 09:01:18 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 1/4] target/arm: Fix non-TCG build failure by inlining pauth_ptr_mask() Date: Mon, 3 Apr 2023 17:01:14 +0100 Message-Id: <20230403160117.3034102-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230403160117.3034102-1-peter.maydell@linaro.org> References: <20230403160117.3034102-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé aarch64_gdb_get_pauth_reg() -- although disabled since commit 5787d17a42 ("target/arm: Don't advertise aarch64-pauth.xml to gdb") is still compiled in. It calls pauth_ptr_mask() which is located in target/arm/tcg/pauth_helper.c, a TCG specific helper. To avoid a linking error when TCG is not enabled: Undefined symbols for architecture arm64: "_pauth_ptr_mask", referenced from: _aarch64_gdb_get_pauth_reg in target_arm_gdbstub64.c.o ld: symbol(s) not found for architecture arm64 clang: error: linker command failed with exit code 1 (use -v to see invocation) - Inline pauth_ptr_mask() in aarch64_gdb_get_pauth_reg() (this is the single user), - Rename pauth_ptr_mask_internal() as pauth_ptr_mask() and inline it in "internals.h", Fixes: e995d5cce4 ("target/arm: Implement gdbstub pauth extension") Suggested-by: Richard Henderson Reviewed-by: Fabiano Rosas Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Message-id: 20230328212516.29592-1-philmd@linaro.org [PMM: reinstated doc comment] Signed-off-by: Peter Maydell --- target/arm/internals.h | 15 ++++++++++----- target/arm/gdbstub64.c | 7 +++++-- target/arm/tcg/pauth_helper.c | 18 +----------------- 3 files changed, 16 insertions(+), 24 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 673519a24a0..c2c70d5918d 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1391,13 +1391,18 @@ bool arm_generate_debug_exceptions(CPUARMState *env); /** * pauth_ptr_mask: - * @env: cpu context - * @ptr: selects between TTBR0 and TTBR1 - * @data: selects between TBI and TBID + * @param: parameters defining the MMU setup * - * Return a mask of the bits of @ptr that contain the authentication code. + * Return a mask of the address bits that contain the authentication code, + * given the MMU config defined by @param. */ -uint64_t pauth_ptr_mask(CPUARMState *env, uint64_t ptr, bool data); +static inline uint64_t pauth_ptr_mask(ARMVAParameters param) +{ + int bot_pac_bit = 64 - param.tsz; + int top_pac_bit = 64 - 8 * param.tbi; + + return MAKE_64BIT_MASK(bot_pac_bit, top_pac_bit - bot_pac_bit); +} /* Add the cpreg definitions for debug related system registers */ void define_debug_regs(ARMCPU *cpu); diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index ec1e07f1399..c1f7e8c934b 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -230,8 +230,11 @@ int aarch64_gdb_get_pauth_reg(CPUARMState *env, GByteArray *buf, int reg) { bool is_data = !(reg & 1); bool is_high = reg & 2; - uint64_t mask = pauth_ptr_mask(env, -is_high, is_data); - return gdb_get_reg64(buf, mask); + ARMMMUIdx mmu_idx = arm_stage1_mmu_idx(env); + ARMVAParameters param; + + param = aa64_va_parameters(env, -is_high, mmu_idx, is_data); + return gdb_get_reg64(buf, pauth_ptr_mask(param)); } default: return 0; diff --git a/target/arm/tcg/pauth_helper.c b/target/arm/tcg/pauth_helper.c index 20f347332dc..de067fa7168 100644 --- a/target/arm/tcg/pauth_helper.c +++ b/target/arm/tcg/pauth_helper.c @@ -339,17 +339,9 @@ static uint64_t pauth_addpac(CPUARMState *env, uint64_t ptr, uint64_t modifier, return pac | ext | ptr; } -static uint64_t pauth_ptr_mask_internal(ARMVAParameters param) -{ - int bot_pac_bit = 64 - param.tsz; - int top_pac_bit = 64 - 8 * param.tbi; - - return MAKE_64BIT_MASK(bot_pac_bit, top_pac_bit - bot_pac_bit); -} - static uint64_t pauth_original_ptr(uint64_t ptr, ARMVAParameters param) { - uint64_t mask = pauth_ptr_mask_internal(param); + uint64_t mask = pauth_ptr_mask(param); /* Note that bit 55 is used whether or not the regime has 2 ranges. */ if (extract64(ptr, 55, 1)) { @@ -359,14 +351,6 @@ static uint64_t pauth_original_ptr(uint64_t ptr, ARMVAParameters param) } } -uint64_t pauth_ptr_mask(CPUARMState *env, uint64_t ptr, bool data) -{ - ARMMMUIdx mmu_idx = arm_stage1_mmu_idx(env); - ARMVAParameters param = aa64_va_parameters(env, ptr, mmu_idx, data); - - return pauth_ptr_mask_internal(param); -} - static uint64_t pauth_auth(CPUARMState *env, uint64_t ptr, uint64_t modifier, ARMPACKey *key, bool data, int keynumber) { From patchwork Mon Apr 3 16:01:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 669792 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d08:0:0:0:0:0 with SMTP id z8csp1964012wrt; Mon, 3 Apr 2023 09:02:32 -0700 (PDT) X-Google-Smtp-Source: AKy350a/0pT37kRAZ2KZM4vTJPOsOFbW+apD0VBuY4ujogEGY13m/v+RiyfUi5oCR5dhh8JK34Ai X-Received: by 2002:ac2:5159:0:b0:4e0:ee54:fa23 with SMTP id q25-20020ac25159000000b004e0ee54fa23mr10003804lfd.8.1680537752657; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id p1-20020a5d68c1000000b002c59f18674asm10088668wrw.22.2023.04.03.09.01.19 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Apr 2023 09:01:19 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 2/4] hw/arm: do not free machine->fdt in arm_load_dtb() Date: Mon, 3 Apr 2023 17:01:15 +0100 Message-Id: <20230403160117.3034102-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230403160117.3034102-1-peter.maydell@linaro.org> References: <20230403160117.3034102-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Markus Armbruster At this moment, arm_load_dtb() can free machine->fdt when binfo->dtb_filename is NULL. If there's no 'dtb_filename', 'fdt' will be retrieved by binfo->get_dtb(). If get_dtb() returns machine->fdt, as is the case of machvirt_dtb() from hw/arm/virt.c, fdt now has a pointer to machine->fdt. And, in that case, the existing g_free(fdt) at the end of arm_load_dtb() will make machine->fdt point to an invalid memory region. Since monitor command 'dumpdtb' was introduced a couple of releases ago, running it with any ARM machine that uses arm_load_dtb() will crash QEMU. Let's enable all arm_load_dtb() callers to use dumpdtb properly. Instead of freeing 'fdt', assign it back to ms->fdt. Cc: Peter Maydell Cc: qemu-arm@nongnu.org Fixes: bf353ad55590f ("qmp/hmp, device_tree.c: introduce dumpdtb") Reported-by: Markus Armbruster Signed-off-by: Daniel Henrique Barboza Signed-off-by: Markus Armbruster Reviewed-by: Daniel Henrique Barboza Message-id: 20230328165935.1512846-1-armbru@redhat.com Signed-off-by: Peter Maydell --- hw/arm/boot.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/hw/arm/boot.c b/hw/arm/boot.c index 50e5141116b..54f6a3e0b3c 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -689,7 +689,10 @@ int arm_load_dtb(hwaddr addr, const struct arm_boot_info *binfo, qemu_register_reset_nosnapshotload(qemu_fdt_randomize_seeds, rom_ptr_for_as(as, addr, size)); - g_free(fdt); + if (fdt != ms->fdt) { + g_free(ms->fdt); + ms->fdt = fdt; + } return size; From patchwork Mon Apr 3 16:01:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 669793 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d08:0:0:0:0:0 with SMTP id z8csp1964016wrt; Mon, 3 Apr 2023 09:02:33 -0700 (PDT) X-Google-Smtp-Source: AKy350aL2fNoMhpryUDgYSUMClApRFyPmlclCJDN51CbBqBwIDSAMTqi3GGgltNl6MTTI2GPaHAA X-Received: by 2002:a19:7404:0:b0:4e8:3fc7:9483 with SMTP id v4-20020a197404000000b004e83fc79483mr10098159lfe.23.1680537752687; Mon, 03 Apr 2023 09:02:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680537752; cv=none; d=google.com; s=arc-20160816; b=B1q29d+FrA1x4WJ2G0oQMWG4tXBkMF1BCv9PPLLNSI16OH6QA7Gn8YV1sPZKqylxrv vUw621UOoJx3WJ4bpLuy5qRde0r/MTfnhhuK0ScEjv1tmKRWdPvGxxY0IEbh3Y9O2d6d BnTMS73axrr+M7/Y4GQj3u2yVKDhtKK6xuj/YD2cS84qTtUZUklj+F/T33wLyzFCBopu 4yuFHOBBIES4xGPrUP1mR/fOUGEVLCQwBDQJi72JBIASuroWo8RSwUbqoINB2Fz9ZTd8 59BTKh+pcc3VWn5d+iiKYYVh5K+Ab2F95JZi+aXQfQFfEwGk/rDHdDhnjDtXRQ+5H/2B U2yA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=D0bzLBgoxKzl8wuuz0d2cPzzjDTy7V+sRD0Owr6cPGk=; b=u3ykrLBa+jC6PlNnKl/eVGP6UyfroGhyNHMtmiX9G3Nd1qU2zPdc+po5GuFqrW8GIs rVns1rqOssmbUQHQlDr/Rj5lQ0CeyM8MrB+OaqW+MWYfT33JSk1wEaNrZeT4Pq2hNdK4 46nyuF0eeQHzqRbGBfBIW/pU7heBrszVvsMeP3qMyXlTflgrCbf+cARrxq2C4frIkl58 CA3MHJsEJcf7yk5mB4ucziFyk4BUE93IKIHhsTyN1mU05qpYLzanHBTmoCMMW9TiR4nh o6SCJfamD2YNw9VmzKtJotQuj2SvuiG9kuGlwBZcud+lC8mYLrWgX08wRO8Kc6nM5KyW dURA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=q5ejblw0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id p1-20020a5d68c1000000b002c59f18674asm10088668wrw.22.2023.04.03.09.01.20 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Apr 2023 09:01:20 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 3/4] target/arm: Fix generated code for cpreg reads when HSTR is active Date: Mon, 3 Apr 2023 17:01:16 +0100 Message-Id: <20230403160117.3034102-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230403160117.3034102-1-peter.maydell@linaro.org> References: <20230403160117.3034102-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In commit 049edada we added some code to handle HSTR_EL2 traps, which we did as an inline "conditionally branch over a gen_exception_insn()". Unfortunately this fails to take account of the fact that gen_exception_insn() will set s->base.is_jmp to DISAS_NORETURN. That means that at the end of the TB we won't generate the necessary code to handle the "branched over the trap and continued normal execution" codepath. The result is that the TCG main loop thinks that we stopped execution of the TB due to a situation that only happens when icount is enabled, and hits an assertion. Explicitly set is_jmp back to DISAS_NEXT so we generate the correct code for when execution continues past this insn. Note that this only happens for cpreg reads; writes will call gen_lookup_tb() which generates a valid end-of-TB. Fixes: 049edada ("target/arm: Make HSTR_EL2 traps take priority over UNDEF-at-EL1") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1551 Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230330101900.2320380-1-peter.maydell@linaro.org --- target/arm/tcg/translate.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index 2cb9368b1ba..3c8401e9086 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -4623,6 +4623,12 @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64, tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, over.label); gen_exception_insn(s, 0, EXCP_UDEF, syndrome); + /* + * gen_exception_insn() will set is_jmp to DISAS_NORETURN, + * but since we're conditionally branching over it, we want + * to assume continue-to-next-instruction. + */ + s->base.is_jmp = DISAS_NEXT; set_disas_label(s, over); } } From patchwork Mon Apr 3 16:01:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 669794 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d08:0:0:0:0:0 with SMTP id z8csp1964015wrt; Mon, 3 Apr 2023 09:02:32 -0700 (PDT) X-Google-Smtp-Source: AK7set+7ALnYVLtwjRIpRBjRg43WJIKvE6M6JO0Jdhc7xCHgw6kd9z0PXJqgH3J/bfpl8o2nLnNd X-Received: by 2002:a05:6808:18a0:b0:387:205b:70c7 with SMTP id bi32-20020a05680818a000b00387205b70c7mr21635934oib.13.1680537752649; Mon, 03 Apr 2023 09:02:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680537752; cv=none; d=google.com; s=arc-20160816; b=VdX1WjAsbHdvav6GAHLcvAZ/EYnf4BWr3edE8LyEEQL2DLZV7kpaR/eRCxOE2z0y9W w90duMuIt9Kvg5UJM7QukywhX4QZPK0a3DsTwqWRWD7omc7J/LtHgy6qWXoSi0ShExdr iOrkQ1WKI4q018Jqn5N7YC7UriWPWOJD2zEvvu6KwR/njuriJR5XuZyQuNAOFZt8tcGM vi2TvKnY0KhG/56aIj4W1qf2EIC3cIvaCuzvqtcYT1bzIhE9fnG1rMbE2bdNXzHK9ecQ ghfrYxmMQdFA/+BTq6tdycm19c3SWaHhGADDyOVxdij6su5e0Pm8O6/kqOXsStK0f0AC aNTA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=V/wpFoRtLBHl9IngzkoD10ivVrKdxV4x7qoi+Upw/so=; b=qqua4aen6ZdTL/xCc6oQ4pki/vm9R2riSNqFWrphEHTK8mXaZPIUbEundkTaO0Al4O 1k489Gscj+pAwzy82B6F4R/FwmwcOo8R+GT7hiG8vTsfIVLEH2cX3wFbbMqQhlNxqX8d bECskb8XaUFRB3Ix/nusCbn9RwGhD9G0Rq2py7jM1E2IowVlShpgYVuw5Bt5zVD/H4O0 wLLPEmRi4JJeZ5b1vcFaGxeb+dFERNoxU4CEnJPPc7ob4nXqgPkZM39jdwxLG+ZtW0Ag r3EXE+khDT4InQQtZDBVDL+ruIRzzWTF7YKcr3/tdNfnRIxgD1p/ZHBginGW/u+i+ct7 HDjw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HtbRkW21; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id p1-20020a5d68c1000000b002c59f18674asm10088668wrw.22.2023.04.03.09.01.20 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Apr 2023 09:01:20 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 4/4] hw/ssi: Fix Linux driver init issue with xilinx_spi Date: Mon, 3 Apr 2023 17:01:17 +0100 Message-Id: <20230403160117.3034102-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230403160117.3034102-1-peter.maydell@linaro.org> References: <20230403160117.3034102-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Chris Rauer The problem is that the Linux driver expects the master transaction inhibit bit(R_SPICR_MTI) to be set during driver initialization so that it can detect the fifo size but QEMU defaults it to zero out of reset. The datasheet indicates this bit is active on reset. See page 25, SPI Control Register section: https://www.xilinx.com/content/dam/xilinx/support/documents/ip_documentation/axi_quad_spi/v3_2/pg153-axi-quad-spi.pdf Signed-off-by: Chris Rauer Message-id: 20230323182811.2641044-1-crauer@google.com Reviewed-by: Edgar E. Iglesias Signed-off-by: Peter Maydell --- hw/ssi/xilinx_spi.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/ssi/xilinx_spi.c b/hw/ssi/xilinx_spi.c index 552927622f4..d4de2e7aabc 100644 --- a/hw/ssi/xilinx_spi.c +++ b/hw/ssi/xilinx_spi.c @@ -156,6 +156,7 @@ static void xlx_spi_do_reset(XilinxSPI *s) txfifo_reset(s); s->regs[R_SPISSR] = ~0; + s->regs[R_SPICR] = R_SPICR_MTI; xlx_spi_update_irq(s); xlx_spi_update_cs(s); }