From patchwork Sat Apr 1 11:54:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 669668 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AE9BCC76196 for ; Sat, 1 Apr 2023 11:54:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229792AbjDALyz (ORCPT ); Sat, 1 Apr 2023 07:54:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51304 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229659AbjDALyy (ORCPT ); Sat, 1 Apr 2023 07:54:54 -0400 Received: from mail-lf1-x12a.google.com (mail-lf1-x12a.google.com [IPv6:2a00:1450:4864:20::12a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2A1091D864 for ; Sat, 1 Apr 2023 04:54:53 -0700 (PDT) Received: by mail-lf1-x12a.google.com with SMTP id k37so32285005lfv.0 for ; Sat, 01 Apr 2023 04:54:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680350091; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=ctHnqMHZO0pzp/yb6Z2dEorUTEc6FXrEYWhX8iD6OjI=; b=aVGHIcDwAhHEbX8rTDGY5Rb7qR+M8HNPK1MH/vfK/lO55HbWywTqJdioncURcXv74e uYUfZxuRkvuzEdG+Y8CDvm9LahtJQPUhWh5yf/HJm6EfXfTLdNdesGBE5Or4MSIVY+xE orjq0j64cZMqQrb0MWijoKzQ+mVpMQ4EDd1EL0NcOEm6OgjcOsBEuBe5a3+A8XaXz7Zh q7V2dWHDmHmbL29R0wg+Ti3q6nM7B4pV6Z5BYUz0MbC+L8Rp79e7uV7bangEAU3uTgVf Qhz0JiukPVUgwnO6F2/EQv5JbXJNJh2pcpZyuERJB7pJNJILCGqm5SyDjg6nJ1JQS18d 2heA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680350091; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ctHnqMHZO0pzp/yb6Z2dEorUTEc6FXrEYWhX8iD6OjI=; b=Vs/T/Ah/QeiVNdXieBpwcLYVDHCSP19Fz+6UWL8sa4TmOeapXEwPxjKnheSofxSNE3 sWWFWI8ObIghTMNLP0jO4YAtRJ9IaPmX3F0+lXxDAPKUQobAsN54lAMmQntEFbf8qkzf vMPBLcJ5OTBkKb0I0+yR77BsKtdzQCcK8jXl7aK9ANLXxpaSx/A062p0OYe1RjUfqI1b nzxoKLOHi3YUxWUi8JVtW/CRuz8ESkL/aMCJeD7don8OUYLhPD2zkYiFeMQ6ba1Ch5Wb Xlng/W7F6Ha6m+/TFLDcZ3VZW8T2lXRzjNIYa+HDjqf9yeYNukggZZ1RXXdkY42H1GjL ezaA== X-Gm-Message-State: AAQBX9fbYMOh+xXBaS9XDAJRHUtwSksC/9K57Cgz+vMHM4rPhLc3+GRh tiAy+fHWeJpJ2eElvN8+F/Ms+g== X-Google-Smtp-Source: AKy350aIVzUYbMsf+4Ma49meqzWQW8ICcdLO0rTGM74lSEzeeotYTSpy/PnWE+VwXf87vD0pJkvzgA== X-Received: by 2002:ac2:5972:0:b0:4db:3847:12f0 with SMTP id h18-20020ac25972000000b004db384712f0mr9567501lfp.50.1680350091424; Sat, 01 Apr 2023 04:54:51 -0700 (PDT) Received: from [192.168.1.101] (abxj225.neoplus.adsl.tpnet.pl. [83.9.3.225]) by smtp.gmail.com with ESMTPSA id w8-20020ac254a8000000b004e83f386878sm786737lfk.153.2023.04.01.04.54.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Apr 2023 04:54:51 -0700 (PDT) From: Konrad Dybcio Date: Sat, 01 Apr 2023 13:54:38 +0200 Subject: [PATCH v6 01/15] drm/msm/adreno: adreno_gpu: Don't set OPP scaling clock w/ GMU MIME-Version: 1.0 Message-Id: <20230223-topic-gmuwrapper-v6-1-2034115bb60c@linaro.org> References: <20230223-topic-gmuwrapper-v6-0-2034115bb60c@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v6-0-2034115bb60c@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1680350084; l=2082; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=uLNnu/k+L1QbWFWkCWE2U/K/JWVJJaw9MSaaSbA5pkE=; b=c69tvTZp+eIVVV5kmR4XL9hM2jDTb2CKHbPZwbWjhYEMNXj783BF9pyz0eHWUGzzmv+6khEclsDI yYPF1Uk6C03PYld7+6ehn4/5kGtJCEAZhtxsV29rkQPqEQgn8BZv X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Recently I contributed the switch to OPP API for all Adreno generations. I did however also skip over the fact that GPUs with a GMU don't specify a core clock of any kind in the GPU node. While that didn't break anything, it did introduce unwanted spam in the dmesg: adreno 5000000.gpu: error -ENOENT: _opp_set_clknames: Couldn't find clock with name: core_clk Guard the entire logic so that it's not used with GMU-equipped GPUs. Fixes: 9f251f934012 ("drm/msm/adreno: Use OPP for every GPU generation") Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 24 ++++++++++++++---------- 1 file changed, 14 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index bb38e728864d..6934cee07d42 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -1074,18 +1074,22 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, u32 speedbin; int ret; - /* - * This can only be done before devm_pm_opp_of_add_table(), or - * dev_pm_opp_set_config() will WARN_ON() - */ - if (IS_ERR(devm_clk_get(dev, "core"))) { + /* Only handle the core clock when GMU is not in use */ + if (config->rev.core < 6) { /* - * If "core" is absent, go for the legacy clock name. - * If we got this far in probing, it's a given one of them exists. + * This can only be done before devm_pm_opp_of_add_table(), or + * dev_pm_opp_set_config() will WARN_ON() */ - devm_pm_opp_set_clkname(dev, "core_clk"); - } else - devm_pm_opp_set_clkname(dev, "core"); + if (IS_ERR(devm_clk_get(dev, "core"))) { + /* + * If "core" is absent, go for the legacy clock name. + * If we got this far in probing, it's a given one of + * them exists. + */ + devm_pm_opp_set_clkname(dev, "core_clk"); + } else + devm_pm_opp_set_clkname(dev, "core"); + } adreno_gpu->funcs = funcs; adreno_gpu->info = adreno_info(config->rev); From patchwork Sat Apr 1 11:54:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 669445 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DB961C76196 for ; Sat, 1 Apr 2023 11:55:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229882AbjDALzG (ORCPT ); Sat, 1 Apr 2023 07:55:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51722 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229825AbjDALzF (ORCPT ); Sat, 1 Apr 2023 07:55:05 -0400 Received: from mail-lf1-x12a.google.com (mail-lf1-x12a.google.com [IPv6:2a00:1450:4864:20::12a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8D6951D92E for ; Sat, 1 Apr 2023 04:54:57 -0700 (PDT) Received: by mail-lf1-x12a.google.com with SMTP id br6so32193965lfb.11 for ; Sat, 01 Apr 2023 04:54:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680350095; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=1zLOaNti8US4yjllYIUZXiOKkjRQYJjDZ58RHJWDDs4=; b=RuNCVGTaN5gZnDQnvL6Nhf5iCmkua53Vi4bno/QMxLBaTtqkqGPCyrmvByqtzYkmHW Xr4YdeQqCir0ro2gRn+mbRb7xIzxOJ3hYAb+KvA16dWVsaHuNJ8LfrM3EErpnjB7qi+X feoiKpibMclNNCJ/GIaDM3Km77vZPtf/TNszA7bFAn9ZZeXR00DgG079KZVG7gZuGdz+ PrAr6cYKl4b0txU4BYmbaIYMxVWPIln/rdoIR4uXbrCRmW8LEinj1gPm346qCaeVYa52 YkxuxLNoeEQ33EPIiQ4tqELVVoYzZADHPEmAyTUCXTYDBI22vn1jLlHplWtj2z9xEALw R+jw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680350095; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1zLOaNti8US4yjllYIUZXiOKkjRQYJjDZ58RHJWDDs4=; b=7mGqkOCb43tI0GKV1NByjod6eSaxDDswvSbwZiWOW1KcecYB6hM/TuFdYFvc7/inTE DrzDZdRbOW29fxAixh6d3VzIYeSNasPTuBDKZ9Ychb9anVVKnv1Z++lnl+Q3NhM5snZp ol/i2rxL4d/BYqIOf2C1OjHw0rr94Wv+X2VGswpNoDZAOgfWdPXCEq5Dh4XhKAC3g7kX dQ8P1fXKK/sb7dKTQ+cUcyC6akdv7gxltE7r8jGIBp1UgnJBkAvSishQoD6vGIT06FjV yPczzzOmAkNfiOU79oDvqryIFuI1FYlTz2X980tE6s0hfVgiOLvHcAezSXobz1+d3c1L J2Qw== X-Gm-Message-State: AAQBX9eGXAJF8cEe/gpMboI6zh01BSCd2PtWwERA7h9EjRG+IfVrjuC5 sYkyuGpkriOcTWKoWiIfKyVfqw== X-Google-Smtp-Source: AKy350YuzizgJ6QE3l39U5ozbe45B4Y6XvzYkEt87TCXHM2UIwCbBE/2TFoNySQXVHG7Z0SLkqf7ag== X-Received: by 2002:ac2:5fc8:0:b0:4eb:1294:983d with SMTP id q8-20020ac25fc8000000b004eb1294983dmr5425511lfg.7.1680350095725; Sat, 01 Apr 2023 04:54:55 -0700 (PDT) Received: from [192.168.1.101] (abxj225.neoplus.adsl.tpnet.pl. [83.9.3.225]) by smtp.gmail.com with ESMTPSA id w8-20020ac254a8000000b004e83f386878sm786737lfk.153.2023.04.01.04.54.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Apr 2023 04:54:55 -0700 (PDT) From: Konrad Dybcio Date: Sat, 01 Apr 2023 13:54:39 +0200 Subject: [PATCH v6 02/15] dt-bindings: display/msm: gpu: Document GMU wrapper-equipped A6xx MIME-Version: 1.0 Message-Id: <20230223-topic-gmuwrapper-v6-2-2034115bb60c@linaro.org> References: <20230223-topic-gmuwrapper-v6-0-2034115bb60c@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v6-0-2034115bb60c@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1680350084; l=3273; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=PlpPtlQZuCcXGxNxg4tBwrBjp8RpPmQvuWz5XR9uQF0=; b=+zjHJg9qutShAJ+HmZMGEEq7+Hwtxprz8Uf0MwcBkcf4tKJyKXX8ACUw+IsQJxplDgzmP73Z/0eG +njJZ0tHCn31Hsd2F4BPwa8r9Kco4MJPEyAU5Cqxoicl6iIaikX5 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The "GMU Wrapper" is Qualcomm's name for "let's treat the GPU blocks we'd normally assign to the GMU as if they were a part of the GMU, even though they are not". It's a (good) software representation of the GMU_CX and GMU_GX register spaces within the GPUSS that helps us programatically treat these de-facto GMU-less parts in a way that's very similar to their GMU-equipped cousins, massively saving up on code duplication. The "wrapper" register space was specifically designed to mimic the layout of a real GMU, though it rather obviously does not have the M3 core et al. GMU wrapper-equipped A6xx GPUs require clocks and clock-names to be specified under the GPU node, just like their older cousins. Account for that. Signed-off-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/display/msm/gpu.yaml | 61 ++++++++++++++++++---- 1 file changed, 52 insertions(+), 9 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Documentation/devicetree/bindings/display/msm/gpu.yaml index 5dabe7b6794b..58ca8912a8c3 100644 --- a/Documentation/devicetree/bindings/display/msm/gpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml @@ -36,10 +36,7 @@ properties: reg-names: minItems: 1 - items: - - const: kgsl_3d0_reg_memory - - const: cx_mem - - const: cx_dbgc + maxItems: 3 interrupts: maxItems: 1 @@ -157,16 +154,62 @@ allOf: required: - clocks - clock-names + - if: properties: compatible: contains: - pattern: '^qcom,adreno-6[0-9][0-9]\.[0-9]$' - - then: # Since Adreno 6xx series clocks should be defined in GMU + enum: + - qcom,adreno-610.0 + - qcom,adreno-619.1 + then: properties: - clocks: false - clock-names: false + clocks: + minItems: 6 + maxItems: 6 + + clock-names: + items: + - const: core + description: GPU Core clock + - const: iface + description: GPU Interface clock + - const: mem_iface + description: GPU Memory Interface clock + - const: alt_mem_iface + description: GPU Alternative Memory Interface clock + - const: gmu + description: CX GMU clock + - const: xo + description: GPUCC clocksource clock + + reg-names: + minItems: 1 + items: + - const: kgsl_3d0_reg_memory + - const: cx_dbgc + + required: + - clocks + - clock-names + else: + if: + properties: + compatible: + contains: + pattern: '^qcom,adreno-6[0-9][0-9]\.[0-9]$' + + then: # Starting with A6xx, the clocks are usually defined in the GMU node + properties: + clocks: false + clock-names: false + + reg-names: + minItems: 1 + items: + - const: kgsl_3d0_reg_memory + - const: cx_mem + - const: cx_dbgc examples: - | From patchwork Sat Apr 1 11:54:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 669667 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 28B54C77B61 for ; Sat, 1 Apr 2023 11:55:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229900AbjDALzH (ORCPT ); Sat, 1 Apr 2023 07:55:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51754 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229832AbjDALzF (ORCPT ); Sat, 1 Apr 2023 07:55:05 -0400 Received: from mail-lf1-x131.google.com (mail-lf1-x131.google.com [IPv6:2a00:1450:4864:20::131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4A3A223B51 for ; Sat, 1 Apr 2023 04:54:58 -0700 (PDT) Received: by mail-lf1-x131.google.com with SMTP id q16so32197998lfe.10 for ; Sat, 01 Apr 2023 04:54:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680350098; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=HnEMhNsn7kHL6KC8gQ4HhHhkok2Hiu0bEYeYgvAPNX0=; b=mRPItMZ+WrNjgMnxSc9haKnqlugPzGyt2cBKUaFlSCaAv5RHs6s+Vs25TkZwsiCdpt Uft/buXPDJ+2IbEpuzfpuxUR8n+xXuWo5lJRQnzCbbA0r6LLwR6ZCAUCDVxUGLLYYi2J JkTh8Yiienili892i0eEGcvlx5p4c+Kn2y6SM8vwaC3M1mo5uJShde1lyKZ3UBFtdhlC jXChioEAZg/FzuQMpgfSaeszbCt+bTSj6X87fRfDEOTS+O4R4eSMSccWv8wcho1H7xb7 5nHIkQU9FDbfnXhjU9rchcvHB9ARnhxGF/e6M3FCskJ+tCaaiUU7yZTsj0rB/SAPIBPc LdWA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680350098; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HnEMhNsn7kHL6KC8gQ4HhHhkok2Hiu0bEYeYgvAPNX0=; b=ySE1ETKdLsTjDJmFC/LYs5fvRn8rU4jZl3xJbh4du65OJnvk3rZYciKAtTXwfrF7BY G4JyLZUNuZkhurMunvFfUvrJ2V2/1WfgqnNu4OMQSKhefmQlsJLuYKXmQ/wgVQYyJaSK RPaNKMbZJwjWT8JSTODZGxTqP61SVq604icx8TsAeyo9uzofSQJenfPR2+mAXdYSs8ru kpaXHw6hhUJDBFe6wfvzDCGoWDwBNAyx/00RwOMEaRIO+3qxJP27rF51XC/NxckYcP8W 2FrW+UkHaJ8d7y6bkLv/aluNwMLMf7CHfL7sZvlrWwVsqjCe0G63LYxDTsRvBsPjDICp Dz8g== X-Gm-Message-State: AAQBX9eUbFB3OYWxhP0hZkso+lAKH+F7XOyOIGrQrFwXwdWf28hjRrl4 0nTfdK1MNUoHHxA8ojKI6PMrog== X-Google-Smtp-Source: AKy350bfnPEXAN3ouyNj2TtaVOBpXsh2+aVPtdalJp3W0r3qtfzTzq9fzTA3aAUJqokjMngHioNYvA== X-Received: by 2002:ac2:4889:0:b0:4e0:61a6:c158 with SMTP id x9-20020ac24889000000b004e061a6c158mr8474555lfc.36.1680350097834; Sat, 01 Apr 2023 04:54:57 -0700 (PDT) Received: from [192.168.1.101] (abxj225.neoplus.adsl.tpnet.pl. [83.9.3.225]) by smtp.gmail.com with ESMTPSA id w8-20020ac254a8000000b004e83f386878sm786737lfk.153.2023.04.01.04.54.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Apr 2023 04:54:57 -0700 (PDT) From: Konrad Dybcio Date: Sat, 01 Apr 2023 13:54:40 +0200 Subject: [PATCH v6 03/15] dt-bindings: display/msm/gmu: Add GMU wrapper MIME-Version: 1.0 Message-Id: <20230223-topic-gmuwrapper-v6-3-2034115bb60c@linaro.org> References: <20230223-topic-gmuwrapper-v6-0-2034115bb60c@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v6-0-2034115bb60c@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio , Krzysztof Kozlowski X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1680350084; l=3381; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=gRbQW6m4WkjCaooGTDuAvaThk4xamrj0048X6Oez/Ng=; b=YkV+Gd21MkX/28W5SFDiGNyKn8qyn7PFblseYbJE0b0W6XqkjW8tVuil7YsKSCvVx5nqKhjFxHPD TsrdSNWMB7qMRxb4zJnGH3gzxufQSD21jECfU5DcIZx04fagzPHT X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The "GMU Wrapper" is Qualcomm's name for "let's treat the GPU blocks we'd normally assign to the GMU as if they were a part of the GMU, even though they are not". It's a (good) software representation of the GMU_CX and GMU_GX register spaces within the GPUSS that helps us programatically treat these de-facto GMU-less parts in a way that's very similar to their GMU-equipped cousins, massively saving up on code duplication. The "wrapper" register space was specifically designed to mimic the layout of a real GMU, though it rather obviously does not have the M3 core et al. To sum it all up, the GMU wrapper is essentially a register space within the GPU, which Linux sees as a dumbed-down regular GMU: there's no clocks, interrupts, multiple reg spaces, iommus and OPP. Document it. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio --- .../devicetree/bindings/display/msm/gmu.yaml | 50 ++++++++++++++++------ 1 file changed, 38 insertions(+), 12 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml b/Documentation/devicetree/bindings/display/msm/gmu.yaml index 029d72822d8b..e36c40b935de 100644 --- a/Documentation/devicetree/bindings/display/msm/gmu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gmu.yaml @@ -19,16 +19,18 @@ description: | properties: compatible: - items: - - pattern: '^qcom,adreno-gmu-6[0-9][0-9]\.[0-9]$' - - const: qcom,adreno-gmu + oneOf: + - items: + - pattern: '^qcom,adreno-gmu-6[0-9][0-9]\.[0-9]$' + - const: qcom,adreno-gmu + - const: qcom,adreno-gmu-wrapper reg: - minItems: 3 + minItems: 1 maxItems: 4 reg-names: - minItems: 3 + minItems: 1 maxItems: 4 clocks: @@ -44,7 +46,6 @@ properties: - description: GMU HFI interrupt - description: GMU interrupt - interrupt-names: items: - const: hfi @@ -72,14 +73,8 @@ required: - compatible - reg - reg-names - - clocks - - clock-names - - interrupts - - interrupt-names - power-domains - power-domain-names - - iommus - - operating-points-v2 additionalProperties: false @@ -217,6 +212,28 @@ allOf: - const: axi - const: memnoc + - if: + properties: + compatible: + contains: + const: qcom,adreno-gmu-wrapper + then: + properties: + reg: + items: + - description: GMU wrapper register space + reg-names: + items: + - const: gmu + else: + required: + - clocks + - clock-names + - interrupts + - interrupt-names + - iommus + - operating-points-v2 + examples: - | #include @@ -249,3 +266,12 @@ examples: iommus = <&adreno_smmu 5>; operating-points-v2 = <&gmu_opp_table>; }; + + gmu_wrapper: gmu@596a000 { + compatible = "qcom,adreno-gmu-wrapper"; + reg = <0x0596a000 0x30000>; + reg-names = "gmu"; + power-domains = <&gpucc GPU_CX_GDSC>, + <&gpucc GPU_GX_GDSC>; + power-domain-names = "cx", "gx"; + }; From patchwork Sat Apr 1 11:54:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 669444 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 008E3C6FD1D for ; Sat, 1 Apr 2023 11:55:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229923AbjDALzK (ORCPT ); Sat, 1 Apr 2023 07:55:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51732 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229867AbjDALzG (ORCPT ); Sat, 1 Apr 2023 07:55:06 -0400 Received: from mail-lf1-x12a.google.com (mail-lf1-x12a.google.com [IPv6:2a00:1450:4864:20::12a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B18D524AC9 for ; Sat, 1 Apr 2023 04:55:00 -0700 (PDT) Received: by mail-lf1-x12a.google.com with SMTP id bi9so32196614lfb.12 for ; Sat, 01 Apr 2023 04:55:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680350100; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=TbK2MVc1rKgyfPXfQElwY/6uPFFij3UrjXWyfn1dhPY=; b=fjL75dISZSV4H+8N12RUuLPgkvtiebKr+6ASoAkWxwfNiElc7/ojpiwwM3yQ/36c3I vWOXBYewl/m36ml0HT2/EnizqK63B9YCoSQR3Kavg8o42p7YH/4eRrbrgz91hpA6uuUk HYesEBGnCLJbbBdCmh9RDfmpPYX7LdT0dEH7vJdDF8brce3qbgqiClPB1Ld2JlKYNVsB GCBaziPE/grDFbX/NVENrq3jFeW6tqRDdlOkW0SGUiB3oVuMWVIcG4thFbLKAP6Sr7mh 3QiAlOsUfwAv06pIxXMAgIz+lnbnd+KQ6gVDFzqSJaWl5wpvDSzBZTUGDf65sbOlEOYh 7+sg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680350100; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TbK2MVc1rKgyfPXfQElwY/6uPFFij3UrjXWyfn1dhPY=; b=qfT2153WKY7wyGhEXZZrf3tN9njtrIyg7RlVhj3EesjD/0X0z/ztWgtjcF+xmfQu3U suo7C+uN2PPgE6mgaHe69oWJ9G26T3tfEZNSLTLGfV6bSmO68g344w7CjpKAOmPuoQN1 +5WmhkAmx1Qp9k6FHevf9r1Fmo0wn4XnEuf7d/Ef2X0G6UeCHBF0SzPSAm2lO5NR1eGx kUgOb9qhaIBrAENoDwWLyY4LnCqoQKGwC+a11lsr6ZsjznCfzjJcG0SczQjh/j7pzFCr pFnCvbFvaln0t86FhgBxrmD9VN9ZfEOissYujFXeP7ADp6KmIM2tLMw1uYd3tm9rbT9n PKQQ== X-Gm-Message-State: AAQBX9eeZgkts2ZixUswaLQohBud3IBzI9Ta4nLhN+JFINGZ43lJYMBN jAl8esxtezlF+JyAXLBIhAq2bA== X-Google-Smtp-Source: AKy350ZikYFxTM1MU3eUgc0PKcoDOOnyTT4LYLXu9S8Wq3YzPlUdOjbCAo75MJyxQB8wUCG3Wxdftw== X-Received: by 2002:a19:5510:0:b0:4ea:f9d4:93a0 with SMTP id n16-20020a195510000000b004eaf9d493a0mr5593306lfe.34.1680350100305; Sat, 01 Apr 2023 04:55:00 -0700 (PDT) Received: from [192.168.1.101] (abxj225.neoplus.adsl.tpnet.pl. [83.9.3.225]) by smtp.gmail.com with ESMTPSA id w8-20020ac254a8000000b004e83f386878sm786737lfk.153.2023.04.01.04.54.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Apr 2023 04:55:00 -0700 (PDT) From: Konrad Dybcio Date: Sat, 01 Apr 2023 13:54:41 +0200 Subject: [PATCH v6 04/15] drm/msm/a6xx: Remove static keyword from sptprac en/disable functions MIME-Version: 1.0 Message-Id: <20230223-topic-gmuwrapper-v6-4-2034115bb60c@linaro.org> References: <20230223-topic-gmuwrapper-v6-0-2034115bb60c@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v6-0-2034115bb60c@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1680350084; l=1711; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=WpExda3PhDQwvsN/3DDBnvG0Z5wUKLMO4vx8OFJgLF8=; b=75IfQDAr9WDnfiDmZMmGzjEjaJNUGRJAMt23AHzSA5NWTjC9aPCa0S1vDW95VzrXJKrvjMNy/KHm ZelYSLzJDnopySv+ciDpRcmx/KPYBt9AILvfACq9ERo1s71ICFme X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org These two will be reused by at least A619_holi in the non-gmu paths. Turn them non-static them to make it possible. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 4 ++-- drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 2 ++ 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index e16b4b3f8535..87babbb2a19f 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -354,7 +354,7 @@ void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state) } /* Enable CPU control of SPTP power power collapse */ -static int a6xx_sptprac_enable(struct a6xx_gmu *gmu) +int a6xx_sptprac_enable(struct a6xx_gmu *gmu) { int ret; u32 val; @@ -376,7 +376,7 @@ static int a6xx_sptprac_enable(struct a6xx_gmu *gmu) } /* Disable CPU control of SPTP power power collapse */ -static void a6xx_sptprac_disable(struct a6xx_gmu *gmu) +void a6xx_sptprac_disable(struct a6xx_gmu *gmu) { u32 val; int ret; diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h index 0bc3eb443fec..7ee5b606bc47 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h @@ -193,5 +193,7 @@ int a6xx_hfi_set_freq(struct a6xx_gmu *gmu, int index); bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu); bool a6xx_gmu_sptprac_is_on(struct a6xx_gmu *gmu); +void a6xx_sptprac_disable(struct a6xx_gmu *gmu); +int a6xx_sptprac_enable(struct a6xx_gmu *gmu); #endif From patchwork Sat Apr 1 11:54:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 669666 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 24BBBC761AF for ; Sat, 1 Apr 2023 11:55:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229831AbjDALzT (ORCPT ); Sat, 1 Apr 2023 07:55:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51766 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229917AbjDALzI (ORCPT ); Sat, 1 Apr 2023 07:55:08 -0400 Received: from mail-lf1-x12a.google.com (mail-lf1-x12a.google.com [IPv6:2a00:1450:4864:20::12a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9B6D525473 for ; Sat, 1 Apr 2023 04:55:03 -0700 (PDT) Received: by mail-lf1-x12a.google.com with SMTP id br6so32194167lfb.11 for ; Sat, 01 Apr 2023 04:55:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680350103; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=EcTVfYVJVvyjT/gmTGLxErkT9wedlUsEwNFe3X7+hGY=; b=hka16u4/n+DaWI8KLthmzu7abmpNUNrh+4WYo9kw74EijqTQ+uv8BmIc5dC2/0XNTb bHWTPITrL5MNXS5B8o+sylcHX20jz0Y+uX+cTZOdirKY5oyr7urEQlInMb3m/su863rE 9QhtgRgP/fJosWhwYGL8MVvOmRz4v/tekU0+3E3jJLg7ZCywP05UTO73WdkToEWM2aVr TmKjintsJd/Se3plcrNqkiJ180wix63MKXEkZ4RtC7cC68WWZ7DISgKkgfTOxea6D9+g nv/D5hOAuVMSlgRYnAIdAU3CjxhsXgB9E8Cck4TnImz8s37pdFx365nxpKoVttMp6Gh5 V1Xg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680350103; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EcTVfYVJVvyjT/gmTGLxErkT9wedlUsEwNFe3X7+hGY=; b=euzucTSOR/SZfjv+v90w2PHBKeiJWTHLz8SB8kj2mfP2orEauKVO5rsoNkDjc0Sz9u cz8DnQbQqaogwd3qBarZUiRDUtdfz52bVPegj+G+mvhnV47OaETvwwtyVA47lkVWtsiQ M6jo5nuKcKKWsUmfhie8djz+TitjFlaFCUGYLfqxzDiieW8QX8IxETTCapeXshKf2vtj g68bYCRNmNDl7Q58mwK7Xumz48m2tHmMluyFKgWLEJsJhVlIrdlu/Su5iCUxyi2b8pED 72wVljURaEY6tqactFfc/aqJ8koKidmK3Aj6WrOT2Z3tzF7oOibbVX0jCsOBF08C2I3x p7Ag== X-Gm-Message-State: AAQBX9eHVAp5ZffJ/tVRH62PHIrNQSBTZ/fcUQT0IclVqfugSA1Tuvyb Ote6ua06JC8fSIwIaWCUytX7nA== X-Google-Smtp-Source: AKy350Yl4KFVVTWJFWuvgEtM0wVoUGH4cdifEepaRt7ptUVvt8TwfVlOO80MecIzIYVBlstcD8zjjw== X-Received: by 2002:ac2:4824:0:b0:4e8:487a:7c2e with SMTP id 4-20020ac24824000000b004e8487a7c2emr3686636lft.14.1680350102999; Sat, 01 Apr 2023 04:55:02 -0700 (PDT) Received: from [192.168.1.101] (abxj225.neoplus.adsl.tpnet.pl. [83.9.3.225]) by smtp.gmail.com with ESMTPSA id w8-20020ac254a8000000b004e83f386878sm786737lfk.153.2023.04.01.04.55.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Apr 2023 04:55:02 -0700 (PDT) From: Konrad Dybcio Date: Sat, 01 Apr 2023 13:54:42 +0200 Subject: [PATCH v6 05/15] drm/msm/a6xx: Extend and explain UBWC config MIME-Version: 1.0 Message-Id: <20230223-topic-gmuwrapper-v6-5-2034115bb60c@linaro.org> References: <20230223-topic-gmuwrapper-v6-0-2034115bb60c@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v6-0-2034115bb60c@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1680350084; l=3025; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=O39lrV4yksGqUskcsqJEvIhhEigi/fA6XvvXYO4w5ps=; b=myh8HvfU5eZVgXTCg2b20N3sNNDdu2Vt9J1nGW840mDCgn7ouXLFoojuTVVlFz4Gv+4vDv130JlZ AuIMwbCbCZNPiZ/ewcioNX4dUYGWfQyHbeXMSj3a1dotlSrhM8q7 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Rename lower_bit to hbb_lo and explain what it signifies. Add explanations (wherever possible to other tunables). Port setting min_access_length, ubwc_mode and hbb_hi from downstream. Reviewed-by: Rob Clark Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 39 +++++++++++++++++++++++++++-------- 1 file changed, 30 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index a501654fd8bd..931f9f3b3a85 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -786,10 +786,25 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu) static void a6xx_set_ubwc_config(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); - u32 lower_bit = 2; - u32 amsbc = 0; + /* Unknown, introduced with A650 family, related to UBWC mode/ver 4 */ u32 rgb565_predicator = 0; + /* Unknown, introduced with A650 family */ u32 uavflagprd_inv = 0; + /* Whether the minimum access length is 64 bits */ + u32 min_acc_len = 0; + /* Entirely magic, per-GPU-gen value */ + u32 ubwc_mode = 0; + /* + * The Highest Bank Bit value represents the bit of the highest DDR bank. + * We then subtract 13 from it (13 is the minimum value allowed by hw) and + * write the lowest two bits of the remaining value as hbb_lo and the + * one above it as hbb_hi to the hardware. This should ideally use DRAM + * type detection. + */ + u32 hbb_hi = 0; + u32 hbb_lo = 2; + /* Unknown, introduced with A640/680 */ + u32 amsbc = 0; /* a618 is using the hw default values */ if (adreno_is_a618(adreno_gpu)) @@ -800,25 +815,31 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu)) { /* TODO: get ddr type from bootloader and use 2 for LPDDR4 */ - lower_bit = 3; + hbb_lo = 3; amsbc = 1; rgb565_predicator = 1; uavflagprd_inv = 2; } if (adreno_is_7c3(adreno_gpu)) { - lower_bit = 1; + hbb_lo = 1; amsbc = 1; rgb565_predicator = 1; uavflagprd_inv = 2; } gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL, - rgb565_predicator << 11 | amsbc << 4 | lower_bit << 1); - gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, lower_bit << 1); - gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, - uavflagprd_inv << 4 | lower_bit << 1); - gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, lower_bit << 21); + rgb565_predicator << 11 | hbb_hi << 10 | amsbc << 4 | + min_acc_len << 3 | hbb_lo << 1 | ubwc_mode); + + gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, hbb_hi << 4 | + min_acc_len << 3 | hbb_lo << 1 | ubwc_mode); + + gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, hbb_hi << 10 | + uavflagprd_inv << 4 | min_acc_len << 3 | + hbb_lo << 1 | ubwc_mode); + + gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, min_acc_len << 23 | hbb_lo << 21); } static int a6xx_cp_init(struct msm_gpu *gpu) From patchwork Sat Apr 1 11:54:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 669443 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DFA75C6FD1D for ; Sat, 1 Apr 2023 11:55:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230016AbjDALze (ORCPT ); Sat, 1 Apr 2023 07:55:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52470 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229982AbjDALzS (ORCPT ); Sat, 1 Apr 2023 07:55:18 -0400 Received: from mail-lf1-x12e.google.com (mail-lf1-x12e.google.com [IPv6:2a00:1450:4864:20::12e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 356881E728 for ; Sat, 1 Apr 2023 04:55:08 -0700 (PDT) Received: by mail-lf1-x12e.google.com with SMTP id h11so25261686lfu.8 for ; Sat, 01 Apr 2023 04:55:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680350106; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=BU8EEQ/1XcQ7vkQQH3yJxVyW9Kgb5rvCb81LF725+nc=; b=LO613yA2wO47UxewpWqLnEHS8wwUGUBngfYi39NINQjTg5HIhKLkWRnhQtg3yxrvwt o3tbX3/VRf74FQjAvmlP1bMQmQEflA1LhTcVnao4ApDhdWyetEHsCu2X75RgFTnOFQvK P+c8UBa7TUPK6fDuBKEDSGFhPJ9zHHlqOxgfftdPLNhbfFHD8WXcdwD+KfCXpnqSQybE 1hbfsoBqqUbU0A5uHG6OYvbPEwIo4Mg4DgYFhNi1bjgEGqZlDTSjLxpxSR7gPGWnpyct T2UAV4B7s7wpu+W0IviGVwR0OtGL0KcGmYJC0I3tESWBqAh3FYDhHkkJG1RmzNuWcj1b 9H4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680350106; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BU8EEQ/1XcQ7vkQQH3yJxVyW9Kgb5rvCb81LF725+nc=; b=IvN4eF4N+GVdya3wrUMt+dtdWflMzwLqvsocVBt/5MwDw51CD0MnNoFQpP1f+mx0Dp 0yWODM+FThwI5374xzaXKdRo3SGFnMR3DeYDqjc4Y3QZeRzXHMGP+0oLS7tdrLcJNthN kNiFkGGAHi7Xl/g04UBS70iKGrYe18L9jdp1iwpsAFMPgE3F4LLwztmsWT1mVgLB/9Vl DdiEAVA/Y2pd4boTUEVeGRSvp+1xLRIcAX+YjsqKZeRicUxiATF+0PSwFvpFYX45b3zP 0WxJ3mnZmZFBjoL/Zg14fVasYA8aB3yyBS143qxaKpNvpB3yT9fuZYXj91ufXZDQUEPy ECDA== X-Gm-Message-State: AAQBX9fKpHJFnCz1dFO+8PenahSpWS3UYg8dbhqmX1smt+iHWImyLOHY JRp2yoE6ovTBC1Jpgva+YcLIMw== X-Google-Smtp-Source: AKy350by0LYVn7wfvRGqoI1MvqYKXNoMlMG8tg/3dWfJ53Zt5C1vSQVT5F2Zv3buazHUaV8OeFYKKQ== X-Received: by 2002:ac2:51a1:0:b0:4d8:8273:ec with SMTP id f1-20020ac251a1000000b004d8827300ecmr8837332lfk.20.1680350105926; Sat, 01 Apr 2023 04:55:05 -0700 (PDT) Received: from [192.168.1.101] (abxj225.neoplus.adsl.tpnet.pl. [83.9.3.225]) by smtp.gmail.com with ESMTPSA id w8-20020ac254a8000000b004e83f386878sm786737lfk.153.2023.04.01.04.55.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Apr 2023 04:55:05 -0700 (PDT) From: Konrad Dybcio Date: Sat, 01 Apr 2023 13:54:43 +0200 Subject: [PATCH v6 06/15] drm/msm/a6xx: Introduce GMU wrapper support MIME-Version: 1.0 Message-Id: <20230223-topic-gmuwrapper-v6-6-2034115bb60c@linaro.org> References: <20230223-topic-gmuwrapper-v6-0-2034115bb60c@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v6-0-2034115bb60c@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1680350084; l=21159; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=hhoI6JSL7f6Vh5CT5I4WlLhDXEEuV3ShzzKoDnYzbxI=; b=UjVSoVYqHObITp/ORN3aSS4DdYbNxJMQs+CrdLOdOKlaop2eH0U3OcFDBzUXyMbgph235Oy/sxZB Q2SupTElCNaIJkSJ5S3rEeYHGYa5TGzUd0lvvuKivQywm8z0CiwG X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Some (particularly SMD_RPM, a.k.a non-RPMh) SoCs implement A6XX GPUs but don't implement the associated GMUs. This is due to the fact that the GMU directly pokes at RPMh. Sadly, this means we have to take care of enabling & scaling power rails, clocks and bandwidth ourselves. Reuse existing Adreno-common code and modify the deeply-GMU-infused A6XX code to facilitate these GPUs. This involves if-ing out lots of GMU callbacks and introducing a new type of GMU - GMU wrapper (it's the actual name that Qualcomm uses in their downstream kernels). This is essentially a register region which is convenient to model as a device. We'll use it for managing the GDSCs. The register layout matches the actual GMU_CX/GX regions on the "real GMU" devices and lets us reuse quite a bit of gmu_read/write/rmw calls. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 72 +++++++- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 255 +++++++++++++++++++++++++--- drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 + drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 14 +- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 8 +- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 6 + 6 files changed, 318 insertions(+), 38 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index 87babbb2a19f..b1acdb027205 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -1469,6 +1469,7 @@ static int a6xx_gmu_get_irq(struct a6xx_gmu *gmu, struct platform_device *pdev, void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu) { + struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; struct a6xx_gmu *gmu = &a6xx_gpu->gmu; struct platform_device *pdev = to_platform_device(gmu->dev); @@ -1494,10 +1495,12 @@ void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu) gmu->mmio = NULL; gmu->rscc = NULL; - a6xx_gmu_memory_free(gmu); + if (!adreno_has_gmu_wrapper(adreno_gpu)) { + a6xx_gmu_memory_free(gmu); - free_irq(gmu->gmu_irq, gmu); - free_irq(gmu->hfi_irq, gmu); + free_irq(gmu->gmu_irq, gmu); + free_irq(gmu->hfi_irq, gmu); + } /* Drop reference taken in of_find_device_by_node */ put_device(gmu->dev); @@ -1516,6 +1519,69 @@ static int cxpd_notifier_cb(struct notifier_block *nb, return 0; } +int a6xx_gmu_wrapper_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node) +{ + struct platform_device *pdev = of_find_device_by_node(node); + struct a6xx_gmu *gmu = &a6xx_gpu->gmu; + int ret; + + if (!pdev) + return -ENODEV; + + gmu->dev = &pdev->dev; + + of_dma_configure(gmu->dev, node, true); + + pm_runtime_enable(gmu->dev); + + /* Mark legacy for manual SPTPRAC control */ + gmu->legacy = true; + + /* Map the GMU registers */ + gmu->mmio = a6xx_gmu_get_mmio(pdev, "gmu"); + if (IS_ERR(gmu->mmio)) { + ret = PTR_ERR(gmu->mmio); + goto err_mmio; + } + + gmu->cxpd = dev_pm_domain_attach_by_name(gmu->dev, "cx"); + if (IS_ERR(gmu->cxpd)) { + ret = PTR_ERR(gmu->cxpd); + goto err_mmio; + } + + if (!device_link_add(gmu->dev, gmu->cxpd, DL_FLAG_PM_RUNTIME)) { + ret = -ENODEV; + goto detach_cxpd; + } + + init_completion(&gmu->pd_gate); + complete_all(&gmu->pd_gate); + gmu->pd_nb.notifier_call = cxpd_notifier_cb; + + /* Get a link to the GX power domain to reset the GPU */ + gmu->gxpd = dev_pm_domain_attach_by_name(gmu->dev, "gx"); + if (IS_ERR(gmu->gxpd)) { + ret = PTR_ERR(gmu->gxpd); + goto err_mmio; + } + + gmu->initialized = true; + + return 0; + +detach_cxpd: + dev_pm_domain_detach(gmu->cxpd, false); + +err_mmio: + iounmap(gmu->mmio); + + /* Drop reference taken in of_find_device_by_node */ + put_device(gmu->dev); + + return ret; +} + int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node) { struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 931f9f3b3a85..8e0345ffab81 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -20,9 +20,11 @@ static inline bool _a6xx_check_idle(struct msm_gpu *gpu) struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); - /* Check that the GMU is idle */ - if (!a6xx_gmu_isidle(&a6xx_gpu->gmu)) - return false; + if (!adreno_has_gmu_wrapper(adreno_gpu)) { + /* Check that the GMU is idle */ + if (!a6xx_gmu_isidle(&a6xx_gpu->gmu)) + return false; + } /* Check tha the CX master is idle */ if (gpu_read(gpu, REG_A6XX_RBBM_STATUS) & @@ -612,13 +614,15 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state) return; /* Disable SP clock before programming HWCG registers */ - gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 1, 0); + if (!adreno_has_gmu_wrapper(adreno_gpu)) + gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 1, 0); for (i = 0; (reg = &adreno_gpu->info->hwcg[i], reg->offset); i++) gpu_write(gpu, reg->offset, state ? reg->value : 0); /* Enable SP clock */ - gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 0, 1); + if (!adreno_has_gmu_wrapper(adreno_gpu)) + gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 0, 1); gpu_write(gpu, REG_A6XX_RBBM_CLOCK_CNTL, state ? clock_cntl_on : 0); } @@ -1018,10 +1022,13 @@ static int hw_init(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); + struct a6xx_gmu *gmu = &a6xx_gpu->gmu; int ret; - /* Make sure the GMU keeps the GPU on while we set it up */ - a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); + if (!adreno_has_gmu_wrapper(adreno_gpu)) { + /* Make sure the GMU keeps the GPU on while we set it up */ + a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); + } /* Clear GBIF halt in case GX domain was not collapsed */ if (a6xx_has_gbif(adreno_gpu)) @@ -1144,6 +1151,17 @@ static int hw_init(struct msm_gpu *gpu) 0x3f0243f0); } + if (adreno_has_gmu_wrapper(adreno_gpu)) { + /* Do it here, as GMU wrapper only inits the GMU for memory reservation etc. */ + + /* Set up the CX GMU counter 0 to count busy ticks */ + gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_MASK, 0xff000000); + + /* Enable power counter 0 */ + gmu_rmw(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0, 0xff, BIT(5)); + gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 1); + } + /* Protect registers from the CP */ a6xx_set_cp_protect(gpu); @@ -1233,6 +1251,8 @@ static int hw_init(struct msm_gpu *gpu) } out: + if (adreno_has_gmu_wrapper(adreno_gpu)) + return ret; /* * Tell the GMU that we are done touching the GPU and it can start power * management @@ -1267,6 +1287,9 @@ static void a6xx_dump(struct msm_gpu *gpu) adreno_dump(gpu); } +#define GBIF_GX_HALT_MASK BIT(0) +#define GBIF_CLIENT_HALT_MASK BIT(0) +#define GBIF_ARB_HALT_MASK BIT(1) #define VBIF_RESET_ACK_TIMEOUT 100 #define VBIF_RESET_ACK_MASK 0x00f0 @@ -1299,7 +1322,8 @@ static void a6xx_recover(struct msm_gpu *gpu) * Turn off keep alive that might have been enabled by the hang * interrupt */ - gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 0); + if (!adreno_has_gmu_wrapper(adreno_gpu)) + gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 0); pm_runtime_dont_use_autosuspend(&gpu->pdev->dev); @@ -1329,6 +1353,32 @@ static void a6xx_recover(struct msm_gpu *gpu) dev_pm_genpd_remove_notifier(gmu->cxpd); + /* Software-reset the GPU */ + if (adreno_has_gmu_wrapper(adreno_gpu)) { + /* Halt the GX side of GBIF */ + gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, GBIF_GX_HALT_MASK); + spin_until(gpu_read(gpu, REG_A6XX_RBBM_GBIF_HALT_ACK) & + GBIF_GX_HALT_MASK); + + /* Halt new client requests on GBIF */ + gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_CLIENT_HALT_MASK); + spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) & + (GBIF_CLIENT_HALT_MASK)) == GBIF_CLIENT_HALT_MASK); + + /* Halt all AXI requests on GBIF */ + gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_ARB_HALT_MASK); + spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) & + (GBIF_ARB_HALT_MASK)) == GBIF_ARB_HALT_MASK); + + /* Clear the halts */ + gpu_write(gpu, REG_A6XX_GBIF_HALT, 0); + + gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, 0); + + /* This *really* needs to go through before we do anything else! */ + mb(); + } + pm_runtime_use_autosuspend(&gpu->pdev->dev); if (active_submits) @@ -1463,7 +1513,8 @@ static void a6xx_fault_detect_irq(struct msm_gpu *gpu) * Force the GPU to stay on until after we finish * collecting information */ - gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 1); + if (!adreno_has_gmu_wrapper(adreno_gpu)) + gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 1); DRM_DEV_ERROR(&gpu->pdev->dev, "gpu fault ring %d fence %x status %8.8X rb %4.4x/%4.4x ib1 %16.16llX/%4.4x ib2 %16.16llX/%4.4x\n", @@ -1624,7 +1675,7 @@ static void a6xx_llc_slices_init(struct platform_device *pdev, a6xx_gpu->llc_mmio = ERR_PTR(-EINVAL); } -static int a6xx_pm_resume(struct msm_gpu *gpu) +static int a6xx_gmu_pm_resume(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); @@ -1644,10 +1695,61 @@ static int a6xx_pm_resume(struct msm_gpu *gpu) a6xx_llc_activate(a6xx_gpu); - return 0; + return ret; } -static int a6xx_pm_suspend(struct msm_gpu *gpu) +static int a6xx_pm_resume(struct msm_gpu *gpu) +{ + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); + struct a6xx_gmu *gmu = &a6xx_gpu->gmu; + unsigned long freq = 0; + struct dev_pm_opp *opp; + int ret; + + gpu->needs_hw_init = true; + + trace_msm_gpu_resume(0); + + mutex_lock(&a6xx_gpu->gmu.lock); + + pm_runtime_resume_and_get(gmu->dev); + pm_runtime_resume_and_get(gmu->gxpd); + + /* Set the core clock, having VDD scaling in mind */ + ret = dev_pm_opp_set_rate(&gpu->pdev->dev, gpu->fast_rate); + if (ret) + goto err_core_clk; + + ret = clk_bulk_prepare_enable(gpu->nr_clocks, gpu->grp_clks); + if (ret) + goto err_bulk_clk; + + ret = clk_prepare_enable(gpu->ebi1_clk); + if (ret) + goto err_mem_clk; + + /* If anything goes south, tear the GPU down piece by piece.. */ + if (ret) { +err_mem_clk: + clk_bulk_disable_unprepare(gpu->nr_clocks, gpu->grp_clks); +err_bulk_clk: + opp = dev_pm_opp_find_freq_ceil(&gpu->pdev->dev, &freq); + dev_pm_opp_put(opp); + dev_pm_opp_set_rate(&gpu->pdev->dev, 0); +err_core_clk: + pm_runtime_put(gmu->gxpd); + pm_runtime_put(gmu->dev); + } + mutex_unlock(&a6xx_gpu->gmu.lock); + + if (!ret) + msm_devfreq_resume(gpu); + + return ret; +} + +static int a6xx_gmu_pm_suspend(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); @@ -1674,11 +1776,62 @@ static int a6xx_pm_suspend(struct msm_gpu *gpu) return 0; } +static int a6xx_pm_suspend(struct msm_gpu *gpu) +{ + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); + struct a6xx_gmu *gmu = &a6xx_gpu->gmu; + unsigned long freq = 0; + struct dev_pm_opp *opp; + int i, ret; + + trace_msm_gpu_suspend(0); + + opp = dev_pm_opp_find_freq_ceil(&gpu->pdev->dev, &freq); + dev_pm_opp_put(opp); + + msm_devfreq_suspend(gpu); + + mutex_lock(&a6xx_gpu->gmu.lock); + + clk_disable_unprepare(gpu->ebi1_clk); + + clk_bulk_disable_unprepare(gpu->nr_clocks, gpu->grp_clks); + + /* Set frequency to the minimum supported level (no 27MHz on A6xx!) */ + ret = dev_pm_opp_set_rate(&gpu->pdev->dev, freq); + if (ret) + goto err; + + pm_runtime_put_sync(gmu->gxpd); + pm_runtime_put_sync(gmu->dev); + + mutex_unlock(&a6xx_gpu->gmu.lock); + + if (a6xx_gpu->shadow_bo) + for (i = 0; i < gpu->nr_rings; i++) + a6xx_gpu->shadow[i] = 0; + + gpu->suspend_count++; + + return 0; + +err: + mutex_unlock(&a6xx_gpu->gmu.lock); + + return ret; +} + static int a6xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); + if (adreno_has_gmu_wrapper(adreno_gpu)) { + *value = gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER); + return 0; + } + mutex_lock(&a6xx_gpu->gmu.lock); /* Force the GPU power on so we can read this register */ @@ -1716,7 +1869,8 @@ static void a6xx_destroy(struct msm_gpu *gpu) drm_gem_object_put(a6xx_gpu->shadow_bo); } - a6xx_llc_slices_destroy(a6xx_gpu); + if (!adreno_has_gmu_wrapper(adreno_gpu)) + a6xx_llc_slices_destroy(a6xx_gpu); mutex_lock(&a6xx_gpu->gmu.lock); a6xx_gmu_remove(a6xx_gpu); @@ -1957,8 +2111,8 @@ static const struct adreno_gpu_funcs funcs = { .set_param = adreno_set_param, .hw_init = a6xx_hw_init, .ucode_load = a6xx_ucode_load, - .pm_suspend = a6xx_pm_suspend, - .pm_resume = a6xx_pm_resume, + .pm_suspend = a6xx_gmu_pm_suspend, + .pm_resume = a6xx_gmu_pm_resume, .recover = a6xx_recover, .submit = a6xx_submit, .active_ring = a6xx_active_ring, @@ -1982,6 +2136,35 @@ static const struct adreno_gpu_funcs funcs = { .get_timestamp = a6xx_get_timestamp, }; +static const struct adreno_gpu_funcs funcs_gmuwrapper = { + .base = { + .get_param = adreno_get_param, + .set_param = adreno_set_param, + .hw_init = a6xx_hw_init, + .ucode_load = a6xx_ucode_load, + .pm_suspend = a6xx_pm_suspend, + .pm_resume = a6xx_pm_resume, + .recover = a6xx_recover, + .submit = a6xx_submit, + .active_ring = a6xx_active_ring, + .irq = a6xx_irq, + .destroy = a6xx_destroy, +#if defined(CONFIG_DRM_MSM_GPU_STATE) + .show = a6xx_show, +#endif + .gpu_busy = a6xx_gpu_busy, +#if defined(CONFIG_DRM_MSM_GPU_STATE) + .gpu_state_get = a6xx_gpu_state_get, + .gpu_state_put = a6xx_gpu_state_put, +#endif + .create_address_space = a6xx_create_address_space, + .create_private_address_space = a6xx_create_private_address_space, + .get_rptr = a6xx_get_rptr, + .progress = a6xx_progress, + }, + .get_timestamp = a6xx_get_timestamp, +}; + struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) { struct msm_drm_private *priv = dev->dev_private; @@ -2003,18 +2186,36 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) adreno_gpu->registers = NULL; + /* Check if there is a GMU phandle and set it up */ + node = of_parse_phandle(pdev->dev.of_node, "qcom,gmu", 0); + /* FIXME: How do we gracefully handle this? */ + BUG_ON(!node); + + adreno_gpu->gmu_is_wrapper = of_device_is_compatible(node, "qcom,adreno-gmu-wrapper"); + /* * We need to know the platform type before calling into adreno_gpu_init * so that the hw_apriv flag can be correctly set. Snoop into the info * and grab the revision number */ info = adreno_info(config->rev); - - if (info && (info->revn == 650 || info->revn == 660 || - adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), info->rev))) + if (!info) + return ERR_PTR(-EINVAL); + + /* Assign these early so that we can use the is_aXYZ helpers */ + /* Numeric revision IDs (e.g. 630) */ + adreno_gpu->revn = info->revn; + /* New-style ADRENO_REV()-only */ + adreno_gpu->rev = info->rev; + /* Quirk data */ + adreno_gpu->info = info; + + if (adreno_is_a650(adreno_gpu) || adreno_is_a660_family(adreno_gpu)) adreno_gpu->base.hw_apriv = true; - a6xx_llc_slices_init(pdev, a6xx_gpu); + /* No LLCC on non-RPMh (and by extension, non-GMU) SoCs */ + if (!adreno_has_gmu_wrapper(adreno_gpu)) + a6xx_llc_slices_init(pdev, a6xx_gpu); ret = a6xx_set_supported_hw(&pdev->dev, config->rev); if (ret) { @@ -2022,7 +2223,10 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) return ERR_PTR(ret); } - ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1); + if (adreno_has_gmu_wrapper(adreno_gpu)) + ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_gmuwrapper, 1); + else + ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1); if (ret) { a6xx_destroy(&(a6xx_gpu->base.base)); return ERR_PTR(ret); @@ -2035,13 +2239,10 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) if (adreno_is_a618(adreno_gpu) || adreno_is_7c3(adreno_gpu)) priv->gpu_clamp_to_idle = true; - /* Check if there is a GMU phandle and set it up */ - node = of_parse_phandle(pdev->dev.of_node, "qcom,gmu", 0); - - /* FIXME: How do we gracefully handle this? */ - BUG_ON(!node); - - ret = a6xx_gmu_init(a6xx_gpu, node); + if (adreno_has_gmu_wrapper(adreno_gpu)) + ret = a6xx_gmu_wrapper_init(a6xx_gpu, node); + else + ret = a6xx_gmu_init(a6xx_gpu, node); of_node_put(node); if (ret) { a6xx_destroy(&(a6xx_gpu->base.base)); diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h index eea2e60ce3b7..51a7656072fa 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h @@ -76,6 +76,7 @@ int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state); void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state); int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node); +int a6xx_gmu_wrapper_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node); void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu); void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp, diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c index 30ecdff363e7..4e5d650578c6 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c @@ -1041,16 +1041,18 @@ struct msm_gpu_state *a6xx_gpu_state_get(struct msm_gpu *gpu) /* Get the generic state from the adreno core */ adreno_gpu_state_get(gpu, &a6xx_state->base); - a6xx_get_gmu_registers(gpu, a6xx_state); + if (!adreno_has_gmu_wrapper(adreno_gpu)) { + a6xx_get_gmu_registers(gpu, a6xx_state); - a6xx_state->gmu_log = a6xx_snapshot_gmu_bo(a6xx_state, &a6xx_gpu->gmu.log); - a6xx_state->gmu_hfi = a6xx_snapshot_gmu_bo(a6xx_state, &a6xx_gpu->gmu.hfi); - a6xx_state->gmu_debug = a6xx_snapshot_gmu_bo(a6xx_state, &a6xx_gpu->gmu.debug); + a6xx_state->gmu_log = a6xx_snapshot_gmu_bo(a6xx_state, &a6xx_gpu->gmu.log); + a6xx_state->gmu_hfi = a6xx_snapshot_gmu_bo(a6xx_state, &a6xx_gpu->gmu.hfi); + a6xx_state->gmu_debug = a6xx_snapshot_gmu_bo(a6xx_state, &a6xx_gpu->gmu.debug); - a6xx_snapshot_gmu_hfi_history(gpu, a6xx_state); + a6xx_snapshot_gmu_hfi_history(gpu, a6xx_state); + } /* If GX isn't on the rest of the data isn't going to be accessible */ - if (!a6xx_gmu_gx_is_on(&a6xx_gpu->gmu)) + if (!adreno_has_gmu_wrapper(adreno_gpu) && !a6xx_gmu_gx_is_on(&a6xx_gpu->gmu)) return &a6xx_state->base; /* Get the banks of indexed registers */ diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index 6934cee07d42..5c5901d65950 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -528,6 +528,10 @@ int adreno_load_fw(struct adreno_gpu *adreno_gpu) if (!adreno_gpu->info->fw[i]) continue; + /* Skip loading GMU firwmare with GMU Wrapper */ + if (adreno_has_gmu_wrapper(adreno_gpu) && i == ADRENO_FW_GMU) + continue; + /* Skip if the firmware has already been loaded */ if (adreno_gpu->fw[i]) continue; @@ -1074,8 +1078,8 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, u32 speedbin; int ret; - /* Only handle the core clock when GMU is not in use */ - if (config->rev.core < 6) { + /* Only handle the core clock when GMU is not in use (or is absent). */ + if (adreno_has_gmu_wrapper(adreno_gpu) || config->rev.core < 6) { /* * This can only be done before devm_pm_opp_of_add_table(), or * dev_pm_opp_set_config() will WARN_ON() diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index f62612a5c70f..ee5352bc5329 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -115,6 +115,7 @@ struct adreno_gpu { * code (a3xx_gpu.c) and stored in this common location. */ const unsigned int *reg_offsets; + bool gmu_is_wrapper; }; #define to_adreno_gpu(x) container_of(x, struct adreno_gpu, base) @@ -145,6 +146,11 @@ struct adreno_platform_config { bool adreno_cmp_rev(struct adreno_rev rev1, struct adreno_rev rev2); +static inline bool adreno_has_gmu_wrapper(struct adreno_gpu *gpu) +{ + return gpu->gmu_is_wrapper; +} + static inline bool adreno_is_a2xx(struct adreno_gpu *gpu) { return (gpu->revn < 300); From patchwork Sat Apr 1 11:54:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 669665 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B16FBC77B6D for ; Sat, 1 Apr 2023 11:55:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229562AbjDALzh (ORCPT ); Sat, 1 Apr 2023 07:55:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52592 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229894AbjDALzV (ORCPT ); Sat, 1 Apr 2023 07:55:21 -0400 Received: from mail-lf1-x134.google.com (mail-lf1-x134.google.com [IPv6:2a00:1450:4864:20::134]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5DD5624AEE for ; Sat, 1 Apr 2023 04:55:09 -0700 (PDT) Received: by mail-lf1-x134.google.com with SMTP id x17so32258432lfu.5 for ; Sat, 01 Apr 2023 04:55:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680350109; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=TqvvserEEXfM7bfoSIgCSJ4UIeQQqPEniXobIbd6OmA=; b=MfjdIHHRqsbWEVlfHK0yGymcYsI7duJyM63jJzDNNQPTU0pcfN9iep6PvHm3ABq5dj F/dtRF4FNAA086+KXdcWwmyDia1xv8k+i+kr2LOmzkTMltgWxJJcUedkQApqV1qh27R7 X2/8+VksnkZ2CuSP+WPcBRMwX0Wsh54fhS/j30VEZwJf2UQI6Z5HCi8JEHZ7NJ74s2VH w7m6t20chxaDnJhIptbRR8sc5YK9KdXqiZl0OsD+isjFwI5F7KuK1tXja3JPNPjbYEXS 3aPLmix353GOLFIfD+oTKaZuiZTgZ75+9+XM1Qi8A2GWJBE6URjPzNLYfA/VTJl4/W6S MAfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680350109; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TqvvserEEXfM7bfoSIgCSJ4UIeQQqPEniXobIbd6OmA=; b=oF2UsmmNYDNVGklqEXZxvR9vIWyT0ekvMMa9LeRnhEMA3l7iI91pWLgNYsE89AJsRW jOd7JAMJ7ZeRJOtCHLr/4QlHEfyMn7cgL907IzuC4ypoDj42FHQg7sXlpZiWGDHMb2L7 pNW2hIIVOlAvTg8cqBxN5V3wAoV3fYAdgsDZuSuUGrE/PqI5J4hQycvMGvZ/FJg+044l +LL5GDL7OLwNt9MHVsh3kSU3mwdHW9ZTfK3WvaKzYtOMHQXpTcQD0xHsTGJnz44tzjnQ wzrLLinAfUy1Q7Pg9JTZo3qSitcVHTDHsg3xAK9It9EhqdqZxJUWA6FZd8aQ7BTdiEXn sDhw== X-Gm-Message-State: AAQBX9doU07hLLl8LxJHZsbkXIKPJh7i/V1ub1tqRoLXY9D2W8hnvs8n EeQ1FcvSC8UOA8EUai1F/oyK/g== X-Google-Smtp-Source: AKy350ZKsnq/mrUrLvubE5qPEGQ/Cxi2AShVFNWxCEZi7DwG0jehzrqC/mrcfTHsYp8T63gYlCU9lA== X-Received: by 2002:a19:c51a:0:b0:4de:3c94:da15 with SMTP id w26-20020a19c51a000000b004de3c94da15mr9296547lfe.4.1680350108727; Sat, 01 Apr 2023 04:55:08 -0700 (PDT) Received: from [192.168.1.101] (abxj225.neoplus.adsl.tpnet.pl. [83.9.3.225]) by smtp.gmail.com with ESMTPSA id w8-20020ac254a8000000b004e83f386878sm786737lfk.153.2023.04.01.04.55.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Apr 2023 04:55:08 -0700 (PDT) From: Konrad Dybcio Date: Sat, 01 Apr 2023 13:54:44 +0200 Subject: [PATCH v6 07/15] drm/msm/a6xx: Remove both GBIF and RBBM GBIF halt on hw init MIME-Version: 1.0 Message-Id: <20230223-topic-gmuwrapper-v6-7-2034115bb60c@linaro.org> References: <20230223-topic-gmuwrapper-v6-0-2034115bb60c@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v6-0-2034115bb60c@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1680350084; l=1312; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=LfJKI18ku3LCGvhXVjTfawfZ9xevg/d8d9jIr1dnQAM=; b=CV/tjUnURsDiZN4KzTdlbV/FyDcpzvhj9HHJ4JsESoZynabtlFtD5aJ2O1Zi5t0SpVVptHxNEgVF xPBV/dlRBEBxymgIl8ldYKixPvQxBkelTh8mkZowc9zhAnRmgELD X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Currently we're only deasserting REG_A6XX_RBBM_GBIF_HALT, but we also need REG_A6XX_GBIF_HALT to be set to 0. For GMU-equipped GPUs this is done in a6xx_bus_clear_pending_transactions(), but for the GMU-less ones we have to do it *somewhere*. Unhalting both side by side sounds like a good plan and it won't cause any issues if it's unnecessary. Also, add a memory barrier to ensure it's gone through. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 8e0345ffab81..17e314a745c3 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1031,8 +1031,12 @@ static int hw_init(struct msm_gpu *gpu) } /* Clear GBIF halt in case GX domain was not collapsed */ - if (a6xx_has_gbif(adreno_gpu)) + if (a6xx_has_gbif(adreno_gpu)) { + gpu_write(gpu, REG_A6XX_GBIF_HALT, 0); gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, 0); + /* Let's make extra sure that the GPU can access the memory.. */ + mb(); + } gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_CNTL, 0); From patchwork Sat Apr 1 11:54:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 669442 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C74D5C761AF for ; Sat, 1 Apr 2023 11:55:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230081AbjDALzv (ORCPT ); Sat, 1 Apr 2023 07:55:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52210 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229947AbjDALza (ORCPT ); Sat, 1 Apr 2023 07:55:30 -0400 Received: from mail-lf1-x12c.google.com (mail-lf1-x12c.google.com [IPv6:2a00:1450:4864:20::12c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 397B924AD2 for ; Sat, 1 Apr 2023 04:55:13 -0700 (PDT) Received: by mail-lf1-x12c.google.com with SMTP id g19so19114021lfr.9 for ; Sat, 01 Apr 2023 04:55:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680350111; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=ifhrbShC7+juhdrM7tSPSmIe9BvFlsZ4IeJyZGUcR1w=; b=t3FWIRjFKkx2JGZv4wZqYWLGC53QNHQPYM2XqLu8rcG+v808heG6inHMxujip9i9TK NGy6evo9wHZqV3omXLiTO5MyoWY69eKT81cPD5Fg8gXUpF8NdBfqKO3aTwXmpnWp+T3I nFUYtBCqZdcDDGRek47/cv0cpCvNws0xMPWt2GPL2yyQ0IMz8w7z9k6U8C4xe1FkeSu6 t/i1veutCJuhgmxKl/vx7k8snA3zcqx7E1zNbbJ0GLFc1ISrX/Ks+8Hrmcm1sGR5uBHa loS3v8zY6ZZOgkjdKJKmQkU0UeVE2MkcCDnxV95qFsaeyOYm4DsNrhELa9FDoD/Oq5dK LKkw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680350111; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ifhrbShC7+juhdrM7tSPSmIe9BvFlsZ4IeJyZGUcR1w=; b=y9PpN6FcuyY3XBSKluJLN5ST6Fdoq5TgIIK5shWNT4KUuwNNX3ST2BOHohkmOcg7rK x3DmZt7UUC0mwlcLj9dcyWi0IVFs42t6+9Ouy+fvGAdYgTJzB0YSCzcM4pWU4VG1N+yj j1sNiG4X1wgw7AibTXWd0F5V3Hg/XhQMEdGckmUeaUylTYl+LKxzqZW0eARedYzwQbMT w2OAwM7dhHe4b/SxkS8Aup0o2LUvaVAe/9D69ADi/og49VEC36vEesTJM8DaigrH6fMU y8fKG2UQ2/2pxB/iQ5jKFdbKfEpwGISKywwjY0kYrNy0euMxf0dQhASfP/90j4Aaktww P3EQ== X-Gm-Message-State: AAQBX9cDrRlWPMYcLv70JU6lRKgZqfWALVZbpanrgPhFuCMrfunk+Sg6 Al2YoOZcTG/SPz97ZaBhuL2qug== X-Google-Smtp-Source: AKy350a11lcjS0h/eZP2Fw6OpWyaX8WRZkquSON+2y9iqlGDGCqkSRGCzQDR1b65rDEhnI1DHsO9Iw== X-Received: by 2002:ac2:5482:0:b0:4b5:8f03:a2bc with SMTP id t2-20020ac25482000000b004b58f03a2bcmr8649139lfk.9.1680350111509; Sat, 01 Apr 2023 04:55:11 -0700 (PDT) Received: from [192.168.1.101] (abxj225.neoplus.adsl.tpnet.pl. [83.9.3.225]) by smtp.gmail.com with ESMTPSA id w8-20020ac254a8000000b004e83f386878sm786737lfk.153.2023.04.01.04.55.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Apr 2023 04:55:11 -0700 (PDT) From: Konrad Dybcio Date: Sat, 01 Apr 2023 13:54:45 +0200 Subject: [PATCH v6 08/15] drm/msm/adreno: Disable has_cached_coherent in GMU wrapper configurations MIME-Version: 1.0 Message-Id: <20230223-topic-gmuwrapper-v6-8-2034115bb60c@linaro.org> References: <20230223-topic-gmuwrapper-v6-0-2034115bb60c@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v6-0-2034115bb60c@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1680350084; l=1374; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=Uy9xduAlMWK2dLdqx78UuoS6GjnaBPbaxTCDUXSqNNk=; b=WbgMypqr8VbfjFpGDgyRqDk0vGFsrUY/gNWlfqaZQ2JlGKoTnt8e9m+Zkw6fJpFD0wul+XOiavpo yz5f2dmyAjAUqze+TnpY+c6yeGpi9YcCLzUgTP7glEDXgHbuUsO3 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org A610 and A619_holi don't support the feature. Disable it to make the GPU stop crashing after almost each and every submission - the received data on the GPU end was simply incomplete in garbled, resulting in almost nothing being executed properly. Extend the disablement to adreno_has_gmu_wrapper, as none of the GMU wrapper Adrenos that don't support yet seem to feature it. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/adreno_device.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index 4d1448714285..4705ce3eb95e 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -551,7 +551,6 @@ static int adreno_bind(struct device *dev, struct device *master, void *data) config.rev.minor, config.rev.patchid); priv->is_a2xx = config.rev.core == 2; - priv->has_cached_coherent = config.rev.core >= 6; gpu = info->init(drm); if (IS_ERR(gpu)) { @@ -563,6 +562,10 @@ static int adreno_bind(struct device *dev, struct device *master, void *data) if (ret) return ret; + if (config.rev.core >= 6) + if (!adreno_has_gmu_wrapper(to_adreno_gpu(gpu))) + priv->has_cached_coherent = true; + return 0; } From patchwork Sat Apr 1 11:54:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 669664 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 722D0C77B61 for ; Sat, 1 Apr 2023 11:55:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230086AbjDALzz (ORCPT ); Sat, 1 Apr 2023 07:55:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51732 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229924AbjDALzf (ORCPT ); Sat, 1 Apr 2023 07:55:35 -0400 Received: from mail-lf1-x135.google.com (mail-lf1-x135.google.com [IPv6:2a00:1450:4864:20::135]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 87298265BC for ; Sat, 1 Apr 2023 04:55:15 -0700 (PDT) Received: by mail-lf1-x135.google.com with SMTP id h11so25261926lfu.8 for ; Sat, 01 Apr 2023 04:55:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680350113; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=/AveNVS90BbixbsT3Hw8pttX0Kjo8MGgQJUSc1CubkM=; b=r1VMGlD/JaOY6H5LFK+DfCNncPEUrIsfr37GCejQxyn9nPaiQeWtrtUXXf8s4GKOxi 7ty6QNq5iMmE9h5VJ5YJ/9lBSaak0AvuacYALS3RJcLOsPAB1JnOKlvMIe6JAaaAO9hT VKJuK4H54UnJZWFT0IRBAC06taxKql7RZopJFULhPd2eL6TdTPEksMeRF/nOtyyl+PKj Ix7T/I8x3GjEOH2uNcTuPELtsMIpq1pf/cMy2aNxUunkJ7W0XAZYWt12DAa3BDd1vPhM ocTU9MKHXUTONkrHei0sZ1yqMaKZW0NXcsNFby+2SMMFMHfjJ3bLLpVhnOpnKVi5JPvr BuPg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680350113; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/AveNVS90BbixbsT3Hw8pttX0Kjo8MGgQJUSc1CubkM=; b=A0MgO8sn+EXMfOiZdJZ0w/l86rOVpqytnMbvayOp858EWIM5nthB93aOObpkVfODhm FriteSmvuTjh0MaKkAuPWr2WBF6swMTPyD8HO1aRwIEhEEUT0KoJjxrZodTcPxBd6lqS 7QLxlfEzDSVlLSQjaL0/urvZGGb2e6mwVt+UqF1+zYsAeA6TTHWjlEQz2j5CLJk1nHBt D1aWAp+PUyugq/p6qGpYm1B6kYEF08QQshz20zoGkDPniw0JqYVu6nvmK1NegMI3hWtl wT6mzozkb4B9AEXQ2h8eDTzLMX38goJzyNmxFXmBWYUCrdKtfdlsM7xirLNub0o3CtWu wB6g== X-Gm-Message-State: AAQBX9cUfpXUGWM83p6kMieapyWVG7llKUvMrbuY8AT95hgrYlyrgmdv FYeHQrDXoPtJ/cEy/TI+6CXabw== X-Google-Smtp-Source: AKy350b+H5PJ6wJk2RC5hbU8BM+KikBw2ugOy6n/cQlKZQllD0i5N1c9g6IyUSzGSJ4+T4jGJgyvMQ== X-Received: by 2002:ac2:44b0:0:b0:4b6:e494:a98d with SMTP id c16-20020ac244b0000000b004b6e494a98dmr8979801lfm.44.1680350113699; Sat, 01 Apr 2023 04:55:13 -0700 (PDT) Received: from [192.168.1.101] (abxj225.neoplus.adsl.tpnet.pl. [83.9.3.225]) by smtp.gmail.com with ESMTPSA id w8-20020ac254a8000000b004e83f386878sm786737lfk.153.2023.04.01.04.55.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Apr 2023 04:55:13 -0700 (PDT) From: Konrad Dybcio Date: Sat, 01 Apr 2023 13:54:46 +0200 Subject: [PATCH v6 09/15] drm/msm/a6xx: Add support for A619_holi MIME-Version: 1.0 Message-Id: <20230223-topic-gmuwrapper-v6-9-2034115bb60c@linaro.org> References: <20230223-topic-gmuwrapper-v6-0-2034115bb60c@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v6-0-2034115bb60c@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1680350084; l=5408; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=Mkcr01HfBHaztD2wRr44pOp8RNWCI4HsPdHfNo0D/wo=; b=UQ+2LdTXuXfrYvTQ8BtWQnex4mYwBwZIQknk3Xa6cSTH5bvgmW3PBRU2MbRbeDqT9Is67ONfppNt 8/28R+FJAR6X3tMgOZCNYlneY6cFmLeC+jXJ3j1WYbKfwI1z9YNZ X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org A619_holi is a GMU-less variant of the already-supported A619 GPU. It's present on at least SM4350 (holi) and SM6375 (blair). No mesa changes are required. Add the required kernel-side support for it. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 47 ++++++++++++++++++++++++++------- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 ++++ 2 files changed, 43 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 17e314a745c3..2d68b7488b1b 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -614,14 +614,16 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state) return; /* Disable SP clock before programming HWCG registers */ - if (!adreno_has_gmu_wrapper(adreno_gpu)) + if (!adreno_has_gmu_wrapper(adreno_gpu) || + adreno_is_a619_holi(adreno_gpu)) gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 1, 0); for (i = 0; (reg = &adreno_gpu->info->hwcg[i], reg->offset); i++) gpu_write(gpu, reg->offset, state ? reg->value : 0); /* Enable SP clock */ - if (!adreno_has_gmu_wrapper(adreno_gpu)) + if (!adreno_has_gmu_wrapper(adreno_gpu) || + adreno_is_a619_holi(adreno_gpu)) gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 0, 1); gpu_write(gpu, REG_A6XX_RBBM_CLOCK_CNTL, state ? clock_cntl_on : 0); @@ -814,6 +816,9 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) if (adreno_is_a618(adreno_gpu)) return; + if (adreno_is_a619_holi(adreno_gpu)) + hbb_lo = 0; + if (adreno_is_a640_family(adreno_gpu)) amsbc = 1; @@ -1031,7 +1036,12 @@ static int hw_init(struct msm_gpu *gpu) } /* Clear GBIF halt in case GX domain was not collapsed */ - if (a6xx_has_gbif(adreno_gpu)) { + if (adreno_is_a619_holi(adreno_gpu)) { + gpu_write(gpu, REG_A6XX_GBIF_HALT, 0); + gpu_write(gpu, 0x18, 0); + /* Let's make extra sure that the GPU can access the memory.. */ + mb(); + } else if (a6xx_has_gbif(adreno_gpu)) { gpu_write(gpu, REG_A6XX_GBIF_HALT, 0); gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, 0); /* Let's make extra sure that the GPU can access the memory.. */ @@ -1040,6 +1050,9 @@ static int hw_init(struct msm_gpu *gpu) gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_CNTL, 0); + if (adreno_is_a619_holi(adreno_gpu)) + a6xx_sptprac_enable(gmu); + /* * Disable the trusted memory range - we don't actually supported secure * memory rendering at this point in time and we don't want to block off @@ -1295,7 +1308,8 @@ static void a6xx_dump(struct msm_gpu *gpu) #define GBIF_CLIENT_HALT_MASK BIT(0) #define GBIF_ARB_HALT_MASK BIT(1) #define VBIF_RESET_ACK_TIMEOUT 100 -#define VBIF_RESET_ACK_MASK 0x00f0 +#define VBIF_RESET_ACK_MASK 0xF0 +#define GPR0_GBIF_HALT_REQUEST 0x1E0 static void a6xx_recover(struct msm_gpu *gpu) { @@ -1359,10 +1373,16 @@ static void a6xx_recover(struct msm_gpu *gpu) /* Software-reset the GPU */ if (adreno_has_gmu_wrapper(adreno_gpu)) { - /* Halt the GX side of GBIF */ - gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, GBIF_GX_HALT_MASK); - spin_until(gpu_read(gpu, REG_A6XX_RBBM_GBIF_HALT_ACK) & - GBIF_GX_HALT_MASK); + if (adreno_is_a619_holi(adreno_gpu)) { + gpu_write(gpu, 0x18, GPR0_GBIF_HALT_REQUEST); + spin_until((gpu_read(gpu, REG_A6XX_RBBM_VBIF_GX_RESET_STATUS) & + (VBIF_RESET_ACK_MASK)) == VBIF_RESET_ACK_MASK); + } else { + /* Halt the GX side of GBIF */ + gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, GBIF_GX_HALT_MASK); + spin_until(gpu_read(gpu, REG_A6XX_RBBM_GBIF_HALT_ACK) & + GBIF_GX_HALT_MASK); + } /* Halt new client requests on GBIF */ gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_CLIENT_HALT_MASK); @@ -1377,7 +1397,10 @@ static void a6xx_recover(struct msm_gpu *gpu) /* Clear the halts */ gpu_write(gpu, REG_A6XX_GBIF_HALT, 0); - gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, 0); + if (adreno_is_a619_holi(adreno_gpu)) + gpu_write(gpu, 0x18, 0); + else + gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, 0); /* This *really* needs to go through before we do anything else! */ mb(); @@ -1733,6 +1756,9 @@ static int a6xx_pm_resume(struct msm_gpu *gpu) if (ret) goto err_mem_clk; + if (adreno_is_a619_holi(adreno_gpu)) + a6xx_sptprac_enable(gmu); + /* If anything goes south, tear the GPU down piece by piece.. */ if (ret) { err_mem_clk: @@ -1798,6 +1824,9 @@ static int a6xx_pm_suspend(struct msm_gpu *gpu) mutex_lock(&a6xx_gpu->gmu.lock); + if (adreno_is_a619_holi(adreno_gpu)) + a6xx_sptprac_disable(gmu); + clk_disable_unprepare(gpu->ebi1_clk); clk_bulk_disable_unprepare(gpu->nr_clocks, gpu->grp_clks); diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index ee5352bc5329..432fee5c1516 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -252,6 +252,11 @@ static inline int adreno_is_a619(struct adreno_gpu *gpu) return gpu->revn == 619; } +static inline int adreno_is_a619_holi(struct adreno_gpu *gpu) +{ + return adreno_is_a619(gpu) && adreno_has_gmu_wrapper(gpu); +} + static inline int adreno_is_a630(struct adreno_gpu *gpu) { return gpu->revn == 630; From patchwork Sat Apr 1 11:54:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 669663 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2C0C0C77B6D for ; Sat, 1 Apr 2023 11:56:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230106AbjDAL4I (ORCPT ); Sat, 1 Apr 2023 07:56:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53348 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230046AbjDALzp (ORCPT ); Sat, 1 Apr 2023 07:55:45 -0400 Received: from mail-lf1-x131.google.com (mail-lf1-x131.google.com [IPv6:2a00:1450:4864:20::131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3D4E824ADB for ; Sat, 1 Apr 2023 04:55:23 -0700 (PDT) Received: by mail-lf1-x131.google.com with SMTP id g19so19114141lfr.9 for ; Sat, 01 Apr 2023 04:55:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680350116; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=sU3St5PjR61Evr0z3eCeYfEgUC4/g6kaT0ER1gzeKnI=; b=X3+Tsdo696/xGnys5+jrcgjxsbJ4tz26jEHLk1bau35tbqaU76hLfYxQ3EzaGk2bHi KAIhAIzhtCBMVyLITVaA+9H+mdOvVtsnrC77qxCMDTBHxp7usE6/jyPdkuiUI/rXFoQb DrKEfZDwBW5Ij+cPw/iTcg6Gdaw1Ln1VmGI2M4lyA+C3WMOZUMHR/X5LZt3mapXqlUKx klFXTtiTWJaZV+mcNpS6Q91Ce3oYzHnhorSZldhzdni3ALd/SyUu5ZeL3GWVC6MlYR/b Jy3LbwfAxc0HXQ0IIyHABjaj3srOIInRnMmfr8El8Xl4U1GwjpasosCQ0VKllv7aazkU TbuQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680350116; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=sU3St5PjR61Evr0z3eCeYfEgUC4/g6kaT0ER1gzeKnI=; b=IKCt0bHpSlt5SmqYIWGthqPJRi76E5O6nv1ahy+aBnq7bA25OZZ0knb1Goey1HleeD +h3tNJ8FplSA+GPiwQA9j5bg3q2NOhOw7bFDsAOut1DdPmXn3Sk8ybDb6UBUOc0D9yLy K9MVC0veh3i6ojXfKfoycoyHD9g36ymDqvz9q6B9nVgLBsVE9gFk6ywNo7Xrtw5CzeMM LUQtzKGcZUMMiQhOH9se+lZ1SgmC7n3GumnU/S1fw64nGC1R11l22xlDrhFMQzYRrf1p uzwsgnpHhNNY4DqlBgLjEqnGts8zjLD9eVRW0ahXx3eI2sMI17MxG1nGJWbwp1girLVi aq7g== X-Gm-Message-State: AAQBX9c5EY2ErpB9XzRX2CdLwP9SQ5c5VIXKlC7HAXcEF5kQf0MHOIce dhshtc+F7eboT61t0+bcP+l+cA== X-Google-Smtp-Source: AKy350Z6cW6Qy51hdjfhrK0gy6MvBPXO9BbOhS8ZyxAn0VviLZGGU5JsR4KA47yBlyg0SFIHCwMzXg== X-Received: by 2002:ac2:5ded:0:b0:4dd:af74:fe1a with SMTP id z13-20020ac25ded000000b004ddaf74fe1amr8692883lfq.48.1680350116244; Sat, 01 Apr 2023 04:55:16 -0700 (PDT) Received: from [192.168.1.101] (abxj225.neoplus.adsl.tpnet.pl. [83.9.3.225]) by smtp.gmail.com with ESMTPSA id w8-20020ac254a8000000b004e83f386878sm786737lfk.153.2023.04.01.04.55.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Apr 2023 04:55:15 -0700 (PDT) From: Konrad Dybcio Date: Sat, 01 Apr 2023 13:54:47 +0200 Subject: [PATCH v6 10/15] drm/msm/a6xx: Add A610 support MIME-Version: 1.0 Message-Id: <20230223-topic-gmuwrapper-v6-10-2034115bb60c@linaro.org> References: <20230223-topic-gmuwrapper-v6-0-2034115bb60c@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v6-0-2034115bb60c@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1680350084; l=10110; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=uv/hEXYmQ3KK0sfiP4PzFF8TdwEUmbZiZa/DfMgQSRI=; b=qBN84nlMOKNNYGtICf4ppsoMaiduKkd1qMsF2iXJTQgSeXLE/GxuqzVKFnPvPGUsLKeOJC7q3fHI 69LcKA8+AzwtpkkohKAbfsLHumDStj7QnyBA5u6fJszJIFIZH3ct X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org A610 is one of (if not the) lowest-tier SKUs in the A6XX family. It features no GMU, as it's implemented solely on SoCs with SMD_RPM. What's more interesting is that it does not feature a VDDGX line either, being powered solely by VDDCX and has an unfortunate hardware quirk that makes its reset line broken - after a couple of assert/ deassert cycles, it will hang for good and will not wake up again. This GPU requires mesa changes for proper rendering, and lots of them at that. The command streams are quite far away from any other A6XX GPU and hence it needs special care. This patch was validated both by running an (incomplete) downstream mesa with some hacks (frames rendered correctly, though some instructions made the GPU hangcheck which is expected - garbage in, garbage out) and by replaying RD traces captured with the downstream KGSL driver - no crashes there, ever. Add support for this GPU on the kernel side, which comes down to pretty simply adding A612 HWCG tables, altering a few values and adding a special case for handling the reset line. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 97 +++++++++++++++++++++++++++--- drivers/gpu/drm/msm/adreno/adreno_device.c | 12 ++++ drivers/gpu/drm/msm/adreno/adreno_gpu.h | 8 ++- 3 files changed, 107 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 2d68b7488b1b..b2c604a66007 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -254,6 +254,56 @@ static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) a6xx_flush(gpu, ring); } +const struct adreno_reglist a612_hwcg[] = { + {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220}, + {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000081}, + {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf}, + {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222}, + {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111}, + {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111}, + {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111}, + {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111}, + {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777}, + {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777}, + {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777}, + {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777}, + {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01202222}, + {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220}, + {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040f00}, + {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05522022}, + {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555}, + {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011}, + {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044}, + {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222}, + {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222}, + {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x02222222}, + {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002}, + {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222}, + {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000}, + {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}, + {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200}, + {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004}, + {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004}, + {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002}, + {REG_A6XX_RBBM_ISDB_CNT, 0x00000182}, + {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000}, + {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222}, + {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111}, + {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555}, + {}, +}; + /* For a615 family (a615, a616, a618 and a619) */ const struct adreno_reglist a615_hwcg[] = { {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222}, @@ -604,6 +654,8 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state) if (adreno_is_a630(adreno_gpu)) clock_cntl_on = 0x8aa8aa02; + else if (adreno_is_a610(adreno_gpu)) + clock_cntl_on = 0xaaa8aa82; else clock_cntl_on = 0x8aa8aa82; @@ -812,6 +864,13 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) /* Unknown, introduced with A640/680 */ u32 amsbc = 0; + if (adreno_is_a610(adreno_gpu)) { + /* HBB = 14 */ + hbb_lo = 1; + min_acc_len = 1; + ubwc_mode = 1; + } + /* a618 is using the hw default values */ if (adreno_is_a618(adreno_gpu)) return; @@ -1079,13 +1138,13 @@ static int hw_init(struct msm_gpu *gpu) a6xx_set_hwcg(gpu, true); /* VBIF/GBIF start*/ - if (adreno_is_a640_family(adreno_gpu) || + if (adreno_is_a610(adreno_gpu) || + adreno_is_a640_family(adreno_gpu) || adreno_is_a650_family(adreno_gpu)) { gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE0, 0x00071620); gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE1, 0x00071620); gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE2, 0x00071620); gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE3, 0x00071620); - gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE3, 0x00071620); gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x3); } else { gpu_write(gpu, REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL, 0x3); @@ -1113,18 +1172,26 @@ static int hw_init(struct msm_gpu *gpu) gpu_write(gpu, REG_A6XX_UCHE_FILTER_CNTL, 0x804); gpu_write(gpu, REG_A6XX_UCHE_CACHE_WAYS, 0x4); - if (adreno_is_a640_family(adreno_gpu) || - adreno_is_a650_family(adreno_gpu)) + if (adreno_is_a640_family(adreno_gpu) || adreno_is_a650_family(adreno_gpu)) { gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x02000140); - else + gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362c); + } else if (adreno_is_a610(adreno_gpu)) { + gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x00800060); + gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x40201b16); + } else { gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x010000c0); - gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362c); + gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362c); + } if (adreno_is_a660_family(adreno_gpu)) gpu_write(gpu, REG_A6XX_CP_LPAC_PROG_FIFO_SIZE, 0x00000020); /* Setting the mem pool size */ - gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 128); + if (adreno_is_a610(adreno_gpu)) { + gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 48); + gpu_write(gpu, REG_A6XX_CP_MEM_POOL_DBG_ADDR, 47); + } else + gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 128); /* Setting the primFifo thresholds default values, * and vccCacheSkipDis=1 bit (0x200) for A640 and newer @@ -1135,6 +1202,8 @@ static int hw_init(struct msm_gpu *gpu) gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00200200); else if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu)) gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300200); + else if (adreno_is_a610(adreno_gpu)) + gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00080000); else gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00180000); @@ -1150,8 +1219,10 @@ static int hw_init(struct msm_gpu *gpu) a6xx_set_ubwc_config(gpu); /* Enable fault detection */ - gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, - (1 << 30) | 0x1fffff); + if (adreno_is_a610(adreno_gpu)) + gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x3ffff); + else + gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x1fffff); gpu_write(gpu, REG_A6XX_UCHE_CLIENT_PF, 1); @@ -1373,6 +1444,14 @@ static void a6xx_recover(struct msm_gpu *gpu) /* Software-reset the GPU */ if (adreno_has_gmu_wrapper(adreno_gpu)) { + /* 11nm chips (i.e. A610-hosting ones) have HW issues with the reset line */ + if (!adreno_is_a610(adreno_gpu)) { + gpu_write(gpu, REG_A6XX_RBBM_SW_RESET_CMD, 1); + gpu_read(gpu, REG_A6XX_RBBM_SW_RESET_CMD); + udelay(100); + gpu_write(gpu, REG_A6XX_RBBM_SW_RESET_CMD, 0); + } + if (adreno_is_a619_holi(adreno_gpu)) { gpu_write(gpu, 0x18, GPR0_GBIF_HALT_REQUEST); spin_until((gpu_read(gpu, REG_A6XX_RBBM_VBIF_GX_RESET_STATUS) & diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index 4705ce3eb95e..bc536d658aa6 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -253,6 +253,18 @@ static const struct adreno_info gpulist[] = { .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE, .init = a5xx_gpu_init, .zapfw = "a540_zap.mdt", + }, { + .rev = ADRENO_REV(6, 1, 0, ANY_ID), + .revn = 610, + .name = "A610", + .fw = { + [ADRENO_FW_SQE] = "a630_sqe.fw", + }, + .gmem = (SZ_128K + SZ_4K), + .inactive_period = 500, + .init = a6xx_gpu_init, + .zapfw = "a610_zap.mdt", + .hwcg = a612_hwcg, }, { .rev = ADRENO_REV(6, 1, 8, ANY_ID), .revn = 618, diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 432fee5c1516..7a5d595d4b99 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -55,7 +55,8 @@ struct adreno_reglist { u32 value; }; -extern const struct adreno_reglist a615_hwcg[], a630_hwcg[], a640_hwcg[], a650_hwcg[], a660_hwcg[]; +extern const struct adreno_reglist a612_hwcg[], a615_hwcg[], a630_hwcg[], a640_hwcg[], a650_hwcg[]; +extern const struct adreno_reglist a660_hwcg[]; struct adreno_info { struct adreno_rev rev; @@ -242,6 +243,11 @@ static inline int adreno_is_a540(struct adreno_gpu *gpu) return gpu->revn == 540; } +static inline int adreno_is_a610(struct adreno_gpu *gpu) +{ + return gpu->revn == 610; +} + static inline int adreno_is_a618(struct adreno_gpu *gpu) { return gpu->revn == 618; From patchwork Sat Apr 1 11:54:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 669441 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4D7FAC76196 for ; Sat, 1 Apr 2023 11:56:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230029AbjDAL4G (ORCPT ); Sat, 1 Apr 2023 07:56:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51842 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229996AbjDALzn (ORCPT ); Sat, 1 Apr 2023 07:55:43 -0400 Received: from mail-lf1-x12a.google.com (mail-lf1-x12a.google.com [IPv6:2a00:1450:4864:20::12a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D977F23B65 for ; Sat, 1 Apr 2023 04:55:19 -0700 (PDT) Received: by mail-lf1-x12a.google.com with SMTP id br6so32194673lfb.11 for ; Sat, 01 Apr 2023 04:55:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680350119; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=3t7r7bLVwjp/X6e/KXxPlx/bh+Wro5dlHvpo45E2bD8=; b=NzTTRlRpvSvd16aS7cfgXLXxn/VD6g15U66cUvuHNj/mkhrI31h47gpcs5JDa9zAyf 7B0429QCo2GmJstv8PJaHIiTncclak+/Z834BaE2fn0D0MsfjH1tbnNbIwPnnHk+Ph5s 2unRZrF+7UQMgp06TP/hx2fcP///KlSy/IVic3Y8zpU5oEmcZ5Nq5dY6v5XrjYA8565W 5MVWAcmpT2iFanFvwQqAi12WwFKTs3S1KAVRI+yezPCRmKLwO5FGok4S6t0ZASQXDS7t sOViDv/3BUARwZjSGJqsj9fre4VLBzdPYrKobqcfqSGkCwLMfjti8ALB45aSsK52dv8W IvQA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680350119; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3t7r7bLVwjp/X6e/KXxPlx/bh+Wro5dlHvpo45E2bD8=; b=birdvzPVWa8kvfmW+8uGZe5JvQM7lsQDP41VDXUnM2gkn/uXW8hDzL8qWmCU5t0gWM +NchtdwSumL2iayX+6G150/MltSkBI41OXAC5YVWOoBIRXW7am2P3KuqkFkicIHX2dOS ONmA7iOYz2qgekZ0oHUS7tKrb8MsZ6Ok4I+2phcsGhuhgNB7WyXSmORfGas3qyQrwWKG cfsmDZpyeea9oi49u1oUDVn6ZZGaWMmw1wdKC5hs2V2PvPWfuQnvZhAyr05PoOA610pY XudlBsC6HRkn4aEiZDLhUfHdpwhZ1c2RTDYTGiWlfgpGhGfS+EcQQEw+og4nHAy0ndEz xi0w== X-Gm-Message-State: AAQBX9dVEzljX0Q5tvvyg2twnyzEr30dkobs+Fz+ELqXxdDaxU3wQM0F lo6tFHJUQnm74LLLWIpHPTYW1A== X-Google-Smtp-Source: AKy350apwp8LZNOX+NjRELJXLuyxbsgElCG+OnYocrrllHGjWJbsC8myznrgiGiOB3UJ8dFGwrMCrg== X-Received: by 2002:ac2:5681:0:b0:4e9:7931:809f with SMTP id 1-20020ac25681000000b004e97931809fmr8406119lfr.61.1680350119467; Sat, 01 Apr 2023 04:55:19 -0700 (PDT) Received: from [192.168.1.101] (abxj225.neoplus.adsl.tpnet.pl. [83.9.3.225]) by smtp.gmail.com with ESMTPSA id w8-20020ac254a8000000b004e83f386878sm786737lfk.153.2023.04.01.04.55.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Apr 2023 04:55:19 -0700 (PDT) From: Konrad Dybcio Date: Sat, 01 Apr 2023 13:54:48 +0200 Subject: [PATCH v6 11/15] drm/msm/a6xx: Fix some A619 tunables MIME-Version: 1.0 Message-Id: <20230223-topic-gmuwrapper-v6-11-2034115bb60c@linaro.org> References: <20230223-topic-gmuwrapper-v6-0-2034115bb60c@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v6-0-2034115bb60c@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1680350084; l=1537; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=GlBHlCM6IP2T9JuCr/p39vVMngHALy1yw+oNEFq+abw=; b=1srYItYyKpbnbLOrCsUkFcPV2ifiY+QFxZcM9gGrY2W3+aX7blDqJ1grHogrgrtAf4y/EGWrwTQT ddWcdZWcBSuHMOOXdiCeqSwta+70o8OsTBf539wegN+BQCdaErzD X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Adreno 619 expects some tunables to be set differently. Make up for it. Fixes: b7616b5c69e6 ("drm/msm/adreno: Add A619 support") Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index b2c604a66007..389a1f7251fe 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1202,6 +1202,8 @@ static int hw_init(struct msm_gpu *gpu) gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00200200); else if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu)) gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300200); + else if (adreno_is_a619(adreno_gpu)) + gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00018000); else if (adreno_is_a610(adreno_gpu)) gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00080000); else @@ -1219,7 +1221,9 @@ static int hw_init(struct msm_gpu *gpu) a6xx_set_ubwc_config(gpu); /* Enable fault detection */ - if (adreno_is_a610(adreno_gpu)) + if (adreno_is_a619(adreno_gpu)) + gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x3fffff); + else if (adreno_is_a610(adreno_gpu)) gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x3ffff); else gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x1fffff); From patchwork Sat Apr 1 11:54:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 669662 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A9354C6FD1D for ; Sat, 1 Apr 2023 11:56:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230053AbjDAL4I (ORCPT ); Sat, 1 Apr 2023 07:56:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53360 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230047AbjDALzq (ORCPT ); Sat, 1 Apr 2023 07:55:46 -0400 Received: from mail-lf1-x134.google.com (mail-lf1-x134.google.com [IPv6:2a00:1450:4864:20::134]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D7F0225551 for ; Sat, 1 Apr 2023 04:55:24 -0700 (PDT) Received: by mail-lf1-x134.google.com with SMTP id x17so32258913lfu.5 for ; Sat, 01 Apr 2023 04:55:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680350124; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=V2TYwAn1Jyo9PBH+9U5+LtUDgGXL54gtjUvzWRdUK1Y=; b=MCDfAhrecL41SY1SS6uJ7vUnQxBWQ8vuGxBhgLKL9MOgthQlKYzvUk4YwBsCv5jJ2p GSJAMnbGJl+nQXlULJs1FSsSD74MryfUHLHiDNZRDBUHd7b58qX9d1s+KCKVmcvraKc0 W533Hf9iG2IsGN7c1+DXlBFdGjAN9FQXLXxFkNafV/3JCOQxuN+0u2Qm7I+8VGbvgiff PB0Fb+PWONoH7YXQOWBKts8gCSqJIDbtTHRq4iXrZ4K3YFnaXEyCP6o9W9BWuvXoYevS Wj/JDr+sYgjWfagMoWqNFMgub18cjNITLh4rTI4gRpRIdi6L8enhVDzo3x2WQ+rxwlLy i4NQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680350124; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=V2TYwAn1Jyo9PBH+9U5+LtUDgGXL54gtjUvzWRdUK1Y=; b=YInAAYcks/ARxSp9smXHHG4/EF4nkdm4YQH3G5qiTWHPvqWNXB6sjQnEJYgE6F3S28 G/G0rlqpTH9E1Z2zaN4zavoWoAwc9PYpgL9Zzjs+NSN6bVLCUJWm4Lr4FV2cWKmDYkcS EAG3p9mdccBR7fo7uD0pLRFymlHmaDMHlJ9Ac1/Z+okbM5Ik5DMWVHOQF+qg26AE1uCe BEC1tdAq0KjqN+ctxx1lDDjLwhuIJiCEvOKzPFQjQfJC69uCMtKqXO+YpnyLDPa+MhV0 o8kv2TzbnfBLq546sc4f9AHQrUlDGHMpie07UDm43L9y9YifKQMxZu/9XYbi7n2+H1W9 nx1w== X-Gm-Message-State: AAQBX9cPJmrG+mIJqseZNtPqLSoLpvQFrh5a9oQqiGlasd9Y0SK0LcwX eF2jfoT7sr5Pu87WtuV4N3pWAw== X-Google-Smtp-Source: AKy350Y7b4+rJ7oIMIiEy7rKr+JmgGH1J0f8tpAFMqT1b/f/K/ZRJo33j0ZI8F4dEfux5Qrqr3cw1g== X-Received: by 2002:a19:550b:0:b0:4e9:c627:195d with SMTP id n11-20020a19550b000000b004e9c627195dmr8145645lfe.57.1680350124471; Sat, 01 Apr 2023 04:55:24 -0700 (PDT) Received: from [192.168.1.101] (abxj225.neoplus.adsl.tpnet.pl. [83.9.3.225]) by smtp.gmail.com with ESMTPSA id w8-20020ac254a8000000b004e83f386878sm786737lfk.153.2023.04.01.04.55.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Apr 2023 04:55:24 -0700 (PDT) From: Konrad Dybcio Date: Sat, 01 Apr 2023 13:54:49 +0200 Subject: [PATCH v6 12/15] drm/msm/a6xx: Use "else if" in GPU speedbin rev matching MIME-Version: 1.0 Message-Id: <20230223-topic-gmuwrapper-v6-12-2034115bb60c@linaro.org> References: <20230223-topic-gmuwrapper-v6-0-2034115bb60c@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v6-0-2034115bb60c@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1680350084; l=1434; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=PUHRMhG2i7xarnxRfpZn2n4mbPzcd2Fd9BsLsPanfMM=; b=9m5H4CFtN6EC+FWJ//p7SwY92+XoqEoJDeGxyad+OdlVR2aSCDzbfBKcJ+7PZ/AAsHVPruU1PezJ w6wcitFEBKR7VUABWMNzhZ/JHGR8NcVQdKNySSAZiH+5yNl8KZbU X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The GPU can only be one at a time. Turn a series of ifs into if + elseifs to save some CPU cycles. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 389a1f7251fe..a802a29f8173 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2171,16 +2171,16 @@ static u32 fuse_to_supp_hw(struct device *dev, struct adreno_rev rev, u32 fuse) if (adreno_cmp_rev(ADRENO_REV(6, 1, 8, ANY_ID), rev)) val = a618_get_speed_bin(fuse); - if (adreno_cmp_rev(ADRENO_REV(6, 1, 9, ANY_ID), rev)) + else if (adreno_cmp_rev(ADRENO_REV(6, 1, 9, ANY_ID), rev)) val = a619_get_speed_bin(fuse); - if (adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), rev)) + else if (adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), rev)) val = adreno_7c3_get_speed_bin(fuse); - if (adreno_cmp_rev(ADRENO_REV(6, 4, 0, ANY_ID), rev)) + else if (adreno_cmp_rev(ADRENO_REV(6, 4, 0, ANY_ID), rev)) val = a640_get_speed_bin(fuse); - if (adreno_cmp_rev(ADRENO_REV(6, 5, 0, ANY_ID), rev)) + else if (adreno_cmp_rev(ADRENO_REV(6, 5, 0, ANY_ID), rev)) val = a650_get_speed_bin(fuse); if (val == UINT_MAX) { From patchwork Sat Apr 1 11:54:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 669439 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D3A2BC76196 for ; Sat, 1 Apr 2023 11:56:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230151AbjDAL41 (ORCPT ); Sat, 1 Apr 2023 07:56:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52536 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230020AbjDALzz (ORCPT ); Sat, 1 Apr 2023 07:55:55 -0400 Received: from mail-lf1-x12f.google.com (mail-lf1-x12f.google.com [IPv6:2a00:1450:4864:20::12f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 12B2520620 for ; Sat, 1 Apr 2023 04:55:37 -0700 (PDT) Received: by mail-lf1-x12f.google.com with SMTP id br6so32194884lfb.11 for ; Sat, 01 Apr 2023 04:55:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680350127; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=p4fj6BZ1SXPCMTA1b95cYrYZNvYyQufsY+lFzyAw5Ag=; b=mw721N/DjJT0KciVbCcGyWDWtaWmwE8gtht2z8TW5VCIJQvWOsglmyDB2zr8BPZ0/e 6tVz62UYb15XC3xzkILdF/1p6CThW4hMoCFmMEvYhduqGhMgAKkbAC9X1G0/rhIqz+1Q a52sVCTOY1uSNpI4hhH1pOc4UiLguukjXtNhZGQ/L3rOPWqvv+tJOuAW5YF0RJpo3xsq U0Hs3Irt3RnqYXcDPD2e44LBp8BSe1G2/+IgHpFsdDzc1Is2unSTH1k7DBaTTqQt2KF7 0J7H3jz5lnfw9VKQFfKrUQnBxdhPLeRhyffKEirqq7n152VWW550AFbxDOZCsgRMazUi XjhQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680350127; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=p4fj6BZ1SXPCMTA1b95cYrYZNvYyQufsY+lFzyAw5Ag=; b=XV//2VAMT3f6/wMSXo9LsIoRCI5mn4oD+bqA/RWvKAEIeAvnw7SbtuICXtoRQ86Pcw yyAgaQeElxAvjLULaCZ/tcUqDdAHcDAJ7v5O3ZbNi+FWgD6Z6wzTkHbSbRQjPdGDiwY9 bLlRQ7/xdyQoATnHomWR1jl3cqAGrEl9hTE8oGo8XOf0X1JOxi0i7ijKit/P8dzRNB0V bbNX0CWtv2w8Mkt65OYgvECBc1wcyye8JStSO+IZln8fncdz9tYFWi5jspSlW11t1sWd UQ2TlCPiTLpV60GCTb3WwWdz/rdMvWt/eeVHlUMEXgteuse8ilPVVyNYyh44lHZDdzXw pXTw== X-Gm-Message-State: AAQBX9fEc/cxN6c2HgB5CKVUwWWdZhzDha6DLwWyRKuR/TZgrUNkJoZE AWHF0Tt/XetlyJQk7zy1v8iDgA== X-Google-Smtp-Source: AKy350a9XBgWNv6tWjTkZJ/0TX4KZgML0jQGPAwiP7nw+piPNJKeMQ7FqslCi2uQAKhO62615gITPQ== X-Received: by 2002:a19:ad46:0:b0:4eb:1527:e29d with SMTP id s6-20020a19ad46000000b004eb1527e29dmr4818192lfd.52.1680350127490; Sat, 01 Apr 2023 04:55:27 -0700 (PDT) Received: from [192.168.1.101] (abxj225.neoplus.adsl.tpnet.pl. [83.9.3.225]) by smtp.gmail.com with ESMTPSA id w8-20020ac254a8000000b004e83f386878sm786737lfk.153.2023.04.01.04.55.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Apr 2023 04:55:27 -0700 (PDT) From: Konrad Dybcio Date: Sat, 01 Apr 2023 13:54:50 +0200 Subject: [PATCH v6 13/15] drm/msm/a6xx: Use adreno_is_aXYZ macros in speedbin matching MIME-Version: 1.0 Message-Id: <20230223-topic-gmuwrapper-v6-13-2034115bb60c@linaro.org> References: <20230223-topic-gmuwrapper-v6-0-2034115bb60c@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v6-0-2034115bb60c@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1680350084; l=4317; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=gt/XSuRfu9SW3ip+LGRQSjqxQbTtasoADdeZewQY5iA=; b=x1D3Y3w9Xahm2EFcpyOmjiy++nMJd9XXmLM6oFTWaKk04TstuKD29p0VA0n0WTh8uuMm7pO+wHwI HGe6iSIsCo7Q9MZZQLVmSkDHMNTIDlXLYq/ilvSbA12YeA8OkeEE X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Before transitioning to using per-SoC and not per-Adreno speedbin fuse values (need another patchset to land elsewhere), a good improvement/stopgap solution is to use adreno_is_aXYZ macros in place of explicit revision matching. Do so to allow differentiating between A619 and A619_holi. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 18 +++++++++--------- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 14 ++++++++++++-- 2 files changed, 21 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index a802a29f8173..6c84ef82e504 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2164,23 +2164,23 @@ static u32 adreno_7c3_get_speed_bin(u32 fuse) return UINT_MAX; } -static u32 fuse_to_supp_hw(struct device *dev, struct adreno_rev rev, u32 fuse) +static u32 fuse_to_supp_hw(struct device *dev, struct adreno_gpu *adreno_gpu, u32 fuse) { u32 val = UINT_MAX; - if (adreno_cmp_rev(ADRENO_REV(6, 1, 8, ANY_ID), rev)) + if (adreno_is_a618(adreno_gpu)) val = a618_get_speed_bin(fuse); - else if (adreno_cmp_rev(ADRENO_REV(6, 1, 9, ANY_ID), rev)) + else if (adreno_is_a619(adreno_gpu)) val = a619_get_speed_bin(fuse); - else if (adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), rev)) + else if (adreno_is_7c3(adreno_gpu)) val = adreno_7c3_get_speed_bin(fuse); - else if (adreno_cmp_rev(ADRENO_REV(6, 4, 0, ANY_ID), rev)) + else if (adreno_is_a640(adreno_gpu)) val = a640_get_speed_bin(fuse); - else if (adreno_cmp_rev(ADRENO_REV(6, 5, 0, ANY_ID), rev)) + else if (adreno_is_a650(adreno_gpu)) val = a650_get_speed_bin(fuse); if (val == UINT_MAX) { @@ -2193,7 +2193,7 @@ static u32 fuse_to_supp_hw(struct device *dev, struct adreno_rev rev, u32 fuse) return (1 << val); } -static int a6xx_set_supported_hw(struct device *dev, struct adreno_rev rev) +static int a6xx_set_supported_hw(struct device *dev, struct adreno_gpu *adreno_gpu) { u32 supp_hw; u32 speedbin; @@ -2212,7 +2212,7 @@ static int a6xx_set_supported_hw(struct device *dev, struct adreno_rev rev) return ret; } - supp_hw = fuse_to_supp_hw(dev, rev, speedbin); + supp_hw = fuse_to_supp_hw(dev, adreno_gpu, speedbin); ret = devm_pm_opp_set_supported_hw(dev, &supp_hw, 1); if (ret) @@ -2333,7 +2333,7 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) if (!adreno_has_gmu_wrapper(adreno_gpu)) a6xx_llc_slices_init(pdev, a6xx_gpu); - ret = a6xx_set_supported_hw(&pdev->dev, config->rev); + ret = a6xx_set_supported_hw(&pdev->dev, adreno_gpu); if (ret) { a6xx_destroy(&(a6xx_gpu->base.base)); return ERR_PTR(ret); diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 7a5d595d4b99..21513cec038f 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -268,9 +268,9 @@ static inline int adreno_is_a630(struct adreno_gpu *gpu) return gpu->revn == 630; } -static inline int adreno_is_a640_family(struct adreno_gpu *gpu) +static inline int adreno_is_a640(struct adreno_gpu *gpu) { - return (gpu->revn == 640) || (gpu->revn == 680); + return gpu->revn == 640; } static inline int adreno_is_a650(struct adreno_gpu *gpu) @@ -289,6 +289,11 @@ static inline int adreno_is_a660(struct adreno_gpu *gpu) return gpu->revn == 660; } +static inline int adreno_is_a680(struct adreno_gpu *gpu) +{ + return gpu->revn == 680; +} + /* check for a615, a616, a618, a619 or any derivatives */ static inline int adreno_is_a615_family(struct adreno_gpu *gpu) { @@ -306,6 +311,11 @@ static inline int adreno_is_a650_family(struct adreno_gpu *gpu) return gpu->revn == 650 || gpu->revn == 620 || adreno_is_a660_family(gpu); } +static inline int adreno_is_a640_family(struct adreno_gpu *gpu) +{ + return adreno_is_a640(gpu) || adreno_is_a680(gpu); +} + u64 adreno_private_address_space_size(struct msm_gpu *gpu); int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx, uint32_t param, uint64_t *value, uint32_t *len); From patchwork Sat Apr 1 11:54:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 669440 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AE9EDC77B70 for ; Sat, 1 Apr 2023 11:56:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230117AbjDAL4J (ORCPT ); Sat, 1 Apr 2023 07:56:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52220 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230061AbjDALzv (ORCPT ); Sat, 1 Apr 2023 07:55:51 -0400 Received: from mail-lf1-x12e.google.com (mail-lf1-x12e.google.com [IPv6:2a00:1450:4864:20::12e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1B05224ACD for ; Sat, 1 Apr 2023 04:55:30 -0700 (PDT) Received: by mail-lf1-x12e.google.com with SMTP id h11so25262381lfu.8 for ; Sat, 01 Apr 2023 04:55:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680350129; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=PvltTppQ4ytNI2iYvcugGpbwqcOyX8AShb2FaDucEqw=; b=ihi5GmzEWv+VcAzvHfPcBqkwlEsowoxk6+WHE7CwZQS+/SHgEFgKpnHsdQnG+Ab7PT 5qo+R699O5MLKGhG9k3gW4dxJlNkeBQU5KlgcYobFXhkgCXV5Y9kCaqm1YZ9DqHEC9EY kf9VdX/TJSOsEnl7KbjrH+liuFucia+1jgHaN9ZJssfYYDaz2wibtce+7dOLK/0jmFrS eekaC3fa6d1TeizoG6IHfoHO1fE6RDhr817M4iLG9GEqHHgEYcELJrybFC/Hzu5VZeU0 XQH121nP4g1Fr/Hje2FbVL5lbPH+pQZLxoqKV4zlmnny+9jWxBkm4mYqUBXB1tOEc0uu QUgg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680350129; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PvltTppQ4ytNI2iYvcugGpbwqcOyX8AShb2FaDucEqw=; b=mM3TUe4RVKrOpt+fa2fw7G4GV0EIfRU+dD3d5tw7QR/t9O5aU68uTRrjDekGPI8/wV oqU8nlvWyHjK4ipG5tJ+JkgnhSzWKn7Ek1Lq/KCwrI/aVVKathVlYyTE8WPozD8XUyDb 50z+swMXrQXgwFqJU/3z2HymZUKuiRu9JMR47Luq5lA95VTQb0Kx3bBvKrT86pzHzg+O rOR38dRSbYyssue7yuSGyY7CUIPXRL3MdDxVWpUNz5F5qKhbmzxqZmDtfLyNVXKPGq+p WgIgpdimPfvfjUFQ/s8bOPBxDO1i1tdtJTjYjsVyUV0ZNwi+nMd4RUIPdMmGPW/9vQP7 5CHg== X-Gm-Message-State: AAQBX9fduR8f+W1sv+sqM/UWnCAysvCwHp8oSHl7UTaUCBRQ7qndld10 mXYdHfbb1WrDA0m3lAqEmVNN9A== X-Google-Smtp-Source: AKy350bJy2z6I4BDJI2gEIHuz15iK1SircE7jIxlPTzfn2dkBmRMrb9deM8+GqUIMVCMMJxe4oLn1Q== X-Received: by 2002:ac2:5288:0:b0:4eb:2d47:602 with SMTP id q8-20020ac25288000000b004eb2d470602mr2203727lfm.59.1680350129586; Sat, 01 Apr 2023 04:55:29 -0700 (PDT) Received: from [192.168.1.101] (abxj225.neoplus.adsl.tpnet.pl. [83.9.3.225]) by smtp.gmail.com with ESMTPSA id w8-20020ac254a8000000b004e83f386878sm786737lfk.153.2023.04.01.04.55.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Apr 2023 04:55:29 -0700 (PDT) From: Konrad Dybcio Date: Sat, 01 Apr 2023 13:54:51 +0200 Subject: [PATCH v6 14/15] drm/msm/a6xx: Add A619_holi speedbin support MIME-Version: 1.0 Message-Id: <20230223-topic-gmuwrapper-v6-14-2034115bb60c@linaro.org> References: <20230223-topic-gmuwrapper-v6-0-2034115bb60c@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v6-0-2034115bb60c@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1680350084; l=2033; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=TnC1uZLteG174FfRp1Tk1pi+iYNuA1vsyt7TElivWgM=; b=q0RiUq5vPj5sHbjyimWm1HIHMcjymEkY+z2mS91KK5DtNd2pLzHtIBFkJ00F2F6/yBV5FQvHu5NK ov4d3OHFDf9jaPJPJhJTc4/u4Ra63DzEiU/mtPGdDoZWZk5zJc4/ X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org A619_holi is implemented on at least two SoCs: SM4350 (holi) and SM6375 (blair). This is what seems to be a first occurrence of this happening, but it's easy to overcome by guarding the SoC-specific fuse values with of_machine_is_compatible(). Do just that to enable frequency limiting on these SoCs. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 6c84ef82e504..f692f540c13c 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2112,6 +2112,34 @@ static u32 a618_get_speed_bin(u32 fuse) return UINT_MAX; } +static u32 a619_holi_get_speed_bin(u32 fuse) +{ + /* + * There are (at least) two SoCs implementing A619_holi: SM4350 (holi) + * and SM6375 (blair). Limit the fuse matching to the corresponding + * SoC to prevent bogus frequency setting (as improbable as it may be, + * given unexpected fuse values are.. unexpected! But still possible.) + */ + + if (fuse == 0) + return 0; + + if (of_machine_is_compatible("qcom,sm4350")) { + if (fuse == 138) + return 1; + else if (fuse == 92) + return 2; + } else if (of_machine_is_compatible("qcom,sm6375")) { + if (fuse == 190) + return 1; + else if (fuse == 177) + return 2; + } else + pr_warn("Unknown SoC implementing A619_holi!\n"); + + return UINT_MAX; +} + static u32 a619_get_speed_bin(u32 fuse) { if (fuse == 0) @@ -2171,6 +2199,9 @@ static u32 fuse_to_supp_hw(struct device *dev, struct adreno_gpu *adreno_gpu, u3 if (adreno_is_a618(adreno_gpu)) val = a618_get_speed_bin(fuse); + else if (adreno_is_a619_holi(adreno_gpu)) + val = a619_holi_get_speed_bin(fuse); + else if (adreno_is_a619(adreno_gpu)) val = a619_get_speed_bin(fuse); From patchwork Sat Apr 1 11:54:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 669661 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7C9E0C77B6E for ; Sat, 1 Apr 2023 11:56:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230090AbjDAL43 (ORCPT ); Sat, 1 Apr 2023 07:56:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53092 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229924AbjDALzz (ORCPT ); Sat, 1 Apr 2023 07:55:55 -0400 Received: from mail-lf1-x12c.google.com (mail-lf1-x12c.google.com [IPv6:2a00:1450:4864:20::12c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5BFFF20C22 for ; Sat, 1 Apr 2023 04:55:39 -0700 (PDT) Received: by mail-lf1-x12c.google.com with SMTP id x17so32259138lfu.5 for ; Sat, 01 Apr 2023 04:55:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680350132; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=l7iaKrmXzAocug0zm1BXOXimd3i27ycjAt6X7axyt1c=; b=huSfh3WPWOS2hUfnr6lymatuU4DazhafyQESbHCwz8Ux2BCzKiKR3v5FqeLRU7ZiaG lgvVM230rE0+NDVKiljZYLo75J16DwD20JogzRb4tvNyNqXe4Ou4ku0kHLPlnOX1M0ZM 9qG/mRyuVeib84/v6csmnNde7gUfbYKX4aRuoqas9hSBjUMHDzLR9Pnx3oscWpKSojmW XhqVJ87ULKEBcdD+UaCFWSLTlnAm29es/bjn0unZqNZMgXVkT5dXgzWJGf6pt7iQE4/G j4v/VZjeXhogtWAVq9cFlfGQVNQqc9cxXxAA9pzpJ5rdI8VUqvy65zPSnoO5nwEwkkir kppA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680350132; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=l7iaKrmXzAocug0zm1BXOXimd3i27ycjAt6X7axyt1c=; b=PRigm85ghLou2rdInFaAgYH1F9rV3yCbMpYlBZfyHWAcL75TRJ57Tav7kmDY/atl5t 4HX4FAtO+Z1fLATVaHdk+N0ojYLXL8J2LllTQaO0m5ixT5X16v8yKZ+1ZQtLoQpLEva9 CVVS6lyyDS0pBhP8XnnA83pwki7hdX9u62o3SMKC6xR9BjptT0dQkmfm0ZSdMgMluxay 1OUl1xoCELnNVdrkPLABRUiYakDcQLwbzyMtFGFdP7NkIDqeZmXzcK7EpE9lxbAkzdTh Z9RujitWsCVvYuT9cVYxsqQ9LbpQVDPqjLepGflV4B1QshXG/KoNsd2beWpTjRnEc3I7 GifQ== X-Gm-Message-State: AAQBX9e9WJpLXuwXpK0L3hO8gcT0CjNA5wE0Y6pbImdI0QGppwfCkyfx rFb6NDM/BigWpvQ9HzSQx7G6Rw== X-Google-Smtp-Source: AKy350azx5qjLTJIYLCDCfdeM/z+nx8o5HVz0WcrmXuRcb964FuH1R/r2IAXFnphdVUg7ElZbC7SXg== X-Received: by 2002:ac2:43a4:0:b0:4ea:f526:5bee with SMTP id t4-20020ac243a4000000b004eaf5265beemr7893904lfl.11.1680350132632; Sat, 01 Apr 2023 04:55:32 -0700 (PDT) Received: from [192.168.1.101] (abxj225.neoplus.adsl.tpnet.pl. [83.9.3.225]) by smtp.gmail.com with ESMTPSA id w8-20020ac254a8000000b004e83f386878sm786737lfk.153.2023.04.01.04.55.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Apr 2023 04:55:32 -0700 (PDT) From: Konrad Dybcio Date: Sat, 01 Apr 2023 13:54:52 +0200 Subject: [PATCH v6 15/15] drm/msm/a6xx: Add A610 speedbin support MIME-Version: 1.0 Message-Id: <20230223-topic-gmuwrapper-v6-15-2034115bb60c@linaro.org> References: <20230223-topic-gmuwrapper-v6-0-2034115bb60c@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v6-0-2034115bb60c@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1680350084; l=1852; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=/AkqnGngmcLmZe0/0dqCMVNhVeDNpUZqOtTS2j9nX1Q=; b=usbd75h1G/MzZMxQHI2wq6t4BEKTNhpk+Isjf6v/HYYNAGutNoR1I0u4FRvYOZtYxNIEFB5z0ccu bEdbYbPfDgPxI6HxpJwVMuOz7DB944fAMB/nw7uB9a+8Ff7nuHQO X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org A610 is implemented on at least three SoCs: SM6115 (bengal), SM6125 (trinket) and SM6225 (khaje). Trinket does not support speed binning (only a single SKU exists) and we don't yet support khaje upstream. Hence, add a fuse mapping table for bengal to allow for per-chip frequency limiting. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index f692f540c13c..e3be878afbb0 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2100,6 +2100,30 @@ static bool a6xx_progress(struct msm_gpu *gpu, struct msm_ringbuffer *ring) return progress; } +static u32 a610_get_speed_bin(u32 fuse) +{ + /* + * There are (at least) three SoCs implementing A610: SM6125 (trinket), + * SM6115 (bengal) and SM6225 (khaje). Trinket does not have speedbinning, + * as only a single SKU exists and we don't support khaje upstream yet. + * Hence, this matching table is only valid for bengal and can be easily + * expanded if need be. + */ + + if (fuse == 0) + return 0; + else if (fuse == 206) + return 1; + else if (fuse == 200) + return 2; + else if (fuse == 157) + return 3; + else if (fuse == 127) + return 4; + + return UINT_MAX; +} + static u32 a618_get_speed_bin(u32 fuse) { if (fuse == 0) @@ -2196,6 +2220,9 @@ static u32 fuse_to_supp_hw(struct device *dev, struct adreno_gpu *adreno_gpu, u3 { u32 val = UINT_MAX; + if (adreno_is_a610(adreno_gpu)) + val = a610_get_speed_bin(fuse); + if (adreno_is_a618(adreno_gpu)) val = a618_get_speed_bin(fuse);