From patchwork Thu Mar 30 16:51:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Morse X-Patchwork-Id: 669209 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ACD92C6FD1D for ; Thu, 30 Mar 2023 16:53:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230355AbjC3QxY (ORCPT ); Thu, 30 Mar 2023 12:53:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37716 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231276AbjC3QxJ (ORCPT ); Thu, 30 Mar 2023 12:53:09 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 953B8EB6F for ; Thu, 30 Mar 2023 09:52:54 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A86FA1650; Thu, 30 Mar 2023 09:53:38 -0700 (PDT) Received: from eglon.cambridge.arm.com (eglon.cambridge.arm.com [10.1.196.177]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id CC0C43F6C4; Thu, 30 Mar 2023 09:52:52 -0700 (PDT) From: James Morse To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Cc: Catalin Marinas , Will Deacon , Mark Rutland , Lorenzo Pieralisi , Sudeep Holla , Marc Zyngier , Oliver Upton , James Morse , Rob Herring , Krzysztof Kozlowski Subject: [PATCH 2/6] firmware: smccc: Add support for erratum discovery API Date: Thu, 30 Mar 2023 17:51:24 +0100 Message-Id: <20230330165128.3237939-3-james.morse@arm.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230330165128.3237939-1-james.morse@arm.com> References: <20230330165128.3237939-1-james.morse@arm.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org It is not always possible for the OS to determine if a CPU is affected by a particular erratum. For example, it may depend on an integration choice the chip designer made, or whether firmware has enabled some particular feature. Add support for the SMCCC 'Errata Management Firmware Interface' that lets the OS query firmware for this information. Link: https://developer.arm.com/documentation/den0100/1-0/?lang=en Signed-off-by: James Morse --- arch/arm64/kernel/cpufeature.c | 7 +++ drivers/firmware/smccc/Kconfig | 8 ++++ drivers/firmware/smccc/Makefile | 1 + drivers/firmware/smccc/em.c | 78 +++++++++++++++++++++++++++++++++ include/linux/arm-smccc.h | 28 ++++++++++++ include/linux/arm_smccc_em.h | 11 +++++ 6 files changed, 133 insertions(+) create mode 100644 drivers/firmware/smccc/em.c create mode 100644 include/linux/arm_smccc_em.h diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 2e3e55139777..62f996006783 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -62,6 +62,7 @@ #define pr_fmt(fmt) "CPU features: " fmt +#include #include #include #include @@ -1047,6 +1048,12 @@ void __init init_cpu_features(struct cpuinfo_arm64 *info) */ init_cpu_hwcaps_indirect_list(); + /* + * Early erratum workaround may need to be discovered from firmware. + */ + if (IS_ENABLED(CONFIG_ARM_SMCCC_EM)) + arm_smccc_em_init(); + /* * Detect and enable early CPU capabilities based on the boot CPU, * after we have initialised the CPU feature infrastructure. diff --git a/drivers/firmware/smccc/Kconfig b/drivers/firmware/smccc/Kconfig index 15e7466179a6..a10a150d49bb 100644 --- a/drivers/firmware/smccc/Kconfig +++ b/drivers/firmware/smccc/Kconfig @@ -23,3 +23,11 @@ config ARM_SMCCC_SOC_ID help Include support for the SoC bus on the ARM SMCCC firmware based platforms providing some sysfs information about the SoC variant. + +config ARM_SMCCC_EM + bool "Errata discovery by ARM SMCCC" + depends on HAVE_ARM_SMCCC_DISCOVERY + default y + help + Include support for querying firmware via SMCCC to determine whether + the CPU is affected by a specific erratum. diff --git a/drivers/firmware/smccc/Makefile b/drivers/firmware/smccc/Makefile index 40d19144a860..39ed128b59b5 100644 --- a/drivers/firmware/smccc/Makefile +++ b/drivers/firmware/smccc/Makefile @@ -2,3 +2,4 @@ # obj-$(CONFIG_HAVE_ARM_SMCCC_DISCOVERY) += smccc.o kvm_guest.o obj-$(CONFIG_ARM_SMCCC_SOC_ID) += soc_id.o +obj-$(CONFIG_ARM_SMCCC_EM) += em.o diff --git a/drivers/firmware/smccc/em.c b/drivers/firmware/smccc/em.c new file mode 100644 index 000000000000..2c66240d8707 --- /dev/null +++ b/drivers/firmware/smccc/em.c @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Arm Errata Management firmware interface. + * + * This firmware interface advertises support for firmware mitigations for CPU + * errata. It can also be used to discover erratum where the 'configurations + * affected' depends on the integration. + * + * Copyright (C) 2022 ARM Limited + */ + +#define pr_fmt(fmt) "arm_smccc_em: " fmt + +#include +#include +#include +#include + +#include + +#include + +static u32 supported; + +int arm_smccc_em_cpu_features(u32 erratum_id) +{ + struct arm_smccc_res res; + + if (!READ_ONCE(supported)) + return -EOPNOTSUPP; + + arm_smccc_1_1_invoke(ARM_SMCCC_EM_CPU_ERRATUM_FEATURES, erratum_id, 0, &res); + switch (res.a0) { + case SMCCC_RET_NOT_SUPPORTED: + return -EOPNOTSUPP; + case SMCCC_EM_RET_INVALID_PARAMTER: + return -EINVAL; + case SMCCC_EM_RET_UNKNOWN: + return -ENOENT; + case SMCCC_EM_RET_HIGHER_EL_MITIGATION: + case SMCCC_EM_RET_NOT_AFFECTED: + case SMCCC_EM_RET_AFFECTED: + return res.a0; + }; + + return -EIO; +} + +int __init arm_smccc_em_init(void) +{ + u32 major_ver, minor_ver; + struct arm_smccc_res res; + enum arm_smccc_conduit conduit = arm_smccc_1_1_get_conduit(); + + if (conduit == SMCCC_CONDUIT_NONE) + return -EOPNOTSUPP; + + arm_smccc_1_1_invoke(ARM_SMCCC_EM_VERSION, &res); + if (res.a0 == SMCCC_RET_NOT_SUPPORTED) + return -EOPNOTSUPP; + + major_ver = PSCI_VERSION_MAJOR(res.a0); + minor_ver = PSCI_VERSION_MINOR(res.a0); + if (major_ver != 1) + return -EIO; + + arm_smccc_1_1_invoke(ARM_SMCCC_EM_FEATURES, + ARM_SMCCC_EM_CPU_ERRATUM_FEATURES, &res); + if (res.a0 == SMCCC_RET_NOT_SUPPORTED) + return -EOPNOTSUPP; + + pr_info("SMCCC Errata Management Interface v%d.%d\n", + major_ver, minor_ver); + + WRITE_ONCE(supported, 1); + + return 0; +} diff --git a/include/linux/arm-smccc.h b/include/linux/arm-smccc.h index 220c8c60e021..cc2e38ce8707 100644 --- a/include/linux/arm-smccc.h +++ b/include/linux/arm-smccc.h @@ -182,6 +182,25 @@ ARM_SMCCC_OWNER_STANDARD, \ 0x53) +/* Errata Management calls (defined by ARM DEN0100) */ +#define ARM_SMCCC_EM_VERSION \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_32, \ + ARM_SMCCC_OWNER_STANDARD, \ + 0xF0) + +#define ARM_SMCCC_EM_FEATURES \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_32, \ + ARM_SMCCC_OWNER_STANDARD, \ + 0xF1) + +#define ARM_SMCCC_EM_CPU_ERRATUM_FEATURES \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_32, \ + ARM_SMCCC_OWNER_STANDARD, \ + 0xF2) + /* * Return codes defined in ARM DEN 0070A * ARM DEN 0070A is now merged/consolidated into ARM DEN 0028 C @@ -191,6 +210,15 @@ #define SMCCC_RET_NOT_REQUIRED -2 #define SMCCC_RET_INVALID_PARAMETER -3 +/* + * Return codes defined in ARM DEN 0100 + */ +#define SMCCC_EM_RET_HIGHER_EL_MITIGATION 3 +#define SMCCC_EM_RET_NOT_AFFECTED 2 +#define SMCCC_EM_RET_AFFECTED 1 +#define SMCCC_EM_RET_INVALID_PARAMTER -2 +#define SMCCC_EM_RET_UNKNOWN -3 + #ifndef __ASSEMBLY__ #include diff --git a/include/linux/arm_smccc_em.h b/include/linux/arm_smccc_em.h new file mode 100644 index 000000000000..71293cbbe545 --- /dev/null +++ b/include/linux/arm_smccc_em.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* Copyright (c) 2023 ARM Limited */ +#ifndef __LINUX_ARM_SMCCC_EM_H +#define __LINUX_ARM_SMCCC_EM_H + +#include + +int arm_smccc_em_init(void); +int arm_smccc_em_cpu_features(u32 erratum_id); + +#endif /* __LINUX_ARM_SMCCC_EM_H */ From patchwork Thu Mar 30 16:51:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Morse X-Patchwork-Id: 669208 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ADD7CC761A6 for ; Thu, 30 Mar 2023 16:53:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231936AbjC3Qxe (ORCPT ); Thu, 30 Mar 2023 12:53:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36258 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229916AbjC3QxO (ORCPT ); Thu, 30 Mar 2023 12:53:14 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id B6BEBEB6C for ; Thu, 30 Mar 2023 09:52:58 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4BDB62F4; Thu, 30 Mar 2023 09:53:42 -0700 (PDT) Received: from eglon.cambridge.arm.com (eglon.cambridge.arm.com [10.1.196.177]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 519993F6C4; Thu, 30 Mar 2023 09:52:56 -0700 (PDT) From: James Morse To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Cc: Catalin Marinas , Will Deacon , Mark Rutland , Lorenzo Pieralisi , Sudeep Holla , Marc Zyngier , Oliver Upton , James Morse , Rob Herring , Krzysztof Kozlowski Subject: [PATCH 4/6] arm64: errata: Disable FWB on parts with non-ARM interconnects Date: Thu, 30 Mar 2023 17:51:26 +0100 Message-Id: <20230330165128.3237939-5-james.morse@arm.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230330165128.3237939-1-james.morse@arm.com> References: <20230330165128.3237939-1-james.morse@arm.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Force Write Back (FWB) allows the hypervisor to force non-cacheable accesses made by a guest to be cacheable. This saves the hypervisor from doing cache maintenance on all pages the guest can access, to ensure the guest doesn't see stale (and possibly sensitive) data when making a non-cacheable access. When stage1 translation is disabled, the SCTRL_E1.I bit controls the attributes used for instruction fetch, one of the options results in a non-cacheable access. A whole host of CPUs missed the FWB override in this case, meaning a KVM guest could fetch stale/junk data instead of instructions. The workaround is to always do the cache maintenance. These parts don't have fine-grained-traps, so it isn't feasible to detect the guest disabling the MMU. Instead, disable FWB on the host. While the CPUs are affected, this erratum doesn't occur on parts using Arm's CMN interconnects. Use the Errata Management API to discover whether this CPU is affected. Because guest execution is compromised, the workaround is enabled by default. If the Errata Management API isn't implemented by firmware, the workaround will be enabled. If a target platform is not affected, and it isn't possible to add support for the Errata Management API, the erratum can be disabled in Kconfig. Signed-off-by: James Morse --- This patch causes the additional output: | Stage-2 Force Write-Back disabled due to erratum #2701951 | CPU features: detected: ARM erratum 2701951 --- Documentation/arm64/silicon-errata.rst | 18 ++++++ arch/arm64/Kconfig | 27 ++++++++ arch/arm64/include/asm/cpufeature.h | 1 + arch/arm64/kernel/cpu_errata.c | 86 ++++++++++++++++++++++++++ arch/arm64/kernel/cpufeature.c | 16 ++++- arch/arm64/tools/cpucaps | 1 + 6 files changed, 148 insertions(+), 1 deletion(-) diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst index ec5f889d7681..d6ca86ebc7af 100644 --- a/Documentation/arm64/silicon-errata.rst +++ b/Documentation/arm64/silicon-errata.rst @@ -106,6 +106,10 @@ stable kernels. +----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-A77 | #1508412 | ARM64_ERRATUM_1508412 | +----------------+-----------------+-----------------+-----------------------------+ +| ARM | Cortex-A78 | #2712571 | ARM64_ERRATUM_2701951 | ++----------------+-----------------+-----------------+-----------------------------+ +| ARM | Cortex-A78C | #2712575,2712572| ARM64_ERRATUM_2701951 | ++----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-A510 | #2051678 | ARM64_ERRATUM_2051678 | +----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-A510 | #2077057 | ARM64_ERRATUM_2077057 | @@ -120,12 +124,20 @@ stable kernels. +----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-A710 | #2224489 | ARM64_ERRATUM_2224489 | +----------------+-----------------+-----------------+-----------------------------+ +| ARM | Cortex-A710 | #2701952 | ARM64_ERRATUM_2701951 | ++----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-A715 | #2645198 | ARM64_ERRATUM_2645198 | +----------------+-----------------+-----------------+-----------------------------+ +| ARM | Cortex-X1 | #2712571 | ARM64_ERRATUM_2701951 | ++----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-X2 | #2119858 | ARM64_ERRATUM_2119858 | +----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-X2 | #2224489 | ARM64_ERRATUM_2224489 | +----------------+-----------------+-----------------+-----------------------------+ +| ARM | Cortex-X2 | #2701952 | ARM64_ERRATUM_2701951 | ++----------------+-----------------+-----------------+-----------------------------+ +| ARM | Cortex-X3 | #2701951 | ARM64_ERRATUM_2701951 | ++----------------+-----------------+-----------------+-----------------------------+ | ARM | Neoverse-N1 | #1188873,1418040| ARM64_ERRATUM_1418040 | +----------------+-----------------+-----------------+-----------------------------+ | ARM | Neoverse-N1 | #1349291 | N/A | @@ -138,6 +150,12 @@ stable kernels. +----------------+-----------------+-----------------+-----------------------------+ | ARM | Neoverse-N2 | #2253138 | ARM64_ERRATUM_2253138 | +----------------+-----------------+-----------------+-----------------------------+ +| ARM | Neoverse-N2 | #2728475 | ARM64_ERRATUM_2701951 | ++----------------+-----------------+-----------------+-----------------------------+ +| ARM | Neoverse-V1 | #2701953 | ARM64_ERRATUM_2701951 | ++----------------+-----------------+-----------------+-----------------------------+ +| ARM | Neoverse-V2 | #2719103 | ARM64_ERRATUM_2701951 | ++----------------+-----------------+-----------------+-----------------------------+ | ARM | MMU-500 | #841119,826419 | N/A | +----------------+-----------------+-----------------+-----------------------------+ +----------------+-----------------+-----------------+-----------------------------+ diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 1023e896d46b..0d07ddd15bfb 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -990,6 +990,33 @@ config ARM64_ERRATUM_2645198 If unsure, say Y. +config ARM64_ERRATUM_2701951 + bool "ARM CPUs: 2701951: disable FWB on affected parts" + select ARM_SMCCC_EM + default y + help + This option adds the workaround for multiple ARM errata titled + "The core might fetch stale instruction from memory when both Stage 1 + Translation and Instruction Cache are Disabled with Stage 2 forced + Write-Back". + This affects Cortex cores: A78, A78C, A710, X1, X2, X3, and Neoverse + cores: V1, V2 and N2. + + Affected cores fail to apply the FWB override to instruction fetch + when stage1 translation is disabled, and SCTLR_EL1.I is clear. This + results in stale data being fetched and executed. Only CPUs that are + connected to a non-Arm interconnect will exhibit symptoms due to this + errata. + + Work around this problem in the driver by disabling FWB on affected + parts. The SMCCC Errata Management API is used to query firmware to + learn if the part is affected. + + If the SMCCC Errata Management API is not implemented on a platform + with an affected core, the workaround will be applied. + + If unsure, say Y. + config CAVIUM_ERRATUM_22375 bool "Cavium erratum 22375, 24313" default y diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h index 6bf013fb110d..435e5d1b49ab 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -635,6 +635,7 @@ static inline bool id_aa64pfr1_mte(u64 pfr1) void __init setup_cpu_features(void); void check_local_cpu_capabilities(void); +bool has_stage2_fwb_errata(const struct arm64_cpu_capabilities *entry, int scope); u64 read_sanitised_ftr_reg(u32 id); u64 __read_sysreg_by_encoding(u32 sys_id); diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index 307faa2b4395..55da9e588b9e 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -6,6 +6,7 @@ */ #include +#include #include #include #include @@ -137,6 +138,81 @@ cpu_clear_bf16_from_user_emulation(const struct arm64_cpu_capabilities *__unused raw_spin_unlock(®_user_mask_modification); } +bool has_stage2_fwb_errata(const struct arm64_cpu_capabilities *ignored, + int scope) +{ + u64 idr; + bool has_feature; + + /* List of CPUs which may have broken FWB support. */ + static const struct midr_range cpus[] = { +#ifdef CONFIG_ARM64_ERRATUM_2701951 + MIDR_ALL_VERSIONS(MIDR_CORTEX_A78), + MIDR_ALL_VERSIONS(MIDR_CORTEX_A78C), + MIDR_ALL_VERSIONS(MIDR_CORTEX_A710), + MIDR_ALL_VERSIONS(MIDR_CORTEX_X1), + MIDR_ALL_VERSIONS(MIDR_CORTEX_X2), + MIDR_RANGE(MIDR_CORTEX_X3, 0, 0, 1, 1), + MIDR_RANGE(MIDR_NEOVERSE_V1, 0, 0, 1, 1), + MIDR_RANGE(MIDR_NEOVERSE_V2, 0, 0, 0, 1), + MIDR_RANGE(MIDR_NEOVERSE_N2, 0, 0, 0, 2), +#endif + { /* sentinel */ }, + }; + + if (scope == ARM64_CPUCAP_SCOPE_SYSTEM) + return cpus_have_cap(ARM64_WORKAROUND_NO_FWB); + + idr = read_cpuid(ID_AA64MMFR2_EL1); + has_feature = FIELD_GET(ID_AA64MMFR2_EL1_FWB, idr); + if (!has_feature) + return false; + + if (is_midr_in_range_list(read_cpuid_id(), cpus)) { + int i; + bool fwb_broken = true; + + /* + * List of erratum numbers for these CPUs. + * It isn't possible to match these to their CPUs, as A78C has + * two erratum numbers. The errata management API will return + * 'UNKNOWN' for an erratum it doesn't recognise. + */ + static const u32 erratum_nums[] = { + 2701951, + 2701952, + 2701953, + 2712571, + 2712572, + 2712575, + 2719103, + 2728475, + }; + + /* + * The CPU is affected, but what about this configuration? + * Only firmware has the answer. Assume the part is affected, + * and query firmware for the set of erratum numbers. If one + * returns not-affected, the workaround isn't needed. + */ + for (i = 0; i < ARRAY_SIZE(erratum_nums); i++) { + int state = arm_smccc_em_cpu_features(erratum_nums[i]); + + if (state == SMCCC_EM_RET_NOT_AFFECTED) { + fwb_broken = false; + break; + } + } + + if (fwb_broken) { + pr_info_once("Stage-2 Force Write-Back disabled due to erratum #2701951\n"); + return true; + } + } + + return false; +} + #define CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max) \ .matches = is_affected_midr_range, \ .midr_range = MIDR_RANGE(model, v_min, r_min, v_max, r_max) @@ -730,6 +806,16 @@ const struct arm64_cpu_capabilities arm64_errata[] = { .cpu_enable = cpu_clear_bf16_from_user_emulation, }, #endif +#ifdef CONFIG_ARM64_ERRATUM_2701951 + { + .desc = "ARM erratum 2701951", + .capability = ARM64_WORKAROUND_NO_FWB, + .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, + .matches = has_stage2_fwb_errata, + + }, +#endif + { } }; diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 62f996006783..099bf6ad7552 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -1586,6 +1586,20 @@ static bool has_cache_dic(const struct arm64_cpu_capabilities *entry, return ctr & BIT(CTR_EL0_DIC_SHIFT); } +static bool has_stage2_fwb(const struct arm64_cpu_capabilities *entry, + int scope) +{ + bool has_feature = has_cpuid_feature(entry, scope); + + if (!has_feature) + return false; + + if (has_stage2_fwb_errata(NULL, scope)) + return false; + + return has_feature; +} + static bool __maybe_unused has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope) { @@ -2438,7 +2452,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .field_pos = ID_AA64MMFR2_EL1_FWB_SHIFT, .field_width = 4, .min_field_value = 1, - .matches = has_cpuid_feature, + .matches = has_stage2_fwb, }, { .desc = "ARMv8.4 Translation Table Level", diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps index 37b1340e9646..2e5f70ec6410 100644 --- a/arch/arm64/tools/cpucaps +++ b/arch/arm64/tools/cpucaps @@ -86,6 +86,7 @@ WORKAROUND_CAVIUM_TX2_219_PRFM WORKAROUND_CAVIUM_TX2_219_TVM WORKAROUND_CLEAN_CACHE WORKAROUND_DEVICE_LOAD_ACQUIRE +WORKAROUND_NO_FWB WORKAROUND_NVIDIA_CARMEL_CNP WORKAROUND_QCOM_FALKOR_E1003 WORKAROUND_REPEAT_TLBI From patchwork Thu Mar 30 16:51:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Morse X-Patchwork-Id: 669207 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F10DFC77B60 for ; Thu, 30 Mar 2023 16:53:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231651AbjC3Qxh (ORCPT ); Thu, 30 Mar 2023 12:53:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35998 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231689AbjC3QxQ (ORCPT ); Thu, 30 Mar 2023 12:53:16 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id BF95B1BC3 for ; Thu, 30 Mar 2023 09:53:01 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C46211682; Thu, 30 Mar 2023 09:53:45 -0700 (PDT) Received: from eglon.cambridge.arm.com (eglon.cambridge.arm.com [10.1.196.177]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E7FCB3F6C4; Thu, 30 Mar 2023 09:52:59 -0700 (PDT) From: James Morse To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Cc: Catalin Marinas , Will Deacon , Mark Rutland , Lorenzo Pieralisi , Sudeep Holla , Marc Zyngier , Oliver Upton , James Morse , Rob Herring , Krzysztof Kozlowski Subject: [PATCH 6/6] arm64: errata: Add a commandline option to enable/disable #2701951 Date: Thu, 30 Mar 2023 17:51:28 +0100 Message-Id: <20230330165128.3237939-7-james.morse@arm.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230330165128.3237939-1-james.morse@arm.com> References: <20230330165128.3237939-1-james.morse@arm.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Erratum #2701951 affects the FWB feature in a number of CPUs, but is only going to be visible on parts that don't use an arm interconnect. This is not something the operating system can discover, it has to be described by platform firmware. The firmware discovery API is not deployed on existing systems. Add a commandline option to allow the workaround to override the value from firmware, or provide a value if the firmware is not implemented. The property is named arm64.arm-interconnect, as this is the description in the 'configurations affected' section of the erratum. Signed-off-by: James Morse --- .../admin-guide/kernel-parameters.txt | 4 +++ arch/arm64/kernel/cpu_errata.c | 36 +++++++++++++++++++ 2 files changed, 40 insertions(+) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index 6221a1d057dd..5898fde6a9e4 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -391,6 +391,10 @@ arcrimi= [HW,NET] ARCnet - "RIM I" (entirely mem-mapped) cards Format: ,, + arm64.arm-interconnect [ARM64] + Indicates the FWB erratum can be disabled because this + SoC uses an arm interconnect. + arm64.nobti [ARM64] Unconditionally disable Branch Target Identification support diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index 55da9e588b9e..c5570904e8b4 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -138,6 +138,32 @@ cpu_clear_bf16_from_user_emulation(const struct arm64_cpu_capabilities *__unused raw_spin_unlock(®_user_mask_modification); } +static enum { + FWB_WA_FORCED_ON = 1, + FWB_WA_UNKNOWN = 0, + FWB_WA_FORCED_OFF = -1, +} __fwb_workaround_forced; +#ifdef CONFIG_ARM64_ERRATUM_2701951 +static int __init parse_fwb_workaround_cmdline_override(char *str) +{ + bool arm_interconnect; + int ret = kstrtobool(str, &arm_interconnect); + + if (ret) + return ret; + + /* + * Erratum #2701951's "Configurations Affected" says the erratum can + * only be seen on SoC's "that do not use Arm interconnect IP." + */ + if (arm_interconnect) + __fwb_workaround_forced = FWB_WA_FORCED_OFF; + else + __fwb_workaround_forced = FWB_WA_FORCED_ON; + return 0; +} +early_param("arm64.arm-interconnect", parse_fwb_workaround_cmdline_override); +#endif /* CONFIG_ARM64_ERRATUM_2701951 */ bool has_stage2_fwb_errata(const struct arm64_cpu_capabilities *ignored, int scope) { @@ -205,9 +231,19 @@ bool has_stage2_fwb_errata(const struct arm64_cpu_capabilities *ignored, } if (fwb_broken) { + if (__fwb_workaround_forced == FWB_WA_FORCED_OFF) { + pr_info_once("Workaround for erratum #2701951 disabled by command-line option\n"); + return false; + } pr_info_once("Stage-2 Force Write-Back disabled due to erratum #2701951\n"); return true; } + + /* Allow the commandline to override whatever firmware said */ + if (has_feature && __fwb_workaround_forced == FWB_WA_FORCED_ON) { + pr_info_once("Workaround for erratum #2701951 enabled by command-line option\n"); + return true; + } } return false;