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[83.9.3.225]) by smtp.gmail.com with ESMTPSA id n7-20020a2e7207000000b002986854f27dsm134573ljc.23.2023.03.30.18.14.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Mar 2023 18:14:58 -0700 (PDT) From: Konrad Dybcio Date: Fri, 31 Mar 2023 03:14:50 +0200 Subject: [PATCH v3 2/5] drm/msm/a6xx: Add support for A650 speed binning MIME-Version: 1.0 Message-Id: <20230331-topic-konahana_speedbin-v3-2-2dede22dd7f7@linaro.org> References: <20230331-topic-konahana_speedbin-v3-0-2dede22dd7f7@linaro.org> In-Reply-To: <20230331-topic-konahana_speedbin-v3-0-2dede22dd7f7@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1680225294; l=1412; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=42U2yCRDQAALlywjy8FiLoqbAeo9f7qbW4rrzl+BgmY=; b=dwyPUzW5kyB7cpYIsra0jqgoc9iICEbp333fN21/hW1uI9eAgh9lyZx3qLIhTqeBJe7Uf2/WSJLw 8UXuc7NcD4q+iFYH51Ld8y73WVcYc3NMkKeHz0Kfjv8gbc3apCoK X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add support for matching QFPROM fuse values to get the correct speed bin on A650 (SM8250) GPUs. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 663090973c1b..2afc160cf06a 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1900,6 +1900,21 @@ static u32 a640_get_speed_bin(u32 fuse) return UINT_MAX; } +static u32 a650_get_speed_bin(u32 fuse) +{ + if (fuse == 0) + return 0; + else if (fuse == 1) + return 1; + /* Yep, 2 and 3 are swapped! :/ */ + else if (fuse == 2) + return 3; + else if (fuse == 3) + return 2; + + return UINT_MAX; +} + static u32 adreno_7c3_get_speed_bin(u32 fuse) { if (fuse == 0) @@ -1928,6 +1943,9 @@ static u32 fuse_to_supp_hw(struct device *dev, struct adreno_rev rev, u32 fuse) if (adreno_cmp_rev(ADRENO_REV(6, 4, 0, ANY_ID), rev)) val = a640_get_speed_bin(fuse); + if (adreno_cmp_rev(ADRENO_REV(6, 5, 0, ANY_ID), rev)) + val = a650_get_speed_bin(fuse); + if (val == UINT_MAX) { DRM_DEV_ERROR(dev, "missing support for speed-bin: %u. Some OPPs may not be supported by hardware\n", From patchwork Fri Mar 31 01:14:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 669182 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 594D9C7619A for ; Fri, 31 Mar 2023 01:15:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229844AbjCaBPI (ORCPT ); Thu, 30 Mar 2023 21:15:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33946 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229887AbjCaBPD (ORCPT ); Thu, 30 Mar 2023 21:15:03 -0400 Received: from mail-lj1-x236.google.com (mail-lj1-x236.google.com [IPv6:2a00:1450:4864:20::236]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CC6DE12046 for ; Thu, 30 Mar 2023 18:15:01 -0700 (PDT) Received: by mail-lj1-x236.google.com with SMTP id bx10so3159260ljb.8 for ; Thu, 30 Mar 2023 18:15:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680225301; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=LYSzPLydtmK2JKcRhPPJf/WCaXdAIMHqEJnKMvnOMFk=; b=QB9AJhVUigoXflzaqK7rWan9FMupoyp/wjPCEWPrRuOD6jYiWwHo82ekHqx8y7Y4c6 XGMdr2D1+kFtG4J0IJ2gdzEMiwAhFJQus3wIcHXSOsspm+P2L8mTLnaJ3up3yWo1iu2J QTR240DGs6kRd2Gk0jOFqRqS1/A3CBnNJcyYdapa/aFt+/jC3Kk/oUbZH+BXd8maBZKz gF0R61U6wNxSJ+S03+AdTG8HT3oh99Cb1WtFSo3Kmhll/6/udnBPTRVoIZkEV8XNdVMU AzADUEQ9zV3iW4zeySzI4KNJaCD3WmsAD3S9OwPwhwOHa0P7U6jbaVSDOe024omWVN0C hJ0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680225301; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LYSzPLydtmK2JKcRhPPJf/WCaXdAIMHqEJnKMvnOMFk=; b=ZpaJ7BPh41sP4eEPBMWCMnWeV3qCuN9W6RSY/hpBo4VOEARnArDxWjuzyNuWlVsBv0 UGoQ0rJ1H9Jdqo1+qcDQvNpeGMEqYRlXlld1Hc0fMY94EV2lm9AJs090ia7NGAjv8DWV meXtn+Gx+jMzcCZHETnBWkN4bOyWN/pd00wzucZiM9hgznCwE0+WFGWBYj+i7V9xQRKn vt8WDHuj4C8R6bmm+H3pNI8CcCN2eGpxKZKX+rTKWEsJatMrzaPTIBMvK7k2rxvBDjZi vnVedoDh8ZygclotGfbwqHGuQy6bQ/DUeB6XvxPh7hE1Wm/Cx3OKb/XhUkG66CIgmEpu H8UA== X-Gm-Message-State: AAQBX9dJErzUcPSi8Cb9fbt+JPmzg7Hg3J4yP/neRk0UMZ12v3jj4vM8 7TFZNJxxZyLJyPaLP8qHNMuQLQ== X-Google-Smtp-Source: AKy350bM6SamDQIPnoK5ZV65Xwd526bmZB2kbPdT3rNXJMHLa+/Z0XO3jm3EO29ULFIcPuQvnUET+w== X-Received: by 2002:a2e:888f:0:b0:299:a8e2:2181 with SMTP id k15-20020a2e888f000000b00299a8e22181mr8005791lji.43.1680225301285; Thu, 30 Mar 2023 18:15:01 -0700 (PDT) Received: from [192.168.1.101] (abxj225.neoplus.adsl.tpnet.pl. [83.9.3.225]) by smtp.gmail.com with ESMTPSA id n7-20020a2e7207000000b002986854f27dsm134573ljc.23.2023.03.30.18.14.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Mar 2023 18:15:00 -0700 (PDT) From: Konrad Dybcio Date: Fri, 31 Mar 2023 03:14:52 +0200 Subject: [PATCH v3 4/5] arm64: dts: qcom: sm8150: Add GPU speedbin support MIME-Version: 1.0 Message-Id: <20230331-topic-konahana_speedbin-v3-4-2dede22dd7f7@linaro.org> References: <20230331-topic-konahana_speedbin-v3-0-2dede22dd7f7@linaro.org> In-Reply-To: <20230331-topic-konahana_speedbin-v3-0-2dede22dd7f7@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1680225294; l=2592; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=koZEmO1fkF/bnaYkvF93NsF8DQclVperHMMUdURxE4o=; b=j2Z9eJ2Mqm4KOtIUJKp9MRUSZpdT9SbI2GcYYME7XSdmYXJ3KKnNeJZ2tOf0YD3GBAikO/WhSGNM fPPJDeCQD3HadP8gcr+3JLBcWjvTqcN/z0+zY0kYv64lwnnN4BDp X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org SM8150 has (at least) two GPU speed bins. With the support added on the driver side, wire up bin detection in the DTS to restrict lower-quality SKUs from running at frequencies they were not validated at. Tested-by: Marijn Suijten # On Sony Xperia 5 (speed bin 0x3) Reviewed-by: Marijn Suijten Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 880483922f22..e4230877555d 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -952,6 +952,17 @@ ethernet: ethernet@20000 { status = "disabled"; }; + qfprom: efuse@784000 { + compatible = "qcom,sm8150-qfprom", "qcom,qfprom"; + reg = <0 0x00784000 0 0x8ff>; + #address-cells = <1>; + #size-cells = <1>; + + gpu_speed_bin: gpu_speed_bin@133 { + reg = <0x133 0x1>; + bits = <5 3>; + }; + }; qupv3_id_0: geniqup@8c0000 { compatible = "qcom,geni-se-qup"; @@ -2169,44 +2180,52 @@ gpu: gpu@2c00000 { qcom,gmu = <&gmu>; + nvmem-cells = <&gpu_speed_bin>; + nvmem-cell-names = "speed_bin"; + status = "disabled"; zap-shader { memory-region = <&gpu_mem>; }; - /* note: downstream checks gpu binning for 675 Mhz */ gpu_opp_table: opp-table { compatible = "operating-points-v2"; opp-675000000 { opp-hz = /bits/ 64 <675000000>; opp-level = ; + opp-supported-hw = <0x2>; }; opp-585000000 { opp-hz = /bits/ 64 <585000000>; opp-level = ; + opp-supported-hw = <0x3>; }; opp-499200000 { opp-hz = /bits/ 64 <499200000>; opp-level = ; + opp-supported-hw = <0x3>; }; opp-427000000 { opp-hz = /bits/ 64 <427000000>; opp-level = ; + opp-supported-hw = <0x3>; }; opp-345000000 { opp-hz = /bits/ 64 <345000000>; opp-level = ; + opp-supported-hw = <0x3>; }; opp-257000000 { opp-hz = /bits/ 64 <257000000>; opp-level = ; + opp-supported-hw = <0x3>; }; }; };