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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id l12-20020a5d560c000000b002cfe685bfd6sm2339831wrv.108.2023.03.31.07.50.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 31 Mar 2023 07:50:47 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 1/3] target/arm: Pass ARMMMUFaultInfo to merge_syn_data_abort() Date: Fri, 31 Mar 2023 15:50:43 +0100 Message-Id: <20230331145045.2584941-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230331145045.2584941-1-peter.maydell@linaro.org> References: <20230331145045.2584941-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org We already pass merge_syn_data_abort() two fields from the ARMMMUFaultInfo struct, and we're about to want to use a third field. Refactor to just pass a pointer to the fault info. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- target/arm/tcg/tlb_helper.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c index 31eb77f7df9..1a61adb8a68 100644 --- a/target/arm/tcg/tlb_helper.c +++ b/target/arm/tcg/tlb_helper.c @@ -24,9 +24,9 @@ bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx) } static inline uint32_t merge_syn_data_abort(uint32_t template_syn, + ARMMMUFaultInfo *fi, unsigned int target_el, - bool same_el, bool ea, - bool s1ptw, bool is_write, + bool same_el, bool is_write, int fsc) { uint32_t syn; @@ -43,9 +43,9 @@ static inline uint32_t merge_syn_data_abort(uint32_t template_syn, * ISS encoding for an exception from a Data Abort, the * ISV field. */ - if (!(template_syn & ARM_EL_ISV) || target_el != 2 || s1ptw) { + if (!(template_syn & ARM_EL_ISV) || target_el != 2 || fi->s1ptw) { syn = syn_data_abort_no_iss(same_el, 0, - ea, 0, s1ptw, is_write, fsc); + fi->ea, 0, fi->s1ptw, is_write, fsc); } else { /* * Fields: IL, ISV, SAS, SSE, SRT, SF and AR come from the template @@ -54,7 +54,7 @@ static inline uint32_t merge_syn_data_abort(uint32_t template_syn, */ syn = syn_data_abort_with_iss(same_el, 0, 0, 0, 0, 0, - ea, 0, s1ptw, is_write, fsc, + fi->ea, 0, fi->s1ptw, is_write, fsc, true); /* Merge the runtime syndrome with the template syndrome. */ syn |= template_syn; @@ -117,9 +117,8 @@ void arm_deliver_fault(ARMCPU *cpu, vaddr addr, syn = syn_insn_abort(same_el, fi->ea, fi->s1ptw, fsc); exc = EXCP_PREFETCH_ABORT; } else { - syn = merge_syn_data_abort(env->exception.syndrome, target_el, - same_el, fi->ea, fi->s1ptw, - access_type == MMU_DATA_STORE, + syn = merge_syn_data_abort(env->exception.syndrome, fi, target_el, + same_el, access_type == MMU_DATA_STORE, fsc); if (access_type == MMU_DATA_STORE && arm_feature(env, ARM_FEATURE_V6)) { From patchwork Fri Mar 31 14:50:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 668853 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d08:0:0:0:0:0 with SMTP id z8csp535762wrt; Fri, 31 Mar 2023 07:52:07 -0700 (PDT) X-Google-Smtp-Source: AKy350aRExZ2bVomlKAZoUsCdsrPL+K1JqlFCppR7Lqs6epEEv88qP68scpuDyvm36NQC/mgmkmr X-Received: by 2002:a05:6214:21a8:b0:5e0:3bbf:78c5 with SMTP id t8-20020a05621421a800b005e03bbf78c5mr9321719qvc.37.1680274327258; Fri, 31 Mar 2023 07:52:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680274327; cv=none; d=google.com; s=arc-20160816; b=pQvXG17UIAgTykrLYDefzAI2G9Cq67ItzfGZ/0M7Yv4zYAH0AJuyPrqoqATKOWB5zH 5pDdLkiTScDWZpuLZtU+9i4AgKi5vNiZoBD59OKBYoi+UPCeOt1oxs48NPlTohvVk+vX dArv1TnDNHHrIfsBRKijHgi4+XH8yNs16UkfaTjbZ4fx2Hw/Rf7Ih0nd1CnguazhU45S dvxzLCG06FgxTtbylwa8JUQDhgMke5R6tMCOFYKYOlpH91OBD3YkLt9RSQ88L5YVg2Pv ZaGerrXSihZHVIOy1GbPLES8PY9xnbPJ2byQQHy82SQUdswOqHJt3TzvjDCVhoyK2YWJ efIA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Ob8zaLRhLK1pUzR/HANUMOjhD/K+he8dJVxHdozinP4=; b=jLm9OH+7r8ROfIW/+++GELvGPhbS9eLo9FhIxdrX3pX+HN+b6RpWt+W5TixJYwm94B 5iMXuWv9K1cJQfQvXG1YRvPpvSr0kmLUrBgjihaKT0W9NKJV0QdexPInj40V+uBCFcoE MeGarSGETtvAt6ENkFJAvMhB+sNk8VmnaVfmFNLfZqAJSur0Ig7Yfx/4PTtDnJxDmoRN vQLOOFPedfNeZ3LkpcCACAznIHvwLV+O6XTbnd16+bTX1Vt1NlSxcF7uWniX7EzFbKDJ 1qpkvfrQ6ZcZlO4GADloN/LkfTuYZPbBAeKX6C47wPZYdS/p3hunLAHfhqxw3sunHUM2 qSHQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=KbmOtAnp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id l12-20020a5d560c000000b002cfe685bfd6sm2339831wrv.108.2023.03.31.07.50.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 31 Mar 2023 07:50:47 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 2/3] target/arm: Don't set ISV when reporting stage 1 faults in ESR_EL2 Date: Fri, 31 Mar 2023 15:50:44 +0100 Message-Id: <20230331145045.2584941-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230331145045.2584941-1-peter.maydell@linaro.org> References: <20230331145045.2584941-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The syndrome value reported to ESR_EL2 should only contain the detailed instruction syndrome information when the fault has been caused by a stage 2 abort, not when the fault was a stage 1 abort (i.e. caused by execution at EL2). We were getting this wrong and reporting the detailed ISV information all the time. Fix the bug by checking fi->stage2. Add a TODO comment noting the cases where we'll have to come back and revisit this when we implement FEAT_LS64 and friends. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/tcg/tlb_helper.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c index 1a61adb8a68..d5a89bc5141 100644 --- a/target/arm/tcg/tlb_helper.c +++ b/target/arm/tcg/tlb_helper.c @@ -32,8 +32,9 @@ static inline uint32_t merge_syn_data_abort(uint32_t template_syn, uint32_t syn; /* - * ISV is only set for data aborts routed to EL2 and - * never for stage-1 page table walks faulting on stage 2. + * ISV is only set for stage-2 data aborts routed to EL2 and + * never for stage-1 page table walks faulting on stage 2 + * or for stage-1 faults. * * Furthermore, ISV is only set for certain kinds of load/stores. * If the template syndrome does not have ISV set, we should leave @@ -42,8 +43,14 @@ static inline uint32_t merge_syn_data_abort(uint32_t template_syn, * See ARMv8 specs, D7-1974: * ISS encoding for an exception from a Data Abort, the * ISV field. + * + * TODO: FEAT_LS64/FEAT_LS64_V/FEAT_SL64_ACCDATA: Translation, + * Access Flag, and Permission faults caused by LD64B, ST64B, + * ST64BV, or ST64BV0 insns report syndrome info even for stage-1 + * faults and regardless of the target EL. */ - if (!(template_syn & ARM_EL_ISV) || target_el != 2 || fi->s1ptw) { + if (!(template_syn & ARM_EL_ISV) || target_el != 2 + || fi->s1ptw || !fi->stage2) { syn = syn_data_abort_no_iss(same_el, 0, fi->ea, 0, fi->s1ptw, is_write, fsc); } else { From patchwork Fri Mar 31 14:50:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 668852 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d08:0:0:0:0:0 with SMTP id z8csp535672wrt; Fri, 31 Mar 2023 07:51:55 -0700 (PDT) X-Google-Smtp-Source: AKy350YJf1CE7r6AwZZGAnTsbwMzV3EXyBykXLZErF4Keicif9IRMEtzw9lFY9P5XDDq7iq30jOP X-Received: by 2002:a05:6214:409:b0:5bd:4363:fbec with SMTP id z9-20020a056214040900b005bd4363fbecmr45621134qvx.27.1680274315101; Fri, 31 Mar 2023 07:51:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680274315; cv=none; d=google.com; s=arc-20160816; b=s0JY0bilFi6ZvzquuXuBjA4H0LRXl5ts5OXj++PpEEBonzJZKBkCsRJl77D9OFX3dx Ax+ICU60ofMGUgUd38ToW6pfCoWSEHCmMKTQUgOQWE89Jeb4ZNbYV4gG1bsY4Rnwx5ui LWySbNJLYXfPaYonaYOxrgnzkVpEeOvC8+fTgwhnAKNKn9lQl9aEKNDxw4ZNjM/jsYlj BM1OgdoO2LQopF4QdwQrx1LebvakLqStSNSRLfGOm3Y6zfkIt9DxwGvjidpDzw27wQdj MGcxrWocvKqY//9GUtds+jXBFKZyxpXgFZINWs44wJtwJr9VW5QsMtLACrGDyikuQZr3 B/XQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=aMsJpOiutF8EzuYcJAT/HhM6ChC4opwqxSHP+TBtq/M=; b=VDpHPME3oI+Ycr/xWiF0ccad24I6+blqaKkgTHq3l2XzWM1hR37aDISV/RiT2OjxnT FRb4hJvNTQz0OkPlrMMBNKzPfpDb7oSUACPor8abWJJi/xVaE+4i/ekB+T8tAobFEgxL hfmacSl7Qqk5RCgrN/WeGm3FfxZN3+UJMEDOhAH+ET0XgeA9M3ekYzxP+cbvSkRG90RX DSBV6emQlzrfGS5XHxlRV+uUfC1eS+chGbzbAAirOEG8DmPEozUbSfbITOqv9tACL0DW GMFuJTm5tmtBzxTZNt8csOzTTn0y2CtyVTpxxukgUokUPWfqxIzYI90H48QV+v5YXqE5 WkOA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=nwn8Qs8J; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id l12-20020a5d560c000000b002cfe685bfd6sm2339831wrv.108.2023.03.31.07.50.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 31 Mar 2023 07:50:47 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 3/3] target/arm: Implement FEAT_PAN3 Date: Fri, 31 Mar 2023 15:50:45 +0100 Message-Id: <20230331145045.2584941-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230331145045.2584941-1-peter.maydell@linaro.org> References: <20230331145045.2584941-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org FEAT_PAN3 adds an EPAN bit to SCTLR_EL1 and SCTLR_EL2, which allows the PAN bit to make memory non-privileged-read/write if it is user-executable as well as if it is user-read/write. Implement this feature and enable it in the AArch64 'max' CPU. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- docs/system/arm/emulation.rst | 1 + target/arm/cpu.h | 5 +++++ target/arm/cpu64.c | 2 +- target/arm/ptw.c | 14 +++++++++++++- 4 files changed, 20 insertions(+), 2 deletions(-) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 2062d712610..73389878755 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -56,6 +56,7 @@ the following architecture extensions: - FEAT_MTE3 (MTE Asymmetric Fault Handling) - FEAT_PAN (Privileged access never) - FEAT_PAN2 (AT S1E1R and AT S1E1W instruction variants affected by PSTATE.PAN) +- FEAT_PAN3 (Support for SCTLR_ELx.EPAN) - FEAT_PAuth (Pointer authentication) - FEAT_PMULL (PMULL, PMULL2 instructions) - FEAT_PMUv3p1 (PMU Extensions v3.1) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c097cae9882..d469a2637b3 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3823,6 +3823,11 @@ static inline bool isar_feature_aa64_ats1e1(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 2; } +static inline bool isar_feature_aa64_pan3(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 3; +} + static inline bool isar_feature_aa64_hcx(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HCX) != 0; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 0fb07cc7b6d..735ca541634 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -1302,7 +1302,7 @@ static void aarch64_max_initfn(Object *obj) t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1); /* FEAT_VHE */ t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* FEAT_HPDS */ t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1); /* FEAT_LOR */ - t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* FEAT_PAN2 */ + t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 3); /* FEAT_PAN3 */ t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* FEAT_XNX */ t = FIELD_DP64(t, ID_AA64MMFR1, ETS, 1); /* FEAT_ETS */ t = FIELD_DP64(t, ID_AA64MMFR1, HCX, 1); /* FEAT_HCX */ diff --git a/target/arm/ptw.c b/target/arm/ptw.c index ec3f51782aa..499308fcb07 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -947,6 +947,7 @@ static int get_S2prot(CPUARMState *env, int s2ap, int xn, bool s1_is_el0) static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64, int ap, int ns, int xn, int pxn) { + ARMCPU *cpu = env_archcpu(env); bool is_user = regime_is_user(env, mmu_idx); int prot_rw, user_rw; bool have_wxn; @@ -958,8 +959,19 @@ static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64, if (is_user) { prot_rw = user_rw; } else { + /* + * PAN controls can forbid data accesses but don't affect insn fetch. + * Plain PAN forbids data accesses if EL0 has data permissions; + * PAN3 forbids data accesses if EL0 has either data or exec perms. + * Note that for AArch64 the 'user can exec' case is exactly !xn. + * We make the IMPDEF choices that SCR_EL3.SIF and Realm EL2&0 + * do not affect EPAN. + */ if (user_rw && regime_is_pan(env, mmu_idx)) { - /* PAN forbids data accesses but doesn't affect insn fetch */ + prot_rw = 0; + } else if (cpu_isar_feature(aa64_pan3, cpu) && is_aa64 && + regime_is_pan(env, mmu_idx) && + (regime_sctlr(env, mmu_idx) & SCTLR_EPAN) && !xn) { prot_rw = 0; } else { prot_rw = simple_ap_to_rw_prot_is_user(ap, false);