From patchwork Wed May 22 22:28:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 164901 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp1410945ili; Wed, 22 May 2019 15:28:50 -0700 (PDT) X-Google-Smtp-Source: APXvYqz+/8ytrYGY6lSluIkoT6+srQgL624jP3BKMu7IumKFgWfSYISh7gm7OPp9dlYpmUAhR7Jb X-Received: by 2002:a17:906:1fc4:: with SMTP id e4mr53832260ejt.81.1558564130569; Wed, 22 May 2019 15:28:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1558564130; cv=none; d=google.com; s=arc-20160816; b=YuIW4PEALbJdGm5pwNxgEOSsXfbm0wqwAe45c8+XelyIUux3V5Y0MCH64VTkBsai4f H1/x6W9xi7INsJiwg+3ZZS0+zsaKLUZigrr9PX9BjSrZbLpZ9qUdKJH3Cg+fOQcoHaMn KQmTeqdvo+BuZqj2hadyVlnBvxPSOw7UdMWv5hdtlpcAwKrbt4iFrLk4LEbBy16Rc6JE GCZ4+W1qKWsrX8ng2ukkpT5K/C3m8DJ/ET8HXRPRNjmByZJTilB7KIxpPnutiqSQJxCK lMMYb5GEeyx+xZH8H7//mIX6NNNtpial2zHNmQ8SHpmrjgCXCt12tkYo6xKu59zrFpiT QsTA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=CNtLSsppNDq+qCEdta/UyzFB0xSoIc+vMFY+eO0LpIo=; b=m74Y3dKn6UKsQJ5DCAi+6Kh1y8zyJ2KKNvIKUIHPL6u8aOoCLauZhzNtEq2OtineJH q9n9YX4Mgx8QgD+cwjIy3UCbuSlkdnvDUMIGsvuIGkwW/5hqt0kgY+e1iVV520M5jfNd l8t8dMcjgDg87F7BRQU/Ud1i/qCiQBDU1Ky95bf3QcIDvaBsPdvjBh6pv4k7BvnPN1Cl lg5gTGtVjnyXkKyA22OCQ0zK7iS6lJwv1Gro7IFNDDnjB1UAO6yfoBjKof6EU32BpM4L 5R6+QJpuMzq8KaetLP9UneXFzUY7tfkAX7/GNSXGqtAjZSlh1scVLQW2S0SEYBoyA4Sv TgGg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=BJO33EC3; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::b44 Subject: [Qemu-devel] [PULL 01/16] tcg/i386: Fix dupi/dupm for avx1 and 32-bit hosts X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The VBROADCASTSD instruction only allows %ymm registers as destination. Rather than forcing VEX.L and writing to the entire 256-bit register, revert to using MOVDDUP with an %xmm register. This is sufficient for an avx1 host since we do not support TCG_TYPE_V256 for that case. Also fix the 32-bit avx2, which should have used VPBROADCASTW. Fixes: 1e262b49b533 Tested-by: Mark Cave-Ayland Reported-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.inc.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) -- 2.17.1 diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index aafd01cb49..b3601446cd 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -358,6 +358,7 @@ static inline int tcg_target_const_match(tcg_target_long val, TCGType type, #define OPC_MOVBE_MyGy (0xf1 | P_EXT38) #define OPC_MOVD_VyEy (0x6e | P_EXT | P_DATA16) #define OPC_MOVD_EyVy (0x7e | P_EXT | P_DATA16) +#define OPC_MOVDDUP (0x12 | P_EXT | P_SIMDF2) #define OPC_MOVDQA_VxWx (0x6f | P_EXT | P_DATA16) #define OPC_MOVDQA_WxVx (0x7f | P_EXT | P_DATA16) #define OPC_MOVDQU_VxWx (0x6f | P_EXT | P_SIMDF3) @@ -921,7 +922,7 @@ static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, } else { switch (vece) { case MO_64: - tcg_out_vex_modrm_offset(s, OPC_VBROADCASTSD, r, 0, base, offset); + tcg_out_vex_modrm_offset(s, OPC_MOVDDUP, r, 0, base, offset); break; case MO_32: tcg_out_vex_modrm_offset(s, OPC_VBROADCASTSS, r, 0, base, offset); @@ -963,12 +964,12 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type, } else if (have_avx2) { tcg_out_vex_modrm_pool(s, OPC_VPBROADCASTQ + vex_l, ret); } else { - tcg_out_vex_modrm_pool(s, OPC_VBROADCASTSD, ret); + tcg_out_vex_modrm_pool(s, OPC_MOVDDUP, ret); } new_pool_label(s, arg, R_386_PC32, s->code_ptr - 4, -4); } else { if (have_avx2) { - tcg_out_vex_modrm_pool(s, OPC_VBROADCASTSD + vex_l, ret); + tcg_out_vex_modrm_pool(s, OPC_VPBROADCASTW + vex_l, ret); } else { tcg_out_vex_modrm_pool(s, OPC_VBROADCASTSS, ret); } From patchwork Wed May 22 22:28:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 164903 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp1413110ili; Wed, 22 May 2019 15:31:21 -0700 (PDT) X-Google-Smtp-Source: APXvYqz3oHn6MecA/0Obe+171sop5SMC2j/i0v2nUB3U6IthYlVQU9K3Mv1EH/rHsO2OfCda8lqQ X-Received: by 2002:a17:906:90d6:: with SMTP id v22mr62124564ejw.183.1558564281354; Wed, 22 May 2019 15:31:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1558564281; cv=none; d=google.com; s=arc-20160816; b=PmvwcpKiTCRRYWuLWyhQPey7N2FJVDSRE5HTKnAtM+3TDgyGsSd+hhNKZb81Y2xFdA h7Gk2FWGnusT8VRdxyAiL85IDKV8xdjQLMw9RswiGCjN+NOa/AZe56nf4lU0QYe4ghJN tujTp+sNq5Q6wFFHVrr/b4P0y34wzud7AzOHQ9qnpMdBnit9yXpzjLzARvONRBXtl3Ke D1LaMbvqAz5FDVJ2xx5r9LMrlt+/4ETC+zMT/x6C1jaYZ7oaqm8RfQ0PzsaoYYtoLati yw/RSP7asGGeAk549GF18BxmST/qRuuFvxeHIhnkcWlmcch+bzgNRo8PALacFjTts9GI 0xmg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=oqAGJXCcrmzUdmSG3sZCijkOSbKbEdDFHwT2UnQhICM=; b=i4wYHgfC7xxAstH1o8mY4I/ya0bQwUUiIMNbS0UgRxX7kOl3y5ODlafKsfRYHHCIqT VwDIvFgp0MkJVSNLlSuGhcBeUOT4LomMP2eDYW5Z6fiYpjQtfNTEH6vmHc5DFXpl9LR1 8wCgPomC6D0n7JANsKWtl8LOe8ZtXGxCSIgYm9E+7tMSJAnE9HAAkyfz4MD5xSRMYbRA Lcn7rjs4YMYff+z+MkB5A9E+b3ZRnVgPGEwU+h8Qvq8hmqTlVioIlDxsbutvxoLqS8Ia ndnJN0tlnXvBc4pG1N0KggQc9cGK+tUzOxSnHQ/oPsFLMhhy9ckwpjruO5hebMb73aqZ BpiA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=LdTUrcB0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::b2e Subject: [Qemu-devel] [PULL 02/16] tcg: Fix missing checks and clears in tcg_gen_gvec_dup_mem X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The paths through tcg_gen_dup_mem_vec and through MO_128 were missing the check_size_align. The path through MO_128 was also missing the expand_clr. This last was not visible because the only user is ARM SVE, which would set oprsz == maxsz, and not require the clear. Fix by adding the check_size_align and using do_dup directly instead of duplicating the check in tcg_gen_gvec_dup_{i32,i64}. Signed-off-by: Richard Henderson --- tcg/tcg-op-gvec.c | 48 ++++++++++++++++++++++++----------------------- 1 file changed, 25 insertions(+), 23 deletions(-) -- 2.17.1 diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index 338ddd9d9e..bbf70e3cd9 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -1446,36 +1446,35 @@ void tcg_gen_gvec_dup_i64(unsigned vece, uint32_t dofs, uint32_t oprsz, void tcg_gen_gvec_dup_mem(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t oprsz, uint32_t maxsz) { + check_size_align(oprsz, maxsz, dofs); if (vece <= MO_64) { - TCGType type = choose_vector_type(0, vece, oprsz, 0); + TCGType type = choose_vector_type(NULL, vece, oprsz, 0); if (type != 0) { TCGv_vec t_vec = tcg_temp_new_vec(type); tcg_gen_dup_mem_vec(vece, t_vec, cpu_env, aofs); do_dup_store(type, dofs, oprsz, maxsz, t_vec); tcg_temp_free_vec(t_vec); - return; + } else if (vece <= MO_32) { + TCGv_i32 in = tcg_temp_new_i32(); + switch (vece) { + case MO_8: + tcg_gen_ld8u_i32(in, cpu_env, aofs); + break; + case MO_16: + tcg_gen_ld16u_i32(in, cpu_env, aofs); + break; + default: + tcg_gen_ld_i32(in, cpu_env, aofs); + break; + } + do_dup(vece, dofs, oprsz, maxsz, in, NULL, 0); + tcg_temp_free_i32(in); + } else { + TCGv_i64 in = tcg_temp_new_i64(); + tcg_gen_ld_i64(in, cpu_env, aofs); + do_dup(vece, dofs, oprsz, maxsz, NULL, in, 0); + tcg_temp_free_i64(in); } - } - if (vece <= MO_32) { - TCGv_i32 in = tcg_temp_new_i32(); - switch (vece) { - case MO_8: - tcg_gen_ld8u_i32(in, cpu_env, aofs); - break; - case MO_16: - tcg_gen_ld16u_i32(in, cpu_env, aofs); - break; - case MO_32: - tcg_gen_ld_i32(in, cpu_env, aofs); - break; - } - tcg_gen_gvec_dup_i32(vece, dofs, oprsz, maxsz, in); - tcg_temp_free_i32(in); - } else if (vece == MO_64) { - TCGv_i64 in = tcg_temp_new_i64(); - tcg_gen_ld_i64(in, cpu_env, aofs); - tcg_gen_gvec_dup_i64(MO_64, dofs, oprsz, maxsz, in); - tcg_temp_free_i64(in); } else { /* 128-bit duplicate. */ /* ??? Dup to 256-bit vector. */ @@ -1504,6 +1503,9 @@ void tcg_gen_gvec_dup_mem(unsigned vece, uint32_t dofs, uint32_t aofs, tcg_temp_free_i64(in0); tcg_temp_free_i64(in1); } + if (oprsz < maxsz) { + expand_clr(dofs + oprsz, maxsz - oprsz); + } } } From patchwork Wed May 22 22:28:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 164904 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp1413242ili; Wed, 22 May 2019 15:31:30 -0700 (PDT) X-Google-Smtp-Source: APXvYqy4Yz2TSnHvs8y0C1qwcwi4nwuuVOqDLhHODTY8iVeM5yCxEsvzrrSp3v2n92onAt2MXXY9 X-Received: by 2002:a05:6402:1812:: with SMTP id g18mr92738770edy.273.1558564290257; Wed, 22 May 2019 15:31:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1558564290; cv=none; d=google.com; s=arc-20160816; b=qHVBCkxfpZ7gFismX5Ac6A0+0jUFvESOhgo0BaZjsZDz5BDc1rCXXIMrnddyHOOLLc /k5jyh6AOoSwBPExwFdAzGzzIBHp9HGSjBsdrs8XAgkAcLqkgE+N+fdKlb8aRfuVkoat Rwv6iewAaaPcjZvyYAPY1OO3b5fpCLTTJ7lCDetTuMMAzlyRy5Aw5vwifzLMESHN7vVX iSyr1GMkINVjb5gXVveArZQ//pnVkEK5pkpQtAvkTafdJXXrT7tvZ4Fe1zcLH32+4zEt Twp5ydVqqI70/y8wtpoeCe+a5brsDsPZkTpb6irQoK+Vyd/maQilXfVNZfBnSnPoKOiK fFzA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=LKqluvSgNgObFg/5PCh55olLBZ6qvjIouGnoyC1zOlQ=; b=ssCohOhl7TUTTwGHTd9hgOMti42PjqGR5RUstSHmgfkw38Hu3WjoizwsxYxH4OYTLU aDCZm+C2huideM/tQBpkcY/4UqysB+09AIZ6isQBwvrlRxTJ6jjW4/qYHap0d+KNuXF7 tPf++EzzNFl0BYdg5d0gKclgEE/xpGFiqbdW9Bp7CUw10kviWY1CDABNE9usQW5dPMbd AM0WgtVTqVureMKjjvpCFysaAsisG1jldrn5UGL8aYS7aAZJ7xm2Uyx0Vzox5fqboixk O/b2hSY6+AqYcTi4j7K2Gy74FGW7GrVN18ADAQ1Ib4OO+hYD37xf9zSa8hL1ArvsgnCo xqUA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=sw3c6Arf; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::b41 Subject: [Qemu-devel] [PULL 03/16] tcg: Add support for vector bitwise select X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This operation performs d = (b & a) | (c & ~a), and is present on a majority of host vector units. Include gvec expanders. Signed-off-by: Richard Henderson --- accel/tcg/tcg-runtime.h | 2 ++ tcg/aarch64/tcg-target.h | 1 + tcg/i386/tcg-target.h | 1 + tcg/tcg-op-gvec.h | 7 +++++++ tcg/tcg-op.h | 3 +++ tcg/tcg-opc.h | 2 ++ tcg/tcg.h | 1 + accel/tcg/tcg-runtime-gvec.c | 14 ++++++++++++++ tcg/tcg-op-gvec.c | 23 +++++++++++++++++++++++ tcg/tcg-op-vec.c | 26 ++++++++++++++++++++++++++ tcg/tcg.c | 2 ++ tcg/README | 4 ++++ 12 files changed, 86 insertions(+) -- 2.17.1 diff --git a/accel/tcg/tcg-runtime.h b/accel/tcg/tcg-runtime.h index 6d73dc2d65..4fa61b49b4 100644 --- a/accel/tcg/tcg-runtime.h +++ b/accel/tcg/tcg-runtime.h @@ -303,3 +303,5 @@ DEF_HELPER_FLAGS_4(gvec_leu8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_leu16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_leu32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_leu64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_5(gvec_bitsel, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index e43554c3c7..52ee66424f 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -140,6 +140,7 @@ typedef enum { #define TCG_TARGET_HAS_mul_vec 1 #define TCG_TARGET_HAS_sat_vec 1 #define TCG_TARGET_HAS_minmax_vec 1 +#define TCG_TARGET_HAS_bitsel_vec 0 #define TCG_TARGET_DEFAULT_MO (0) #define TCG_TARGET_HAS_MEMORY_BSWAP 1 diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 66f16fbe3c..08a0386433 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -190,6 +190,7 @@ extern bool have_avx2; #define TCG_TARGET_HAS_mul_vec 1 #define TCG_TARGET_HAS_sat_vec 1 #define TCG_TARGET_HAS_minmax_vec 1 +#define TCG_TARGET_HAS_bitsel_vec 0 #define TCG_TARGET_deposit_i32_valid(ofs, len) \ (((ofs) == 0 && (len) == 8) || ((ofs) == 8 && (len) == 8) || \ diff --git a/tcg/tcg-op-gvec.h b/tcg/tcg-op-gvec.h index 52a398c190..2a9e0c7c0a 100644 --- a/tcg/tcg-op-gvec.h +++ b/tcg/tcg-op-gvec.h @@ -342,6 +342,13 @@ void tcg_gen_gvec_cmp(TCGCond cond, unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz); +/* + * Perform vector bit select: d = (b & a) | (c & ~a). + */ +void tcg_gen_gvec_bitsel(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t cofs, + uint32_t oprsz, uint32_t maxsz); + /* * 64-bit vector operations. Use these when the register has been allocated * with tcg_global_mem_new_i64, and so we cannot also address it via pointer. diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index 660fe205d0..268860ed2f 100644 --- a/tcg/tcg-op.h +++ b/tcg/tcg-op.h @@ -1000,6 +1000,9 @@ void tcg_gen_sarv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); void tcg_gen_cmp_vec(TCGCond cond, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); +void tcg_gen_bitsel_vec(unsigned vece, TCGv_vec r, TCGv_vec a, + TCGv_vec b, TCGv_vec c); + void tcg_gen_ld_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset); void tcg_gen_st_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset); void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset, TCGType t); diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h index 4a2dd116eb..c05b71427c 100644 --- a/tcg/tcg-opc.h +++ b/tcg/tcg-opc.h @@ -256,6 +256,8 @@ DEF(sarv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shv_vec)) DEF(cmp_vec, 1, 2, 1, IMPLVEC) +DEF(bitsel_vec, 1, 3, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_bitsel_vec)) + DEF(last_generic, 0, 0, 0, TCG_OPF_NOT_PRESENT) #if TCG_TARGET_MAYBE_vec diff --git a/tcg/tcg.h b/tcg/tcg.h index 0e01a70d66..72f9f6c70b 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -187,6 +187,7 @@ typedef uint64_t TCGRegSet; #define TCG_TARGET_HAS_mul_vec 0 #define TCG_TARGET_HAS_sat_vec 0 #define TCG_TARGET_HAS_minmax_vec 0 +#define TCG_TARGET_HAS_bitsel_vec 0 #else #define TCG_TARGET_MAYBE_vec 1 #endif diff --git a/accel/tcg/tcg-runtime-gvec.c b/accel/tcg/tcg-runtime-gvec.c index 0f09e0ef38..3b6052fe97 100644 --- a/accel/tcg/tcg-runtime-gvec.c +++ b/accel/tcg/tcg-runtime-gvec.c @@ -1444,3 +1444,17 @@ void HELPER(gvec_umax64)(void *d, void *a, void *b, uint32_t desc) } clear_high(d, oprsz, desc); } + +void HELPER(gvec_bitsel)(void *d, void *a, void *b, void *c, uint32_t desc) +{ + intptr_t oprsz = simd_oprsz(desc); + intptr_t i; + + for (i = 0; i < oprsz; i += sizeof(vec64)) { + vec64 aa = *(vec64 *)(a + i); + vec64 bb = *(vec64 *)(b + i); + vec64 cc = *(vec64 *)(c + i); + *(vec64 *)(d + i) = (bb & aa) | (cc & ~aa); + } + clear_high(d, oprsz, desc); +} diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index bbf70e3cd9..f18464cf07 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -3195,3 +3195,26 @@ void tcg_gen_gvec_cmp(TCGCond cond, unsigned vece, uint32_t dofs, expand_clr(dofs + oprsz, maxsz - oprsz); } } + +static void tcg_gen_bitsel_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, TCGv_i64 c) +{ + TCGv_i64 t = tcg_temp_new_i64(); + + tcg_gen_and_i64(t, b, a); + tcg_gen_andc_i64(d, c, a); + tcg_gen_or_i64(d, d, t); + tcg_temp_free_i64(t); +} + +void tcg_gen_gvec_bitsel(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t cofs, + uint32_t oprsz, uint32_t maxsz) +{ + static const GVecGen4 g = { + .fni8 = tcg_gen_bitsel_i64, + .fniv = tcg_gen_bitsel_vec, + .fno = gen_helper_gvec_bitsel, + }; + + tcg_gen_gvec_4(dofs, aofs, bofs, cofs, oprsz, maxsz, &g); +} diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c index 543508d545..99cbf29e0b 100644 --- a/tcg/tcg-op-vec.c +++ b/tcg/tcg-op-vec.c @@ -88,6 +88,7 @@ bool tcg_can_emit_vecop_list(const TCGOpcode *list, case INDEX_op_dup2_vec: case INDEX_op_ld_vec: case INDEX_op_st_vec: + case INDEX_op_bitsel_vec: /* These opcodes are mandatory and should not be listed. */ g_assert_not_reached(); default: @@ -691,3 +692,28 @@ void tcg_gen_sars_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 b) { do_shifts(vece, r, a, b, INDEX_op_sars_vec, INDEX_op_sarv_vec); } + +void tcg_gen_bitsel_vec(unsigned vece, TCGv_vec r, TCGv_vec a, + TCGv_vec b, TCGv_vec c) +{ + TCGTemp *rt = tcgv_vec_temp(r); + TCGTemp *at = tcgv_vec_temp(a); + TCGTemp *bt = tcgv_vec_temp(b); + TCGTemp *ct = tcgv_vec_temp(c); + TCGType type = rt->base_type; + + tcg_debug_assert(at->base_type >= type); + tcg_debug_assert(bt->base_type >= type); + tcg_debug_assert(ct->base_type >= type); + + if (TCG_TARGET_HAS_bitsel_vec) { + vec_gen_4(INDEX_op_bitsel_vec, type, MO_8, + temp_arg(rt), temp_arg(at), temp_arg(bt), temp_arg(ct)); + } else { + TCGv_vec t = tcg_temp_new_vec(type); + tcg_gen_and_vec(MO_8, t, a, b); + tcg_gen_andc_vec(MO_8, r, c, a); + tcg_gen_or_vec(MO_8, r, r, t); + tcg_temp_free_vec(t); + } +} diff --git a/tcg/tcg.c b/tcg/tcg.c index 24083b8c00..5d947dbcb0 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1646,6 +1646,8 @@ bool tcg_op_supported(TCGOpcode op) case INDEX_op_smax_vec: case INDEX_op_umax_vec: return have_vec && TCG_TARGET_HAS_minmax_vec; + case INDEX_op_bitsel_vec: + return have_vec && TCG_TARGET_HAS_bitsel_vec; default: tcg_debug_assert(op > INDEX_op_last_generic && op < NB_OPS); diff --git a/tcg/README b/tcg/README index cbdfd3b6bc..76057ab59f 100644 --- a/tcg/README +++ b/tcg/README @@ -627,6 +627,10 @@ E.g. VECL=1 -> 64 << 1 -> v128, and VECE=2 -> 1 << 2 -> i32. Compare vectors by element, storing -1 for true and 0 for false. +* bitsel_vec v0, v1, v2, v3 + + Bitwise select, v0 = (v2 & v1) | (v3 & ~v1), across the entire vector. + ********* Note 1: Some shortcuts are defined when the last operand is known to be From patchwork Wed May 22 22:28:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 164905 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp1413528ili; Wed, 22 May 2019 15:31:52 -0700 (PDT) X-Google-Smtp-Source: APXvYqy7W9cqy5O2DSd14Wda5ICGoHtaShQXGkApKI/YArqe0Y8ZPectn5p641CymrcEb0AolYwq X-Received: by 2002:a50:9177:: with SMTP id f52mr93811572eda.18.1558564312424; Wed, 22 May 2019 15:31:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1558564312; cv=none; d=google.com; s=arc-20160816; b=n1tRIU9oAIHZdSUlCDkodaIuuv2JcYhEYZgLJ8BtZ+Q0gJ37IZCurAp3nTgy1ZAg2k 1wgNh5h1Ijq9WEpE5ugGupNXPcFkX1T8zfZq1BAsRjQr3fXWn3nriEzDKNevTxLIylbj aPWRh6QAaK8QOoFDpZ48RDGMy1DCNmed0EAk/LLfdrTo0xZmaCuxG3l8ggGC4Tr3Ddcf OfL9C64RzOdzMPJHJGpEslkQ17k/3IJF40LBHDuC3wmC2lAfVUghQoYljndwy3uZKklf chy/AupI487SEIWwL/rmVZdr8nOpkJtSEbkRvhTqORJTyf6FlKmUPoyS7GFAw3ZO0V6f 82qQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=dIrUBx1AozwSRTf1CstcHoUDbRuw3JV0rC9AxpXdw/A=; b=pOObFbAGeUnPGSHJTbapy54Xv36jPyqoyf2YGIlLWvNnWAYzVKtbOFfugwV57xvUlh 1qPUcYiLLd7233jJeL3BOeVWcZFrr9c73vMLYerirjn6dvk+BWOygcse6qIzFwvMewRQ FCWAd2/m7thqaAzPpjhuLwBpn6WY2039Z48GMmx9ErxdM+dDtxe4cuJgt+u9eUXPjaUG DbK8gAlByTls2RcPK797u8hv1k6a38hC8HdGokF7J6utyfSADgI1MXvTbUSPfbgH+qiL ghEcCl4d5PN3U1wlXn+3vHR2V9WSz5j1mGw3cfJJ0WEL/+7v8csDWTobxfKhOI9Hakro 3s4g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=IYPob7b0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::c44 Subject: [Qemu-devel] [PULL 04/16] tcg: Add support for vector compare select X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Perform a per-element conditional move. This combination operation is easier to implement on some host vector units than plain cmp+bitsel. Omit the usual gvec interface, as this is intended to be used by target-specific gvec expansion call-backs. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.h | 1 + tcg/i386/tcg-target.h | 1 + tcg/tcg-op.h | 2 ++ tcg/tcg-opc.h | 1 + tcg/tcg.h | 1 + tcg/tcg-op-vec.c | 59 ++++++++++++++++++++++++++++++++++++++++ tcg/tcg.c | 3 ++ tcg/README | 7 +++++ 8 files changed, 75 insertions(+) -- 2.17.1 diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 52ee66424f..b4a9d36bbc 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -141,6 +141,7 @@ typedef enum { #define TCG_TARGET_HAS_sat_vec 1 #define TCG_TARGET_HAS_minmax_vec 1 #define TCG_TARGET_HAS_bitsel_vec 0 +#define TCG_TARGET_HAS_cmpsel_vec 0 #define TCG_TARGET_DEFAULT_MO (0) #define TCG_TARGET_HAS_MEMORY_BSWAP 1 diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 08a0386433..16a83a7f7b 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -191,6 +191,7 @@ extern bool have_avx2; #define TCG_TARGET_HAS_sat_vec 1 #define TCG_TARGET_HAS_minmax_vec 1 #define TCG_TARGET_HAS_bitsel_vec 0 +#define TCG_TARGET_HAS_cmpsel_vec 0 #define TCG_TARGET_deposit_i32_valid(ofs, len) \ (((ofs) == 0 && (len) == 8) || ((ofs) == 8 && (len) == 8) || \ diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index 268860ed2f..2d4dd5cd7d 100644 --- a/tcg/tcg-op.h +++ b/tcg/tcg-op.h @@ -1002,6 +1002,8 @@ void tcg_gen_cmp_vec(TCGCond cond, unsigned vece, TCGv_vec r, void tcg_gen_bitsel_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b, TCGv_vec c); +void tcg_gen_cmpsel_vec(TCGCond cond, unsigned vece, TCGv_vec r, + TCGv_vec a, TCGv_vec b, TCGv_vec c, TCGv_vec d); void tcg_gen_ld_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset); void tcg_gen_st_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset); diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h index c05b71427c..c7d971fa3d 100644 --- a/tcg/tcg-opc.h +++ b/tcg/tcg-opc.h @@ -257,6 +257,7 @@ DEF(sarv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shv_vec)) DEF(cmp_vec, 1, 2, 1, IMPLVEC) DEF(bitsel_vec, 1, 3, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_bitsel_vec)) +DEF(cmpsel_vec, 1, 4, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_cmpsel_vec)) DEF(last_generic, 0, 0, 0, TCG_OPF_NOT_PRESENT) diff --git a/tcg/tcg.h b/tcg/tcg.h index 72f9f6c70b..21cd6f1249 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -188,6 +188,7 @@ typedef uint64_t TCGRegSet; #define TCG_TARGET_HAS_sat_vec 0 #define TCG_TARGET_HAS_minmax_vec 0 #define TCG_TARGET_HAS_bitsel_vec 0 +#define TCG_TARGET_HAS_cmpsel_vec 0 #else #define TCG_TARGET_MAYBE_vec 1 #endif diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c index 99cbf29e0b..a888c02df8 100644 --- a/tcg/tcg-op-vec.c +++ b/tcg/tcg-op-vec.c @@ -119,6 +119,11 @@ bool tcg_can_emit_vecop_list(const TCGOpcode *list, continue; } break; + case INDEX_op_cmpsel_vec: + if (tcg_can_emit_vec_op(INDEX_op_cmp_vec, type, vece)) { + continue; + } + break; default: break; } @@ -159,6 +164,20 @@ void vec_gen_4(TCGOpcode opc, TCGType type, unsigned vece, op->args[3] = c; } +static void vec_gen_6(TCGOpcode opc, TCGType type, unsigned vece, TCGArg r, + TCGArg a, TCGArg b, TCGArg c, TCGArg d, TCGArg e) +{ + TCGOp *op = tcg_emit_op(opc); + TCGOP_VECL(op) = type - TCG_TYPE_V64; + TCGOP_VECE(op) = vece; + op->args[0] = r; + op->args[1] = a; + op->args[2] = b; + op->args[3] = c; + op->args[4] = d; + op->args[5] = e; +} + static void vec_gen_op2(TCGOpcode opc, unsigned vece, TCGv_vec r, TCGv_vec a) { TCGTemp *rt = tcgv_vec_temp(r); @@ -717,3 +736,43 @@ void tcg_gen_bitsel_vec(unsigned vece, TCGv_vec r, TCGv_vec a, tcg_temp_free_vec(t); } } + +void tcg_gen_cmpsel_vec(TCGCond cond, unsigned vece, TCGv_vec r, + TCGv_vec a, TCGv_vec b, TCGv_vec c, TCGv_vec d) +{ + TCGTemp *rt = tcgv_vec_temp(r); + TCGTemp *at = tcgv_vec_temp(a); + TCGTemp *bt = tcgv_vec_temp(b); + TCGTemp *ct = tcgv_vec_temp(c); + TCGTemp *dt = tcgv_vec_temp(d); + TCGArg ri = temp_arg(rt); + TCGArg ai = temp_arg(at); + TCGArg bi = temp_arg(bt); + TCGArg ci = temp_arg(ct); + TCGArg di = temp_arg(dt); + TCGType type = rt->base_type; + const TCGOpcode *hold_list; + int can; + + tcg_debug_assert(at->base_type >= type); + tcg_debug_assert(bt->base_type >= type); + tcg_debug_assert(ct->base_type >= type); + tcg_debug_assert(dt->base_type >= type); + + tcg_assert_listed_vecop(INDEX_op_cmpsel_vec); + hold_list = tcg_swap_vecop_list(NULL); + can = tcg_can_emit_vec_op(INDEX_op_cmpsel_vec, type, vece); + + if (can > 0) { + vec_gen_6(INDEX_op_cmpsel_vec, type, vece, ri, ai, bi, ci, di, cond); + } else if (can < 0) { + tcg_expand_vec_op(INDEX_op_cmpsel_vec, type, vece, + ri, ai, bi, ci, di, cond); + } else { + TCGv_vec t = tcg_temp_new_vec(type); + tcg_gen_cmp_vec(cond, vece, t, a, b); + tcg_gen_bitsel_vec(vece, r, t, c, d); + tcg_temp_free_vec(t); + } + tcg_swap_vecop_list(hold_list); +} diff --git a/tcg/tcg.c b/tcg/tcg.c index 5d947dbcb0..02a2680169 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1648,6 +1648,8 @@ bool tcg_op_supported(TCGOpcode op) return have_vec && TCG_TARGET_HAS_minmax_vec; case INDEX_op_bitsel_vec: return have_vec && TCG_TARGET_HAS_bitsel_vec; + case INDEX_op_cmpsel_vec: + return have_vec && TCG_TARGET_HAS_cmpsel_vec; default: tcg_debug_assert(op > INDEX_op_last_generic && op < NB_OPS); @@ -2028,6 +2030,7 @@ static void tcg_dump_ops(TCGContext *s, bool have_prefs) case INDEX_op_setcond_i64: case INDEX_op_movcond_i64: case INDEX_op_cmp_vec: + case INDEX_op_cmpsel_vec: if (op->args[k] < ARRAY_SIZE(cond_name) && cond_name[op->args[k]]) { col += qemu_log(",%s", cond_name[op->args[k++]]); diff --git a/tcg/README b/tcg/README index 76057ab59f..21fcdf737f 100644 --- a/tcg/README +++ b/tcg/README @@ -631,6 +631,13 @@ E.g. VECL=1 -> 64 << 1 -> v128, and VECE=2 -> 1 << 2 -> i32. Bitwise select, v0 = (v2 & v1) | (v3 & ~v1), across the entire vector. +* cmpsel_vec v0, c1, c2, v3, v4, cond + + Select elements based on comparison results: + for (i = 0; i < n; ++i) { + v0[i] = (c1[i] cond c2[i]) ? v3[i] : v4[i]. + } + ********* Note 1: Some shortcuts are defined when the last operand is known to be From patchwork Wed May 22 22:28:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 164907 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp1413686ili; Wed, 22 May 2019 15:32:04 -0700 (PDT) X-Google-Smtp-Source: APXvYqyDsusMonLfl8wwTFvU6wvdUtSoPONoP6oKK8ZJTdShPBIH4vN1ieeh/IP8usGY2ZaKlVvH X-Received: by 2002:a17:906:2498:: with SMTP id e24mr3403583ejb.42.1558564323958; Wed, 22 May 2019 15:32:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1558564323; cv=none; d=google.com; s=arc-20160816; b=FGC9TPOBcc4hzNpGDIbmGIeRmO748C+Ozu3zqu2zzfXgniCu1vR1gpunBkan5HPqgA oeihMkLcGjya8poApaLOzGTZYueWOSy1LkwlK/Dt5xgP54znycBu1jLS7FfXkDZUGhPn UAKlPobqz1evKKblj0z+bS9KopWG1kOuV8DJKmRclK1rgs4uGccUWr5Yyq3KozkPgNOr bJy/KFGeDUkhQaJxKwepDt+JN3B4wp9WMdn+6am+ssoul4ORZQFli9iA3NHKmv8w+G9l 6tEWwa86ahJz+BM3BpFW9ht8CrMAMf5HoKCBVeTyp1Jr4baHrWKZQTn8YuGf4X+ZgDyZ AWGQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=IHzD/cFhgds3vlWGOoqI0eCnewZUJpWI1Gh0PD14SRs=; b=Yu3BMk+UfFRVj2llvOF3HydqqR6ROPp8eZrESOzy6SDe3SYjhFLyRN5HMcFInoQzY8 tDMqXZ9fDNAThx7imraFJj0Kumj265swSNS08CvkO1/PB0oms27yCmShOLmtP1+FDjgy dgZfCXLPfbFpc5/wYj5RuXF2C0YvLT/37BY5mbjo/22Qp8Sho/PxWLNEODmg7a8oHkiM 7tcwMAFu6/pkCpG3lodEBr0WukRv3XyYqelglCytnnR305aaySN+KnZMxh46d/7AwiuN Bt94O8N5MlVKUl+RwWqPENf7+3FcVObqmWO3bEGwC741nwT0H4RnYwZT/uuweOB1xAqN hapw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=r3PiTJIY; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::b2b Subject: [Qemu-devel] [PULL 05/16] tcg: Introduce do_op3_nofail for vector expansion X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This makes do_op3 match do_op2 in allowing for failure, and thus fall back expansions. Signed-off-by: Richard Henderson --- tcg/tcg-op-vec.c | 45 +++++++++++++++++++++++++++------------------ 1 file changed, 27 insertions(+), 18 deletions(-) -- 2.17.1 diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c index a888c02df8..004a34935b 100644 --- a/tcg/tcg-op-vec.c +++ b/tcg/tcg-op-vec.c @@ -562,7 +562,7 @@ void tcg_gen_cmp_vec(TCGCond cond, unsigned vece, } } -static void do_op3(unsigned vece, TCGv_vec r, TCGv_vec a, +static bool do_op3(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b, TCGOpcode opc) { TCGTemp *rt = tcgv_vec_temp(r); @@ -580,82 +580,91 @@ static void do_op3(unsigned vece, TCGv_vec r, TCGv_vec a, can = tcg_can_emit_vec_op(opc, type, vece); if (can > 0) { vec_gen_3(opc, type, vece, ri, ai, bi); - } else { + } else if (can < 0) { const TCGOpcode *hold_list = tcg_swap_vecop_list(NULL); - tcg_debug_assert(can < 0); tcg_expand_vec_op(opc, type, vece, ri, ai, bi); tcg_swap_vecop_list(hold_list); + } else { + return false; } + return true; +} + +static void do_op3_nofail(unsigned vece, TCGv_vec r, TCGv_vec a, + TCGv_vec b, TCGOpcode opc) +{ + bool ok = do_op3(vece, r, a, b, opc); + tcg_debug_assert(ok); } void tcg_gen_add_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) { - do_op3(vece, r, a, b, INDEX_op_add_vec); + do_op3_nofail(vece, r, a, b, INDEX_op_add_vec); } void tcg_gen_sub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) { - do_op3(vece, r, a, b, INDEX_op_sub_vec); + do_op3_nofail(vece, r, a, b, INDEX_op_sub_vec); } void tcg_gen_mul_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) { - do_op3(vece, r, a, b, INDEX_op_mul_vec); + do_op3_nofail(vece, r, a, b, INDEX_op_mul_vec); } void tcg_gen_ssadd_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) { - do_op3(vece, r, a, b, INDEX_op_ssadd_vec); + do_op3_nofail(vece, r, a, b, INDEX_op_ssadd_vec); } void tcg_gen_usadd_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) { - do_op3(vece, r, a, b, INDEX_op_usadd_vec); + do_op3_nofail(vece, r, a, b, INDEX_op_usadd_vec); } void tcg_gen_sssub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) { - do_op3(vece, r, a, b, INDEX_op_sssub_vec); + do_op3_nofail(vece, r, a, b, INDEX_op_sssub_vec); } void tcg_gen_ussub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) { - do_op3(vece, r, a, b, INDEX_op_ussub_vec); + do_op3_nofail(vece, r, a, b, INDEX_op_ussub_vec); } void tcg_gen_smin_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) { - do_op3(vece, r, a, b, INDEX_op_smin_vec); + do_op3_nofail(vece, r, a, b, INDEX_op_smin_vec); } void tcg_gen_umin_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) { - do_op3(vece, r, a, b, INDEX_op_umin_vec); + do_op3_nofail(vece, r, a, b, INDEX_op_umin_vec); } void tcg_gen_smax_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) { - do_op3(vece, r, a, b, INDEX_op_smax_vec); + do_op3_nofail(vece, r, a, b, INDEX_op_smax_vec); } void tcg_gen_umax_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) { - do_op3(vece, r, a, b, INDEX_op_umax_vec); + do_op3_nofail(vece, r, a, b, INDEX_op_umax_vec); } void tcg_gen_shlv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) { - do_op3(vece, r, a, b, INDEX_op_shlv_vec); + do_op3_nofail(vece, r, a, b, INDEX_op_shlv_vec); } void tcg_gen_shrv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) { - do_op3(vece, r, a, b, INDEX_op_shrv_vec); + do_op3_nofail(vece, r, a, b, INDEX_op_shrv_vec); } void tcg_gen_sarv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) { - do_op3(vece, r, a, b, INDEX_op_sarv_vec); + do_op3_nofail(vece, r, a, b, INDEX_op_sarv_vec); } static void do_shifts(unsigned vece, TCGv_vec r, TCGv_vec a, @@ -691,7 +700,7 @@ static void do_shifts(unsigned vece, TCGv_vec r, TCGv_vec a, } else { tcg_gen_dup_i32_vec(vece, vec_s, s); } - do_op3(vece, r, a, vec_s, opc_v); + do_op3_nofail(vece, r, a, vec_s, opc_v); tcg_temp_free_vec(vec_s); } tcg_swap_vecop_list(hold_list); From patchwork Wed May 22 22:28:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 164902 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp1411124ili; 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X-Received-From: 2607:f8b0:4864:20::b43 Subject: [Qemu-devel] [PULL 06/16] tcg: Expand vector minmax using cmp+cmpsel X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Provide a generic fallback for the min/max operations. Signed-off-by: Richard Henderson --- tcg/tcg-op-vec.c | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) -- 2.17.1 diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c index 004a34935b..501d9630a2 100644 --- a/tcg/tcg-op-vec.c +++ b/tcg/tcg-op-vec.c @@ -120,6 +120,10 @@ bool tcg_can_emit_vecop_list(const TCGOpcode *list, } break; case INDEX_op_cmpsel_vec: + case INDEX_op_smin_vec: + case INDEX_op_smax_vec: + case INDEX_op_umin_vec: + case INDEX_op_umax_vec: if (tcg_can_emit_vec_op(INDEX_op_cmp_vec, type, vece)) { continue; } @@ -632,24 +636,32 @@ void tcg_gen_ussub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) do_op3_nofail(vece, r, a, b, INDEX_op_ussub_vec); } +static void do_minmax(unsigned vece, TCGv_vec r, TCGv_vec a, + TCGv_vec b, TCGOpcode opc, TCGCond cond) +{ + if (!do_op3(vece, r, a, b, opc)) { + tcg_gen_cmpsel_vec(cond, vece, r, a, b, a, b); + } +} + void tcg_gen_smin_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) { - do_op3_nofail(vece, r, a, b, INDEX_op_smin_vec); + do_minmax(vece, r, a, b, INDEX_op_smin_vec, TCG_COND_LT); } void tcg_gen_umin_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) { - do_op3_nofail(vece, r, a, b, INDEX_op_umin_vec); + do_minmax(vece, r, a, b, INDEX_op_umin_vec, TCG_COND_LTU); } void tcg_gen_smax_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) { - do_op3_nofail(vece, r, a, b, INDEX_op_smax_vec); + do_minmax(vece, r, a, b, INDEX_op_smax_vec, TCG_COND_GT); } void tcg_gen_umax_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) { - do_op3_nofail(vece, r, a, b, INDEX_op_umax_vec); + do_minmax(vece, r, a, b, INDEX_op_umax_vec, TCG_COND_GTU); } void tcg_gen_shlv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) From patchwork Wed May 22 22:28:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 164909 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp1417144ili; Wed, 22 May 2019 15:36:21 -0700 (PDT) X-Google-Smtp-Source: APXvYqwKc1zGLITLb127VyU8WmWL20n+H89Qot93CoM4XEz6N5fJhqGr7zwsslGJdoF0JuDkj6mB X-Received: by 2002:a50:974d:: with SMTP id d13mr94000857edb.209.1558564581259; Wed, 22 May 2019 15:36:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1558564581; cv=none; d=google.com; s=arc-20160816; b=aUJkBMxeDNXqwU+QROQtMqFZxYyL5663BOCN8pnJ+V19CdXffY32aKwgNT504XQmQ2 OazTJikGd1yDXYA9XCPzf9MRcO1BhNdJmNxityh/HrehRovHOCEAfDym0eSeM6+dP6xh B4lJait9PvKtLK+2XHflAIypCypl81241zZPpsobxO2XxfbeVku/UACIGfhRb9FDGHEm V9UsalBKbcpuqdXE1xHvr5KjU7gtIVzpSR0EBEpBYSBnKGdhrkh1HmJF/YAXlaNQR1ts lfm9gY5AozdKGBhnn9Cqh8FNXCON40Rg3JmRtzhzB00EG8ETP3nyKQRIMYNd/Ra2m16u bplw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=h2THfX9yFXUdDN24lXnYzdU4v3sPNpuvs1LZ+ysU720=; b=RpH8aUjw1/kTSNbMF1Zc7sTYwvortGNHNZkZluo0P4JlY1V8zGY54yDOh6c/oChS4A WsRDlVUsGBAfb/qXSTPbbFBIKx4PJ18Pxj1A70F5coCHEvriYPMC/YagWypCZq4PziC5 mNTLOEX0LvU5oUEn7BvkqOvZQmk8AACS9DpoG7S/M7d7uPaVOe4ThN21fIpAjUq2FmGl IxF4fOMZ0lB2YgNH/W1OteVD6P/OQUMDd7v6bS3edAjMEEHrcBn7OSHxFfWVBBzgeMF1 HYrnJWBvXMlD0OLjSz40g5TxNKSmNy7rpZupuToFuv+1TKaBLPx+Zp3llOn7yPOV6kYi cEUw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=kloKS3sr; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::b29 Subject: [Qemu-devel] [PULL 07/16] tcg: Add TCG_OPF_NOT_PRESENT if TCG_TARGET_HAS_foo is negative X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" If INDEX_op_foo is always expanded by tcg_expand_vec_op, then there may be no reasonable set of constraints to return from tcg_target_op_def for that opcode. Let TCG_TARGET_HAS_foo be specified as -1 in that case. Thus a boolean test for TCG_TARGET_HAS_foo is true, but we will not assert within process_op_defs when no constraints are specified. Compare this with tcg_can_emit_vec_op, which already uses this tri-state indication. Signed-off-by: Richard Henderson --- tcg/tcg-opc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.17.1 diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h index c7d971fa3d..242d608e6d 100644 --- a/tcg/tcg-opc.h +++ b/tcg/tcg-opc.h @@ -35,7 +35,7 @@ DEF(call, 0, 0, 3, TCG_OPF_CALL_CLOBBER | TCG_OPF_NOT_PRESENT) DEF(br, 0, 0, 1, TCG_OPF_BB_END) -#define IMPL(X) (__builtin_constant_p(X) && !(X) ? TCG_OPF_NOT_PRESENT : 0) +#define IMPL(X) (__builtin_constant_p(X) && (X) <= 0 ? TCG_OPF_NOT_PRESENT : 0) #if TCG_TARGET_REG_BITS == 32 # define IMPL64 TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT #else From patchwork Wed May 22 22:28:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 164911 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp1418069ili; Wed, 22 May 2019 15:37:40 -0700 (PDT) X-Google-Smtp-Source: APXvYqyLDCRdwP7XZDT6ON0byr/YlWu2QV2NAUsWYvQ1eWWahAYrbbVb092SvDk0x+AvSe9t8BJG X-Received: by 2002:a50:b4b8:: with SMTP id w53mr93142451edd.255.1558564660630; Wed, 22 May 2019 15:37:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1558564660; cv=none; d=google.com; s=arc-20160816; b=KzJONNysu4aPmL6iRs1v1jDhlrHUfrDjgcbnP66qz9CRt0ku1sqb5vWcbdlxWMxsTv PMi1DX9ZAup3N9fQOS6P+9tB7sIDVQFpDNBhQ+o81wvKjteWYfvMCRaTLmFzsl5DKxZ+ 87R+BfTSq+hITg5j33qvm6D/pjKvX5ZSIOXHokPO+HuX9khlFpeSTi0DZQgyWuCly5M7 VdIgCFUno/dEbwxSHfliIQ2czVu6EKUhJts+Ucqk1k0g7EpbZJDFHZO0iuDEAJL9w3KP JcXlStOCFSUr2Nul7ywORRo+HCHil5THYo6lLr9/8eg6xyw5xf4h4fjByAMbbXoISKFQ VPhA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=oLTml3dhbqYDrgc3cYARBzaQje8i0Sq1y8nx8+B4Ie0=; b=YSuHNqNzgkhq8S/SORZ+A6QBWZIj27HW5BjBS5LKoJmjxntVrH/DCU7iJizdF2s/1L RNm7IW9qOUCGY0eU0YVfqQmJdKdtWFqFxB6yXV9plu/eHu16NBDUYs9GnMaYpzPq7pbT 1He7nidFaKqiDpM54uc0BhK0mTGjBrxWZDPYvCbC9fsICEXSVZ2ehoNG2WYhLE/9s6LG TKnSFsWFje8jJaWIS8gKHwb+jYUTXN2E1r5Yyo4PKNS7cptcdv3LHKxqKtXpEroUcep2 xOSkiqVdY8RujRhtCJMo1a1SeAdh8RmlbgWAmlWnstf6zAMPl//YgshjPXEv20AxJQF2 Vshw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=pTPteNdO; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::b29 Subject: [Qemu-devel] [PULL 08/16] tcg/i386: Support vector comparison select value X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We already had backend support for this feature. Expand the new cmpsel opcode using vpblendb. The combination allows us to avoid an extra NOT for some comparison codes. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.h | 2 +- tcg/i386/tcg-target.inc.c | 39 +++++++++++++++++++++++++++++++++++---- 2 files changed, 36 insertions(+), 5 deletions(-) -- 2.17.1 diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 16a83a7f7b..928e8b87bb 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -191,7 +191,7 @@ extern bool have_avx2; #define TCG_TARGET_HAS_sat_vec 1 #define TCG_TARGET_HAS_minmax_vec 1 #define TCG_TARGET_HAS_bitsel_vec 0 -#define TCG_TARGET_HAS_cmpsel_vec 0 +#define TCG_TARGET_HAS_cmpsel_vec -1 #define TCG_TARGET_deposit_i32_valid(ofs, len) \ (((ofs) == 0 && (len) == 8) || ((ofs) == 8 && (len) == 8) || \ diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index b3601446cd..ffcafb1e14 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -3246,6 +3246,7 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) case INDEX_op_andc_vec: return 1; case INDEX_op_cmp_vec: + case INDEX_op_cmpsel_vec: return -1; case INDEX_op_shli_vec: @@ -3464,8 +3465,8 @@ static void expand_vec_mul(TCGType type, unsigned vece, } } -static void expand_vec_cmp(TCGType type, unsigned vece, TCGv_vec v0, - TCGv_vec v1, TCGv_vec v2, TCGCond cond) +static bool expand_vec_cmp_noinv(TCGType type, unsigned vece, TCGv_vec v0, + TCGv_vec v1, TCGv_vec v2, TCGCond cond) { enum { NEED_SWAP = 1, @@ -3522,11 +3523,34 @@ static void expand_vec_cmp(TCGType type, unsigned vece, TCGv_vec v0, tcg_temp_free_vec(t2); } } - if (fixup & NEED_INV) { + return fixup & NEED_INV; +} + +static void expand_vec_cmp(TCGType type, unsigned vece, TCGv_vec v0, + TCGv_vec v1, TCGv_vec v2, TCGCond cond) +{ + if (expand_vec_cmp_noinv(type, vece, v0, v1, v2, cond)) { tcg_gen_not_vec(vece, v0, v0); } } +static void expand_vec_cmpsel(TCGType type, unsigned vece, TCGv_vec v0, + TCGv_vec c1, TCGv_vec c2, + TCGv_vec v3, TCGv_vec v4, TCGCond cond) +{ + TCGv_vec t = tcg_temp_new_vec(type); + + if (expand_vec_cmp_noinv(type, vece, t, c1, c2, cond)) { + /* Invert the sense of the compare by swapping arguments. */ + TCGv_vec x; + x = v3, v3 = v4, v4 = x; + } + vec_gen_4(INDEX_op_x86_vpblendvb_vec, type, vece, + tcgv_vec_arg(v0), tcgv_vec_arg(v4), + tcgv_vec_arg(v3), tcgv_vec_arg(t)); + tcg_temp_free_vec(t); +} + static void expand_vec_minmax(TCGType type, unsigned vece, TCGCond cond, bool min, TCGv_vec v0, TCGv_vec v1, TCGv_vec v2) @@ -3551,7 +3575,7 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, { va_list va; TCGArg a2; - TCGv_vec v0, v1, v2; + TCGv_vec v0, v1, v2, v3, v4; va_start(va, a0); v0 = temp_tcgv_vec(arg_temp(a0)); @@ -3578,6 +3602,13 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, expand_vec_cmp(type, vece, v0, v1, v2, va_arg(va, TCGArg)); break; + case INDEX_op_cmpsel_vec: + v2 = temp_tcgv_vec(arg_temp(a2)); + v3 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); + v4 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); + expand_vec_cmpsel(type, vece, v0, v1, v2, v3, v4, va_arg(va, TCGArg)); + break; + case INDEX_op_smin_vec: v2 = temp_tcgv_vec(arg_temp(a2)); expand_vec_minmax(type, vece, TCG_COND_GT, true, v0, v1, v2); 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X-Received-From: 2607:f8b0:4864:20::b31 Subject: [Qemu-devel] [PULL 09/16] tcg/i386: Remove expansion for missing minmax X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is now handled by code within tcg-op-vec.c. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.inc.c | 37 ------------------------------------- 1 file changed, 37 deletions(-) -- 2.17.1 diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index ffcafb1e14..569a2c2120 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -3297,7 +3297,6 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) case INDEX_op_smax_vec: case INDEX_op_umin_vec: case INDEX_op_umax_vec: - return vece <= MO_32 ? 1 : -1; case INDEX_op_abs_vec: return vece <= MO_32; @@ -3551,25 +3550,6 @@ static void expand_vec_cmpsel(TCGType type, unsigned vece, TCGv_vec v0, tcg_temp_free_vec(t); } -static void expand_vec_minmax(TCGType type, unsigned vece, - TCGCond cond, bool min, - TCGv_vec v0, TCGv_vec v1, TCGv_vec v2) -{ - TCGv_vec t1 = tcg_temp_new_vec(type); - - tcg_debug_assert(vece == MO_64); - - tcg_gen_cmp_vec(cond, vece, t1, v1, v2); - if (min) { - TCGv_vec t2; - t2 = v1, v1 = v2, v2 = t2; - } - vec_gen_4(INDEX_op_x86_vpblendvb_vec, type, vece, - tcgv_vec_arg(v0), tcgv_vec_arg(v1), - tcgv_vec_arg(v2), tcgv_vec_arg(t1)); - tcg_temp_free_vec(t1); -} - void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, TCGArg a0, ...) { @@ -3609,23 +3589,6 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, expand_vec_cmpsel(type, vece, v0, v1, v2, v3, v4, va_arg(va, TCGArg)); break; - case INDEX_op_smin_vec: - v2 = temp_tcgv_vec(arg_temp(a2)); - expand_vec_minmax(type, vece, TCG_COND_GT, true, v0, v1, v2); - break; - case INDEX_op_smax_vec: - v2 = temp_tcgv_vec(arg_temp(a2)); - expand_vec_minmax(type, vece, TCG_COND_GT, false, v0, v1, v2); - break; - case INDEX_op_umin_vec: - v2 = temp_tcgv_vec(arg_temp(a2)); - expand_vec_minmax(type, vece, TCG_COND_GTU, true, v0, v1, v2); - break; - case INDEX_op_umax_vec: - v2 = temp_tcgv_vec(arg_temp(a2)); - expand_vec_minmax(type, vece, TCG_COND_GTU, false, v0, v1, v2); - break; - default: break; } From patchwork Wed May 22 22:28:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 164912 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp1418189ili; Wed, 22 May 2019 15:37:53 -0700 (PDT) X-Google-Smtp-Source: APXvYqz/OG6/oyxkTboTRkRqWbuHnvoY4Tw6Fka3NoTiw2gGXmuBqrYmDltQzluAG5RU06YqUkuf X-Received: by 2002:a17:906:4dc7:: with SMTP id f7mr66035178ejw.207.1558564673822; Wed, 22 May 2019 15:37:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1558564673; cv=none; d=google.com; s=arc-20160816; b=kwaYHlaIXwxwTjn1yn7ZWAt/E8A8w2fqbc6USFU+enSt+HG96XGuwimsW1EYPphAnM R39nzI9Slfu1Xcxr9s//f5LqWpE/jAUnkHMtlrFubAa5ZaB1i+J5kVxroxDO5wSL6rq1 oJpfbdS7WN9khuwpVoKFMrCimgr/1m0PR7SgYouGaq91ZUERL+3Gl+Mle3UKebTeLCW2 bztNbbS/Ca4W4jryB5LeD88ng1dt/RUYz8AzkOuBEHkSddcUMEa5UoOLwPnVQR/pkLj0 wyQA4tYgUrjWFmRSU3ilystKtwqsvgUV9XfXN7K/+qTod768RZt3T7k7A/3eYF5ISdXO rMVg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=OLftcOa71o3SDWkHEvzuYmmBM81jvFAhtQKjy7MXc3g=; b=RWrOjRcwezV9JlEYp1wE511D+emA4rTkdI72o1fcjrDD9dEbj95zt6t671sVnsWAG7 yXdFAh2kYCV+PBlxj4ZUBNHBvTQlpJNTQoTPXjkAuoxPdV9W80hioXhtXelk/9AiI1Dx srvqEihvmSBRGmrMPMqZ0197UShjIa3Aq4ybeSCKedG+nnVyJO6R9YN/NWwaZaR3viUs mQ5hFRGbbl9PG5YlJqzn+O5veASEw/ojKfj7BSCkGqqbbsAHVx9+jjV52iiRd7Tg0kda FKwXQql4XMKbtxTCB0bsYUv9vOLzuKUWRsCfey7ESb6PPfV68433dUP27Zwx6jHN5Tlm xIdw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=uUBBJxmv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::c43 Subject: [Qemu-devel] [PULL 10/16] tcg/i386: Use umin/umax in expanding unsigned compare X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Using umin(a, b) == a as an expansion for TCG_COND_LEU is a better alternative to (a - INT_MIN) <= (b - INT_MIN). Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.inc.c | 80 +++++++++++++++++++++++++++++---------- 1 file changed, 61 insertions(+), 19 deletions(-) -- 2.17.1 diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 569a2c2120..6ec5e60448 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -3468,28 +3468,61 @@ static bool expand_vec_cmp_noinv(TCGType type, unsigned vece, TCGv_vec v0, TCGv_vec v1, TCGv_vec v2, TCGCond cond) { enum { - NEED_SWAP = 1, - NEED_INV = 2, - NEED_BIAS = 4 - }; - static const uint8_t fixups[16] = { - [0 ... 15] = -1, - [TCG_COND_EQ] = 0, - [TCG_COND_NE] = NEED_INV, - [TCG_COND_GT] = 0, - [TCG_COND_LT] = NEED_SWAP, - [TCG_COND_LE] = NEED_INV, - [TCG_COND_GE] = NEED_SWAP | NEED_INV, - [TCG_COND_GTU] = NEED_BIAS, - [TCG_COND_LTU] = NEED_BIAS | NEED_SWAP, - [TCG_COND_LEU] = NEED_BIAS | NEED_INV, - [TCG_COND_GEU] = NEED_BIAS | NEED_SWAP | NEED_INV, + NEED_INV = 1, + NEED_SWAP = 2, + NEED_BIAS = 4, + NEED_UMIN = 8, + NEED_UMAX = 16, }; TCGv_vec t1, t2; uint8_t fixup; - fixup = fixups[cond & 15]; - tcg_debug_assert(fixup != 0xff); + switch (cond) { + case TCG_COND_EQ: + case TCG_COND_GT: + fixup = 0; + break; + case TCG_COND_NE: + case TCG_COND_LE: + fixup = NEED_INV; + break; + case TCG_COND_LT: + fixup = NEED_SWAP; + break; + case TCG_COND_GE: + fixup = NEED_SWAP | NEED_INV; + break; + case TCG_COND_LEU: + if (vece <= MO_32) { + fixup = NEED_UMIN; + } else { + fixup = NEED_BIAS | NEED_INV; + } + break; + case TCG_COND_GTU: + if (vece <= MO_32) { + fixup = NEED_UMIN | NEED_INV; + } else { + fixup = NEED_BIAS; + } + break; + case TCG_COND_GEU: + if (vece <= MO_32) { + fixup = NEED_UMAX; + } else { + fixup = NEED_BIAS | NEED_SWAP | NEED_INV; + } + break; + case TCG_COND_LTU: + if (vece <= MO_32) { + fixup = NEED_UMAX | NEED_INV; + } else { + fixup = NEED_BIAS | NEED_SWAP; + } + break; + default: + g_assert_not_reached(); + } if (fixup & NEED_INV) { cond = tcg_invert_cond(cond); @@ -3500,7 +3533,16 @@ static bool expand_vec_cmp_noinv(TCGType type, unsigned vece, TCGv_vec v0, } t1 = t2 = NULL; - if (fixup & NEED_BIAS) { + if (fixup & (NEED_UMIN | NEED_UMAX)) { + t1 = tcg_temp_new_vec(type); + if (fixup & NEED_UMIN) { + tcg_gen_umin_vec(vece, t1, v1, v2); + } else { + tcg_gen_umax_vec(vece, t1, v1, v2); + } + v2 = t1; + cond = TCG_COND_EQ; + } else if (fixup & NEED_BIAS) { t1 = tcg_temp_new_vec(type); t2 = tcg_temp_new_vec(type); tcg_gen_dupi_vec(vece, t2, 1ull << ((8 << vece) - 1)); From patchwork Wed May 22 22:28:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 164916 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp1420920ili; Wed, 22 May 2019 15:41:41 -0700 (PDT) X-Google-Smtp-Source: APXvYqxfwbuuCVya/P6ZZl4y99YP7tvGZPwU6O6TPt0G1f4kN2IeBoimsGEnr/Jp8NMmc62j88Ef X-Received: by 2002:a50:b062:: with SMTP id i89mr94458322edd.85.1558564901781; Wed, 22 May 2019 15:41:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1558564901; cv=none; d=google.com; s=arc-20160816; b=p4W/Di9wBwIVHHraynXSzZnNN+L3js3Ep4ZZIn6EZ5vpK11CYMlcgphQLHth35bpo5 r9Y6MXpienlgDQqU3ps52y1rlYA7v1892Rf7v2dfWVUSgy1YJAztz1KBWb0Yz1bLXmjg oAmFlaeMM52wtdInuZY/uBh7cK7WWZSeyTm2Xuc5WNtgNXr5mhxl8aY6WBz6O5CyeLpC bhAoG/EMjx5pnEoX3e1j9RDU2oHnQgPZmCKn4Uq22I1EDa081Ew/XLRh9SdnKmu9rGFo m37UV/bbV/i2rNkwelRrF6JHD0OXJSenfeZzVee/A9XNzqHVwYNhlW0tU1vtHYSDPXmz gBfA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=2Z/xMZNbQQoNoZQShCqBViE6D5UwKBhH3tq+yJTAfz4=; b=MyQtsmrWqQrY1A2lj7YLo4ll5JbtdeNuJF8X8ZsKAIQZVD8J/z57aP+B7g/F4ACYuc qfnDIk6RRC6nKdmsyBvd0K/QzWXC33c6uDkLptqJCRxRGwAed77RNTL24KaIOjd1Um5Q q299tKHipgJksLLAQurgUDcZ2ecJK7naPv54yASq92RKxJnna/B7IX7ds7UiXiqSRWvn PostC4CPiB6+5GwKXYtgE+0TQI0h8HrtLV4lVpMOOvxB5e7pUnex2HZ6aguc0QunLI7o HQeD/npbtTQ7vdljtswIyZxtL7ur1hVbI7FqXaRrxoUhId7U7TrnqgZlsryypa825Sy5 gjdA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=K8ibIvSs; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::b44 Subject: [Qemu-devel] [PULL 11/16] tcg/aarch64: Support vector bitwise select value X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The instruction set has 3 insns that perform the same operation, only varying in which operand must overlap the destination. We can represent the operation without overlap and choose based on the operands seen. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.h | 2 +- tcg/aarch64/tcg-target.inc.c | 24 +++++++++++++++++++++++- 2 files changed, 24 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index b4a9d36bbc..ca214f6909 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -140,7 +140,7 @@ typedef enum { #define TCG_TARGET_HAS_mul_vec 1 #define TCG_TARGET_HAS_sat_vec 1 #define TCG_TARGET_HAS_minmax_vec 1 -#define TCG_TARGET_HAS_bitsel_vec 0 +#define TCG_TARGET_HAS_bitsel_vec 1 #define TCG_TARGET_HAS_cmpsel_vec 0 #define TCG_TARGET_DEFAULT_MO (0) diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index 40bf35079a..e99149cda7 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -523,6 +523,9 @@ typedef enum { I3616_ADD = 0x0e208400, I3616_AND = 0x0e201c00, I3616_BIC = 0x0e601c00, + I3616_BIF = 0x2ee01c00, + I3616_BIT = 0x2ea01c00, + I3616_BSL = 0x2e601c00, I3616_EOR = 0x2e201c00, I3616_MUL = 0x0e209c00, I3616_ORR = 0x0ea01c00, @@ -2181,7 +2184,7 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, TCGType type = vecl + TCG_TYPE_V64; unsigned is_q = vecl; - TCGArg a0, a1, a2; + TCGArg a0, a1, a2, a3; a0 = args[0]; a1 = args[1]; @@ -2304,6 +2307,20 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, } break; + case INDEX_op_bitsel_vec: + a3 = args[3]; + if (a0 == a3) { + tcg_out_insn(s, 3616, BIT, is_q, 0, a0, a2, a1); + } else if (a0 == a2) { + tcg_out_insn(s, 3616, BIF, is_q, 0, a0, a3, a1); + } else { + if (a0 != a1) { + tcg_out_mov(s, type, a0, a1); + } + tcg_out_insn(s, 3616, BSL, is_q, 0, a0, a2, a3); + } + break; + case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ case INDEX_op_dupi_vec: /* Always emitted via tcg_out_movi. */ case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ @@ -2334,6 +2351,7 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) case INDEX_op_usadd_vec: case INDEX_op_ussub_vec: case INDEX_op_shlv_vec: + case INDEX_op_bitsel_vec: return 1; case INDEX_op_shrv_vec: case INDEX_op_sarv_vec: @@ -2408,6 +2426,8 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) = { .args_ct_str = { "r", "r", "rA", "rZ", "rZ" } }; static const TCGTargetOpDef add2 = { .args_ct_str = { "r", "r", "rZ", "rZ", "rA", "rMZ" } }; + static const TCGTargetOpDef w_w_w_w + = { .args_ct_str = { "w", "w", "w", "w" } }; switch (op) { case INDEX_op_goto_ptr: @@ -2580,6 +2600,8 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) return &w_wr; case INDEX_op_cmp_vec: return &w_w_wZ; + case INDEX_op_bitsel_vec: + return &w_w_w_w; default: return NULL; From patchwork Wed May 22 22:28:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 164915 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp1420200ili; Wed, 22 May 2019 15:40:45 -0700 (PDT) X-Google-Smtp-Source: APXvYqz3q0sPiYXoCYY5du3CUfs392vmQF3oMSxhNgUwwa+Dnt+eesKvxMSRMAZZQPD9pIEdnmRx X-Received: by 2002:a17:906:e101:: with SMTP id gj1mr37350911ejb.54.1558564844928; Wed, 22 May 2019 15:40:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1558564844; cv=none; d=google.com; s=arc-20160816; b=EK0hHpWNU+3u4TktjFdgKz7Z025E1tvUIGAs4O2cu/fIPr/zIneExqHVlYBzRSIira PHMhyVexMZycY/cxhdK83qhh2YRfjw7+1tA5OgWA1egyt+EnZv8KlXlad+hbfsA4JFbz JHpCrvrjKzG6hfI3TljhxEDzy1P1Gw2Uv2anPXuLLgQPPhInYiUay1z9AoWH1kStlG2X nocZJhFgU2YZeGEur5EX8Nf0ZNeF7jGlKU6QgamotBVvfxF9rka91r1d5OH4vs/Mhpow lekTjoyzjxTuFJe2OXqWmUTylKVQ1YcMVYP/qpk698u4Tr2HGJ1zZof/reAp7QMzpPRK Ubyw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=/D6aLozHwnS1sPI8iNsL3pMxewPkp4IUhb3tHD+DOe4=; b=n7M0uz/A3z/BhKhkkib1STG/Q4u6AYELqZ7Cr1KPOjCSfVqByJJPaIP2VOpUssBL0X OzlCjJt77DF6/BFSRbZOpo7rvJ3LAqKtBgytnmxvlejw1Mdgyb7q6o2SeBlvDiUcDmot x5Y/Lt8ZK4NndJYvCVnygfZCIcs1aeiA5k8yazYBkmkg6DdQGm05f2nbUPqxYosb9GhE lrOk52Bk+3k6GMJy4uoKmFUWlmfaoKp1A5QmAO+BUmf3oMVSaHN4Wfhpg60SUKZJ98k+ 0KQkSVl+O8rDHE2MAf8obV4nXHE/h12V3V0j1Is/1nvVagVf9ph2XUgBb1042Zwysas5 i/PA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=VEiP8vmV; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::b42 Subject: [Qemu-devel] [PULL 12/16] tcg/aarch64: Split up is_fimm X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" There are several sub-classes of vector immediate, and only MOVI can use them all. This will enable usage of MVNI and ORRI, which use progressively fewer sub-classes. This patch adds no new functionality, merely splits the function and moves part of the logic into tcg_out_dupi_vec. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.inc.c | 205 ++++++++++++++++++++--------------- 1 file changed, 120 insertions(+), 85 deletions(-) -- 2.17.1 diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index e99149cda7..1422dfebe2 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -190,103 +190,86 @@ static inline bool is_limm(uint64_t val) return (val & (val - 1)) == 0; } -/* Match a constant that is valid for vectors. */ -static bool is_fimm(uint64_t v64, int *op, int *cmode, int *imm8) +/* Return true if v16 is a valid 16-bit shifted immediate. */ +static bool is_shimm16(uint16_t v16, int *cmode, int *imm8) { - int i; - - *op = 0; - /* Match replication across 8 bits. */ - if (v64 == dup_const(MO_8, v64)) { - *cmode = 0xe; - *imm8 = v64 & 0xff; + if (v16 == (v16 & 0xff)) { + *cmode = 0x8; + *imm8 = v16 & 0xff; + return true; + } else if (v16 == (v16 & 0xff00)) { + *cmode = 0xa; + *imm8 = v16 >> 8; return true; } - /* Match replication across 16 bits. */ - if (v64 == dup_const(MO_16, v64)) { - uint16_t v16 = v64; + return false; +} - if (v16 == (v16 & 0xff)) { - *cmode = 0x8; - *imm8 = v16 & 0xff; - return true; - } else if (v16 == (v16 & 0xff00)) { - *cmode = 0xa; - *imm8 = v16 >> 8; - return true; - } +/* Return true if v32 is a valid 32-bit shifted immediate. */ +static bool is_shimm32(uint32_t v32, int *cmode, int *imm8) +{ + if (v32 == (v32 & 0xff)) { + *cmode = 0x0; + *imm8 = v32 & 0xff; + return true; + } else if (v32 == (v32 & 0xff00)) { + *cmode = 0x2; + *imm8 = (v32 >> 8) & 0xff; + return true; + } else if (v32 == (v32 & 0xff0000)) { + *cmode = 0x4; + *imm8 = (v32 >> 16) & 0xff; + return true; + } else if (v32 == (v32 & 0xff000000)) { + *cmode = 0x6; + *imm8 = v32 >> 24; + return true; } - /* Match replication across 32 bits. */ - if (v64 == dup_const(MO_32, v64)) { - uint32_t v32 = v64; + return false; +} - if (v32 == (v32 & 0xff)) { - *cmode = 0x0; - *imm8 = v32 & 0xff; - return true; - } else if (v32 == (v32 & 0xff00)) { - *cmode = 0x2; - *imm8 = (v32 >> 8) & 0xff; - return true; - } else if (v32 == (v32 & 0xff0000)) { - *cmode = 0x4; - *imm8 = (v32 >> 16) & 0xff; - return true; - } else if (v32 == (v32 & 0xff000000)) { - *cmode = 0x6; - *imm8 = v32 >> 24; - return true; - } else if ((v32 & 0xffff00ff) == 0xff) { - *cmode = 0xc; - *imm8 = (v32 >> 8) & 0xff; - return true; - } else if ((v32 & 0xff00ffff) == 0xffff) { - *cmode = 0xd; - *imm8 = (v32 >> 16) & 0xff; - return true; - } - /* Match forms of a float32. */ - if (extract32(v32, 0, 19) == 0 - && (extract32(v32, 25, 6) == 0x20 - || extract32(v32, 25, 6) == 0x1f)) { - *cmode = 0xf; - *imm8 = (extract32(v32, 31, 1) << 7) - | (extract32(v32, 25, 1) << 6) - | extract32(v32, 19, 6); - return true; - } +/* Return true if v32 is a valid 32-bit shifting ones immediate. */ +static bool is_soimm32(uint32_t v32, int *cmode, int *imm8) +{ + if ((v32 & 0xffff00ff) == 0xff) { + *cmode = 0xc; + *imm8 = (v32 >> 8) & 0xff; + return true; + } else if ((v32 & 0xff00ffff) == 0xffff) { + *cmode = 0xd; + *imm8 = (v32 >> 16) & 0xff; + return true; } - /* Match forms of a float64. */ + return false; +} + +/* Return true if v32 is a valid float32 immediate. */ +static bool is_fimm32(uint32_t v32, int *cmode, int *imm8) +{ + if (extract32(v32, 0, 19) == 0 + && (extract32(v32, 25, 6) == 0x20 + || extract32(v32, 25, 6) == 0x1f)) { + *cmode = 0xf; + *imm8 = (extract32(v32, 31, 1) << 7) + | (extract32(v32, 25, 1) << 6) + | extract32(v32, 19, 6); + return true; + } + return false; +} + +/* Return true if v64 is a valid float64 immediate. */ +static bool is_fimm64(uint64_t v64, int *cmode, int *imm8) +{ if (extract64(v64, 0, 48) == 0 && (extract64(v64, 54, 9) == 0x100 || extract64(v64, 54, 9) == 0x0ff)) { *cmode = 0xf; - *op = 1; *imm8 = (extract64(v64, 63, 1) << 7) | (extract64(v64, 54, 1) << 6) | extract64(v64, 48, 6); return true; } - /* Match bytes of 0x00 and 0xff. */ - for (i = 0; i < 64; i += 8) { - uint64_t byte = extract64(v64, i, 8); - if (byte != 0 && byte != 0xff) { - break; - } - } - if (i == 64) { - *cmode = 0xe; - *op = 1; - *imm8 = (extract64(v64, 0, 1) << 0) - | (extract64(v64, 8, 1) << 1) - | (extract64(v64, 16, 1) << 2) - | (extract64(v64, 24, 1) << 3) - | (extract64(v64, 32, 1) << 4) - | (extract64(v64, 40, 1) << 5) - | (extract64(v64, 48, 1) << 6) - | (extract64(v64, 56, 1) << 7); - return true; - } return false; } @@ -817,11 +800,63 @@ static void tcg_out_logicali(TCGContext *s, AArch64Insn insn, TCGType ext, static void tcg_out_dupi_vec(TCGContext *s, TCGType type, TCGReg rd, tcg_target_long v64) { - int op, cmode, imm8; + bool q = type == TCG_TYPE_V128; + int cmode, imm8, i; - if (is_fimm(v64, &op, &cmode, &imm8)) { - tcg_out_insn(s, 3606, MOVI, type == TCG_TYPE_V128, rd, op, cmode, imm8); - } else if (type == TCG_TYPE_V128) { + /* Test all bytes equal first. */ + if (v64 == dup_const(MO_8, v64)) { + imm8 = (uint8_t)v64; + tcg_out_insn(s, 3606, MOVI, q, rd, 0, 0xe, imm8); + return; + } + + /* + * Test all bytes 0x00 or 0xff second. This can match cases that + * might otherwise take 2 or 3 insns for MO_16 or MO_32 below. + */ + for (i = imm8 = 0; i < 8; i++) { + uint8_t byte = v64 >> (i * 8); + if (byte == 0xff) { + imm8 |= 1 << i; + } else if (byte != 0) { + goto fail_bytes; + } + } + tcg_out_insn(s, 3606, MOVI, q, rd, 1, 0xe, imm8); + return; + fail_bytes: + + /* + * Tests for various replications. For each element width, if we + * cannot find an expansion there's no point checking a larger + * width because we already know by replication it cannot match. + */ + if (v64 == dup_const(MO_16, v64)) { + uint16_t v16 = v64; + + if (is_shimm16(v16, &cmode, &imm8)) { + tcg_out_insn(s, 3606, MOVI, q, rd, 0, cmode, imm8); + return; + } + } else if (v64 == dup_const(MO_32, v64)) { + uint32_t v32 = v64; + + if (is_shimm32(v32, &cmode, &imm8) || + is_soimm32(v32, &cmode, &imm8) || + is_fimm32(v32, &cmode, &imm8)) { + tcg_out_insn(s, 3606, MOVI, q, rd, 0, cmode, imm8); + return; + } + } else if (is_fimm64(v64, &cmode, &imm8)) { + tcg_out_insn(s, 3606, MOVI, q, rd, 1, cmode, imm8); + return; + } + + /* + * As a last resort, load from the constant pool. Sadly there + * is no LD1R (literal), so store the full 16-byte vector. + */ + if (type == TCG_TYPE_V128) { new_pool_l2(s, R_AARCH64_CONDBR19, s->code_ptr, 0, v64, v64); tcg_out_insn(s, 3305, LDR_v128, 0, rd); } else { From patchwork Wed May 22 22:28:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 164914 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp1419880ili; Wed, 22 May 2019 15:40:21 -0700 (PDT) X-Google-Smtp-Source: APXvYqyADSuQQ4Plp6W9QUs7RZG71zpPfmCHXrQ1Ri9qsTxLhXAJ+b2SdfLGcFEgah3491TMVmcO X-Received: by 2002:a50:d519:: with SMTP id u25mr94932696edi.185.1558564821596; Wed, 22 May 2019 15:40:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1558564821; cv=none; d=google.com; s=arc-20160816; b=hHFBWxH8EJXw8Vo0SbSWX7Z+10dTa0dwOkAe3sWzuW9cn2ktKUI7K/CX1uYlS/tH6e YTAmBv5rUf3ySUrcPVkf59DKE9CixDp7aJ8MbT9HSbDJl4xA5jHbO53Vfdep6c0bHyic J+VRSnx0L2I7ZXaqCIaDWaJngd8LEuxOnWN06TlV+A/DgWVJb3dZfIQrapoaws5J5ncc 90njC5EeYgSVfHEH24v8DYI1V40cqoovm2r/r/4kWEGwRRxCRzPKa9ZfpF5hTH+1LLTY LfoTJ2myzjtZ/eMVKCeyNrTNvu08Ur6rz6h2RYr4HI9o/FEl3X+yqvf2NYvGZ6TAcgjy 70yQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=5pgxUU1cRl5UBw70ixoMtifwIrAs5XS+sRdx95+Fg/g=; b=uzFZ2YHbBUN65/hLpLUXBhFYlKbpyN3kpioA3bzjsKiI9ItaxyyejSR4Q84/HA2mky IAt6mlNwrmjKAjCJlYzMe3iXVe9tx9ThOTsAZwU1qSk6RXCUQw0QAmuAp+rEPfJliTOc BRl+OR8HPiNAjK7BWVE2iDx33bbuOBdwuX2e+K/5lehe06vclOPVmJe/SJKTHQ8GTNyL 03x82OogqGpi90sD+QL5aMXCrdEmzYrRFvyATZwVTbbIYW6STe+ePD3uDrRGKj1KbM0J obgz0+7P9tsWTgDtlIzwJmy3tl08S3FSK/jpHlJrLiWZpuCCRxE++Tdp+ZmbRKOLnHLc niQA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ZmIZP62u; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::c43 Subject: [Qemu-devel] [PULL 13/16] tcg/aarch64: Use MVNI in tcg_out_dupi_vec X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The compliment of a subset of immediates can be computed with a single instruction. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.inc.c | 11 +++++++++++ 1 file changed, 11 insertions(+) -- 2.17.1 diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index 1422dfebe2..0b8b733805 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -494,6 +494,7 @@ typedef enum { /* AdvSIMD modified immediate */ I3606_MOVI = 0x0f000400, + I3606_MVNI = 0x2f000400, /* AdvSIMD shift by immediate */ I3614_SSHR = 0x0f000400, @@ -838,8 +839,13 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type, tcg_out_insn(s, 3606, MOVI, q, rd, 0, cmode, imm8); return; } + if (is_shimm16(~v16, &cmode, &imm8)) { + tcg_out_insn(s, 3606, MVNI, q, rd, 0, cmode, imm8); + return; + } } else if (v64 == dup_const(MO_32, v64)) { uint32_t v32 = v64; + uint32_t n32 = ~v32; if (is_shimm32(v32, &cmode, &imm8) || is_soimm32(v32, &cmode, &imm8) || @@ -847,6 +853,11 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type, tcg_out_insn(s, 3606, MOVI, q, rd, 0, cmode, imm8); return; } + if (is_shimm32(n32, &cmode, &imm8) || + is_soimm32(n32, &cmode, &imm8)) { + tcg_out_insn(s, 3606, MVNI, q, rd, 0, cmode, imm8); + return; + } } else if (is_fimm64(v64, &cmode, &imm8)) { tcg_out_insn(s, 3606, MOVI, q, rd, 1, cmode, imm8); return; From patchwork Wed May 22 22:28:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 164908 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp1414287ili; Wed, 22 May 2019 15:32:46 -0700 (PDT) X-Google-Smtp-Source: APXvYqyJSEozNNl7eDOE6iWdId2x3c+vJO0gftJzeNRD76JoitkLtE4i9Zv2oSdObb2u8o7EQsQ8 X-Received: by 2002:a17:906:cc92:: with SMTP id oq18mr47152460ejb.230.1558564366651; Wed, 22 May 2019 15:32:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1558564366; cv=none; d=google.com; s=arc-20160816; b=Hm0S2dlm8Rs0oARmZurJSf1FZGHSn1nghmLcqkr/Q+2Dcs/vKdTh+TpVHO2ve8sqm0 TaliGgF6G0zc5eyRMilwDdMyRsL7poqXkPXSAIOet1m31h+c64e9PPzNyVqdOP11Vxn3 RE4YLyLb7LSJ6FMj9TADT3W54e1PYZIOJ8xd8VutvS4/WXK1peMNL65/pRfn6s7sSNV3 QbVQtBqK9xX5JzTbTrEdmPBPLjyjKnKOANXQAQINU6+dZ812SZ3o7iOMFGv4bFx7BK9Q Po7FdwahucTU3DjUMT/0odJAxU7PvrSVly/BmWTKigCziDRVbMgVeEoJpmZp1oTeDGGy tzqA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=zqTcnSP07QNrvm+tUagQdKAYnifB03tbX5A/KwjlV2s=; b=VEtFjkt1ACcet0qNpI7elOgTrumXeRSpYHA+G01GMWBDw/xJWufPip+zS7pl3eEVdV PAs1frf/8uvm1fARXy401XWOKU9TA2WrvgMl+VxfWKkq4NO8EwCDkXVLbKbNHQjtLtkH BPA7KV7cUSGz8gsmCEeHW/BAu/rNEGbcUmBAmGFrb9kF95a86KdK4GBXBBqrC1cDHXYQ keLCIK5aU1p0/B1l9ZtdVYeCUHjXeayI/fzB02KQkVDUq1ZB4MnrjG9IzI3H9DF1FWJz jTaia529LHMGYqD4ZWmawytMgpAzEAG3aUCQhj51pm73xu7YoxED/M8nmSsLcsNXBNEq Kp0w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=vHLqMPz8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::b41 Subject: [Qemu-devel] [PULL 14/16] tcg/aarch64: Build vector immediates with two insns X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Use MOVI+ORR or MVNI+BIC in order to build some vector constants, as opposed to dropping them to the constant pool. This includes all 16-bit constants and a similar set of 32-bit constants. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.inc.c | 47 ++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) -- 2.17.1 diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index 0b8b733805..52c18074ae 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -273,6 +273,26 @@ static bool is_fimm64(uint64_t v64, int *cmode, int *imm8) return false; } +/* + * Return non-zero if v32 can be formed by MOVI+ORR. + * Place the parameters for MOVI in (cmode, imm8). + * Return the cmode for ORR; the imm8 can be had via extraction from v32. + */ +static int is_shimm32_pair(uint32_t v32, int *cmode, int *imm8) +{ + int i; + + for (i = 6; i > 0; i -= 2) { + /* Mask out one byte we can add with ORR. */ + uint32_t tmp = v32 & ~(0xffu << (i * 4)); + if (is_shimm32(tmp, cmode, imm8) || + is_soimm32(tmp, cmode, imm8)) { + break; + } + } + return i; +} + static int tcg_target_const_match(tcg_target_long val, TCGType type, const TCGArgConstraint *arg_ct) { @@ -495,6 +515,8 @@ typedef enum { /* AdvSIMD modified immediate */ I3606_MOVI = 0x0f000400, I3606_MVNI = 0x2f000400, + I3606_BIC = 0x2f001400, + I3606_ORR = 0x0f001400, /* AdvSIMD shift by immediate */ I3614_SSHR = 0x0f000400, @@ -843,6 +865,14 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type, tcg_out_insn(s, 3606, MVNI, q, rd, 0, cmode, imm8); return; } + + /* + * Otherwise, all remaining constants can be loaded in two insns: + * rd = v16 & 0xff, rd |= v16 & 0xff00. + */ + tcg_out_insn(s, 3606, MOVI, q, rd, 0, 0x8, v16 & 0xff); + tcg_out_insn(s, 3606, ORR, q, rd, 0, 0xa, v16 >> 8); + return; } else if (v64 == dup_const(MO_32, v64)) { uint32_t v32 = v64; uint32_t n32 = ~v32; @@ -858,6 +888,23 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type, tcg_out_insn(s, 3606, MVNI, q, rd, 0, cmode, imm8); return; } + + /* + * Restrict the set of constants to those we can load with + * two instructions. Others we load from the pool. + */ + i = is_shimm32_pair(v32, &cmode, &imm8); + if (i) { + tcg_out_insn(s, 3606, MOVI, q, rd, 0, cmode, imm8); + tcg_out_insn(s, 3606, ORR, q, rd, 0, i, extract32(v32, i * 4, 8)); + return; + } + i = is_shimm32_pair(n32, &cmode, &imm8); + if (i) { + tcg_out_insn(s, 3606, MVNI, q, rd, 0, cmode, imm8); + tcg_out_insn(s, 3606, BIC, q, rd, 0, i, extract32(n32, i * 4, 8)); + return; + } } else if (is_fimm64(v64, &cmode, &imm8)) { tcg_out_insn(s, 3606, MOVI, q, rd, 1, cmode, imm8); return; From patchwork Wed May 22 22:28:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 164917 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp1421795ili; Wed, 22 May 2019 15:42:55 -0700 (PDT) X-Google-Smtp-Source: APXvYqwbFaOmRX3BeXPxue5s0ExbRaG3pQRL2+Qc1KuLx6zAMpoiiMbh51/wyxJ3wZcb6l8hMyKA X-Received: by 2002:a17:906:7206:: with SMTP id m6mr74006010ejk.39.1558564975442; Wed, 22 May 2019 15:42:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1558564975; cv=none; d=google.com; s=arc-20160816; b=LiRZFiXbu8HYQmjEK8s3hGERb49yzhBExiUjQfvi9jERAvVtB7aj+pfXtltyRWdnjh g7HtEgMU7Ceg3VqyhMLAmszJIUUhrDVOn1tAEgTuG5iudwx7BKwpAy6PrXDg4eHkcC2v sKfMjZATLL3h8GmT28VFZFXiWBgz/F3TgjfYDck6IGvB6FybZLhafDqqAN3sIgEXyEaP Uo1J4N2lEYORGsa4XACDB2yZrAriuoJhaWXW99bXi+EEydE/KhhJS7t8ui6JxYlLwgNr wyTtemhNZxkwruaRaPHD52EczUYYtC5LESJ/BiFqR9CJfa4LirDlA0IGadQyStpSOEPA yhrQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=AirXKI1PS8HjM151RJTWK1/DcdzF7g0f+0zrycENkFI=; b=SKLZp3KkWnVyG5XTBHd6CdtipM9jT7kboPIJeE/52Ke/bFW1IDsqIwqFFYJTIQ4Uz7 dl0hBxQp+cm3CJ38enZ3BfS5vjf7VAxqddMPQme1YULqYg/aSlcO3ZGG0H9cDlncm1gO 3q0pyEg+5RnUecYhjqlYz/gkqtNoge8VfP68sEaTOfMBCGzVwjY1MvPhQvfgvximg5Rk UDuISp4SOGWDXyQG7HYZlv04SnN9l2/5/g2axURXAFjFglfjGZ+Sqelmjw9zJRb+dtSi rYt9Fv2K8wXelwYfIfzQ1LAW3dRybnwJ0LFQYsGKftwQzhRRQiNbjih+yk81kMaD44fD 5U1Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=znq81cNx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::b30 Subject: [Qemu-devel] [PULL 15/16] tcg/aarch64: Allow immediates for vector ORR and BIC X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The allows immediates to be used for ORR and BIC, as well as the trivial inversions, ORC and AND. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.inc.c | 90 +++++++++++++++++++++++++++++++++--- 1 file changed, 83 insertions(+), 7 deletions(-) -- 2.17.1 diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index 52c18074ae..9e1dad9696 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -119,6 +119,8 @@ static inline bool patch_reloc(tcg_insn_unit *code_ptr, int type, #define TCG_CT_CONST_LIMM 0x200 #define TCG_CT_CONST_ZERO 0x400 #define TCG_CT_CONST_MONE 0x800 +#define TCG_CT_CONST_ORRI 0x1000 +#define TCG_CT_CONST_ANDI 0x2000 /* parse target specific constraints */ static const char *target_parse_constraint(TCGArgConstraint *ct, @@ -154,6 +156,12 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, case 'M': /* minus one */ ct->ct |= TCG_CT_CONST_MONE; break; + case 'O': /* vector orr/bic immediate */ + ct->ct |= TCG_CT_CONST_ORRI; + break; + case 'N': /* vector orr/bic immediate, inverted */ + ct->ct |= TCG_CT_CONST_ANDI; + break; case 'Z': /* zero */ ct->ct |= TCG_CT_CONST_ZERO; break; @@ -293,6 +301,16 @@ static int is_shimm32_pair(uint32_t v32, int *cmode, int *imm8) return i; } +/* Return true if V is a valid 16-bit or 32-bit shifted immediate. */ +static bool is_shimm1632(uint32_t v32, int *cmode, int *imm8) +{ + if (v32 == deposit32(v32, 16, 16, v32)) { + return is_shimm16(v32, cmode, imm8); + } else { + return is_shimm32(v32, cmode, imm8); + } +} + static int tcg_target_const_match(tcg_target_long val, TCGType type, const TCGArgConstraint *arg_ct) { @@ -317,6 +335,23 @@ static int tcg_target_const_match(tcg_target_long val, TCGType type, return 1; } + switch (ct & (TCG_CT_CONST_ORRI | TCG_CT_CONST_ANDI)) { + case 0: + break; + case TCG_CT_CONST_ANDI: + val = ~val; + /* fallthru */ + case TCG_CT_CONST_ORRI: + if (val == deposit64(val, 32, 32, val)) { + int cmode, imm8; + return is_shimm1632(val, &cmode, &imm8); + } + break; + default: + /* Both bits should not be set for the same insn. */ + g_assert_not_reached(); + } + return 0; } @@ -2278,6 +2313,7 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, TCGType type = vecl + TCG_TYPE_V64; unsigned is_q = vecl; TCGArg a0, a1, a2, a3; + int cmode, imm8; a0 = args[0]; a1 = args[1]; @@ -2309,20 +2345,56 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, tcg_out_insn(s, 3617, ABS, is_q, vece, a0, a1); break; case INDEX_op_and_vec: + if (const_args[2]) { + is_shimm1632(~a2, &cmode, &imm8); + if (a0 == a1) { + tcg_out_insn(s, 3606, BIC, is_q, a0, 0, cmode, imm8); + return; + } + tcg_out_insn(s, 3606, MVNI, is_q, a0, 0, cmode, imm8); + a2 = a0; + } tcg_out_insn(s, 3616, AND, is_q, 0, a0, a1, a2); break; case INDEX_op_or_vec: + if (const_args[2]) { + is_shimm1632(a2, &cmode, &imm8); + if (a0 == a1) { + tcg_out_insn(s, 3606, ORR, is_q, a0, 0, cmode, imm8); + return; + } + tcg_out_insn(s, 3606, MOVI, is_q, a0, 0, cmode, imm8); + a2 = a0; + } tcg_out_insn(s, 3616, ORR, is_q, 0, a0, a1, a2); break; - case INDEX_op_xor_vec: - tcg_out_insn(s, 3616, EOR, is_q, 0, a0, a1, a2); - break; case INDEX_op_andc_vec: + if (const_args[2]) { + is_shimm1632(a2, &cmode, &imm8); + if (a0 == a1) { + tcg_out_insn(s, 3606, BIC, is_q, a0, 0, cmode, imm8); + return; + } + tcg_out_insn(s, 3606, MOVI, is_q, a0, 0, cmode, imm8); + a2 = a0; + } tcg_out_insn(s, 3616, BIC, is_q, 0, a0, a1, a2); break; case INDEX_op_orc_vec: + if (const_args[2]) { + is_shimm1632(~a2, &cmode, &imm8); + if (a0 == a1) { + tcg_out_insn(s, 3606, ORR, is_q, a0, 0, cmode, imm8); + return; + } + tcg_out_insn(s, 3606, MVNI, is_q, a0, 0, cmode, imm8); + a2 = a0; + } tcg_out_insn(s, 3616, ORN, is_q, 0, a0, a1, a2); break; + case INDEX_op_xor_vec: + tcg_out_insn(s, 3616, EOR, is_q, 0, a0, a1, a2); + break; case INDEX_op_ssadd_vec: tcg_out_insn(s, 3616, SQADD, is_q, vece, a0, a1, a2); break; @@ -2505,6 +2577,8 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) static const TCGTargetOpDef lZ_l = { .args_ct_str = { "lZ", "l" } }; static const TCGTargetOpDef r_r_r = { .args_ct_str = { "r", "r", "r" } }; static const TCGTargetOpDef w_w_w = { .args_ct_str = { "w", "w", "w" } }; + static const TCGTargetOpDef w_w_wO = { .args_ct_str = { "w", "w", "wO" } }; + static const TCGTargetOpDef w_w_wN = { .args_ct_str = { "w", "w", "wN" } }; static const TCGTargetOpDef w_w_wZ = { .args_ct_str = { "w", "w", "wZ" } }; static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } }; static const TCGTargetOpDef r_r_rA = { .args_ct_str = { "r", "r", "rA" } }; @@ -2660,11 +2734,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_add_vec: case INDEX_op_sub_vec: case INDEX_op_mul_vec: - case INDEX_op_and_vec: - case INDEX_op_or_vec: case INDEX_op_xor_vec: - case INDEX_op_andc_vec: - case INDEX_op_orc_vec: case INDEX_op_ssadd_vec: case INDEX_op_sssub_vec: case INDEX_op_usadd_vec: @@ -2691,6 +2761,12 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) return &w_r; case INDEX_op_dup_vec: return &w_wr; + case INDEX_op_or_vec: + case INDEX_op_andc_vec: + return &w_w_wO; + case INDEX_op_and_vec: + case INDEX_op_orc_vec: + return &w_w_wN; case INDEX_op_cmp_vec: return &w_w_wZ; case INDEX_op_bitsel_vec: From patchwork Wed May 22 22:28:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 164913 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp1419741ili; Wed, 22 May 2019 15:40:08 -0700 (PDT) X-Google-Smtp-Source: APXvYqxMVS0XiXmZ4J1fHmMfj1Bq1XvJ3BYijhvAom/x0KjiXCyGPqY+KDGSFU3EcpSNZttvEwlq X-Received: by 2002:aa7:c5d2:: with SMTP id h18mr51204581eds.110.1558564808513; Wed, 22 May 2019 15:40:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1558564808; cv=none; d=google.com; s=arc-20160816; b=La+Wc0HHk7LkwmIWf0cyL1KdO1rdqPUu7G2bgdoP1EKrKIn0hnm00mHktZvyFgs9Jc KkamP9MytrbjPaoLJvyIJvNfiGRm5wn2H8WvKgIKiGlnoveVs/quEMrY/ZTy4pnwh58x izQwLQ0RIQObq6IncxHYWelsXU5GtHpbyWcF4o8H/V16lDHtlBFwq8fnIPjfPK99Ju9q mNoGMiUZVyIT9uSjIfsEscjYH8HVQurcKvbeVHADjkt+fQVyd/RyuoQ6hF8t3zvMMMTC tiNQwlVENBSnbsN9hLTC7/AyLbLS2xknh7BaNVdBBu5Et17JtnmBObdxzAMiHQcsLpqF DxGg== ARC-Message-Signature: i=1; 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X-Received-From: 2607:f8b0:4864:20::b42 Subject: [Qemu-devel] [PULL 16/16] tcg/i386: Use MOVDQA for TCG_TYPE_V128 load/store X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This instruction raises #GP, aka SIGSEGV, if the effective address is not aligned to 16-bytes. We have assertions in tcg-op-gvec.c that the offset from ENV is aligned, for vector types <= V128. But the offset itself does not validate that the final pointer is aligned -- one must also remember to use the QEMU_ALIGNED() attribute on the vector member within ENV. PowerPC Altivec has vector load/store instructions that silently discard the low 4 bits of the address, making alignment mistakes difficult to discover. Aid that by making the most popular host visibly signal the error. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.inc.c | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 6ec5e60448..c0443da4af 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -1082,14 +1082,24 @@ static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, } /* FALLTHRU */ case TCG_TYPE_V64: + /* There is no instruction that can validate 8-byte alignment. */ tcg_debug_assert(ret >= 16); tcg_out_vex_modrm_offset(s, OPC_MOVQ_VqWq, ret, 0, arg1, arg2); break; case TCG_TYPE_V128: + /* + * The gvec infrastructure is asserts that v128 vector loads + * and stores use a 16-byte aligned offset. Validate that the + * final pointer is aligned by using an insn that will SIGSEGV. + */ tcg_debug_assert(ret >= 16); - tcg_out_vex_modrm_offset(s, OPC_MOVDQU_VxWx, ret, 0, arg1, arg2); + tcg_out_vex_modrm_offset(s, OPC_MOVDQA_VxWx, ret, 0, arg1, arg2); break; case TCG_TYPE_V256: + /* + * The gvec infrastructure only requires 16-byte alignment, + * so here we must use an unaligned load. + */ tcg_debug_assert(ret >= 16); tcg_out_vex_modrm_offset(s, OPC_MOVDQU_VxWx | P_VEXL, ret, 0, arg1, arg2); @@ -1117,14 +1127,24 @@ static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, } /* FALLTHRU */ case TCG_TYPE_V64: + /* There is no instruction that can validate 8-byte alignment. */ tcg_debug_assert(arg >= 16); tcg_out_vex_modrm_offset(s, OPC_MOVQ_WqVq, arg, 0, arg1, arg2); break; case TCG_TYPE_V128: + /* + * The gvec infrastructure is asserts that v128 vector loads + * and stores use a 16-byte aligned offset. Validate that the + * final pointer is aligned by using an insn that will SIGSEGV. + */ tcg_debug_assert(arg >= 16); - tcg_out_vex_modrm_offset(s, OPC_MOVDQU_WxVx, arg, 0, arg1, arg2); + tcg_out_vex_modrm_offset(s, OPC_MOVDQA_WxVx, arg, 0, arg1, arg2); break; case TCG_TYPE_V256: + /* + * The gvec infrastructure only requires 16-byte alignment, + * so here we must use an unaligned store. + */ tcg_debug_assert(arg >= 16); tcg_out_vex_modrm_offset(s, OPC_MOVDQU_WxVx | P_VEXL, arg, 0, arg1, arg2);