From patchwork Wed Mar 29 19:17:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 668337 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AD932C77B62 for ; Wed, 29 Mar 2023 19:17:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230225AbjC2TRu (ORCPT ); Wed, 29 Mar 2023 15:17:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53532 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230219AbjC2TRt (ORCPT ); Wed, 29 Mar 2023 15:17:49 -0400 Received: from mail-lj1-x22b.google.com (mail-lj1-x22b.google.com [IPv6:2a00:1450:4864:20::22b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 62AA865B7 for ; Wed, 29 Mar 2023 12:17:39 -0700 (PDT) Received: by mail-lj1-x22b.google.com with SMTP id t14so17289331ljd.5 for ; Wed, 29 Mar 2023 12:17:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680117457; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=i75VT9iHv+RQumVifxqdOqhI73icvNqP22fPvcEQdoU=; b=ubhALSethZ3f57tX9OLKfXZrI7UmEbjyqygzC9f/0RoaLeA0fadM8d/iX861w3RGtM 6M2Xp8CTCtvrKlSDSqfuDmvH+eSQaoDxSQkfWdQ8S+CWQJ1O8FmR22mleoW1CBDxHrzU mWQ+qj6i/aft5e7XlmFuLW8kFRmtJHkyMdZeZ7KidKSWkMWp4cqc+psqRjfbE5rJTj78 BI1qjAf1GORpcZ+AXr5e3vfJrwYhtWw/hCOKso5L1qDvlDAQ9Moasxs8DyI4QjWleIzX ht2kkmk+DbRqlzMDmJMCQOm/ty+uKB2i9nBlkCM76D9yAeKlMC0Uof+CcDkDmmgWA+/X Dv+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680117457; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=i75VT9iHv+RQumVifxqdOqhI73icvNqP22fPvcEQdoU=; b=OpvNh965U95xiEFAfXvnumFpT7WDrKSgPr6fKaOpQw0rHOByLfid3kZ8+tMgVTxbAq WIK1XYhn8JD05KuQINvjNivxj0Xzxp1FywuMnGo+qs7oG2Vj8rcgT4SNNZOYk4la8IXw KAvypiJrqByzD7wPt/gCzlbJDurFLmOodXeONCn61r4O6QnkIG28TQpuw77honVijFlg ZEJN12ptPLUpkQdIZ1vnwxfSvDM6KV1DwMaXukcBQjNiRDO7DexOFA2ZkejfBf4FnBER CfltN5S9oCq2/IjBaCRU+6D3L0gmP2h0MsAN8Q66K2GEkbUZbRj8nsujryWExkj6SonD Mvxg== X-Gm-Message-State: AAQBX9dhk8AHw++gcY+JejDUXARefbrW3QQAKfwxUhTCaksbLx/T1PWu 7m2OgOIMs7Bt5K9UMINcialUIg== X-Google-Smtp-Source: AKy350ZfvqbkKUbInO2LPR9pxLn1EXDL65EJxZnE6SDdRR8dw4JsDXmbGJXMSH4xzaiqosqmIyGTEg== X-Received: by 2002:a2e:9c04:0:b0:29e:e7b1:1202 with SMTP id s4-20020a2e9c04000000b0029ee7b11202mr5746591lji.43.1680117457657; Wed, 29 Mar 2023 12:17:37 -0700 (PDT) Received: from [192.168.1.101] (abxj225.neoplus.adsl.tpnet.pl. [83.9.3.225]) by smtp.gmail.com with ESMTPSA id f4-20020a2e3804000000b0029ad1fc89b3sm5189658lja.60.2023.03.29.12.17.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Mar 2023 12:17:37 -0700 (PDT) From: Konrad Dybcio Date: Wed, 29 Mar 2023 21:17:28 +0200 Subject: [PATCH 1/4] arm64: dts: qcom: msm8998: Improve GPU OPP table MIME-Version: 1.0 Message-Id: <20230329-topic-adreno_opp-v1-1-24d34ac6f007@linaro.org> References: <20230329-topic-adreno_opp-v1-0-24d34ac6f007@linaro.org> In-Reply-To: <20230329-topic-adreno_opp-v1-0-24d34ac6f007@linaro.org> To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , AngeloGioacchino Del Regno , Jordan Crouse , Srinivas Kandagatla , Vivek Gautam , Vinod Koul , Rob Clark , Stephen Boyd Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Andy Gross , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1680117452; l=3231; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=BuTOgjCT81kJFbrqBabPtOTaRvqV7WCYi0kTMwbrGyM=; b=sIueiwaBv29WZYicIP/gR6f1I5FJrtIi4R/EoqLoj5R6f4Cpwk3nADWHqIKjdyJsZQNZ5nsG2rgH BOk3yWWuDdxPFGzt0xsYbCEE08QXV0aCsCc9Zw/ZrDReYpsf8AdS X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add a newline before the first OPP subnode, remove useless opp-supported-hw (there's only a single speed bin anyway) and replace opp-level with required-opps to make sure the power domain level is actually set, as opp-level is not the right property for this.. Furthermore, correct the levels that were incorrect before (confirmed against downstream). Round off frequencies that had uneven fluff on the last two digits. To top if off, leave a note that we should really be scaling the VDD GFX power domain coming from CPR4, which is not yet supported. Scaling MX is still very important though and can be considered valid for the time being - it's better if we scale at one of two voltage rails than if we scaled none.. Fixes: 87cd46d68aea ("arm64: dts: qcom: msm8998: Configure Adreno GPU and related IOMMU") Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 39 +++++++++++++++-------------------- 1 file changed, 17 insertions(+), 22 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 09b222f363c2..11952f9ed9ae 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -1396,51 +1396,46 @@ adreno_gpu: gpu@5000000 { interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; iommus = <&adreno_smmu 0>; operating-points-v2 = <&gpu_opp_table>; + /* TODO: also scale VDDGFX with CPR4 */ power-domains = <&rpmpd MSM8998_VDDMX>; status = "disabled"; gpu_opp_table: opp-table { compatible = "operating-points-v2"; - opp-710000097 { - opp-hz = /bits/ 64 <710000097>; - opp-level = ; - opp-supported-hw = <0xff>; + + opp-710000000 { + opp-hz = /bits/ 64 <710000000>; + required-opps = <&rpmpd_opp_turbo>; }; - opp-670000048 { - opp-hz = /bits/ 64 <670000048>; - opp-level = ; - opp-supported-hw = <0xff>; + opp-670000000 { + opp-hz = /bits/ 64 <670000000>; + required-opps = <&rpmpd_opp_turbo>; }; - opp-596000097 { - opp-hz = /bits/ 64 <596000097>; - opp-level = ; - opp-supported-hw = <0xff>; + opp-596000000 { + opp-hz = /bits/ 64 <596000000>; + required-opps = <&rpmpd_opp_nom>; }; - opp-515000097 { - opp-hz = /bits/ 64 <515000097>; - opp-level = ; - opp-supported-hw = <0xff>; + opp-515000000 { + opp-hz = /bits/ 64 <515000000>; + required-opps = <&rpmpd_opp_nom>; }; opp-414000000 { opp-hz = /bits/ 64 <414000000>; - opp-level = ; - opp-supported-hw = <0xff>; + required-opps = <&rpmpd_opp_svs>; }; opp-342000000 { opp-hz = /bits/ 64 <342000000>; - opp-level = ; - opp-supported-hw = <0xff>; + required-opps = <&rpmpd_opp_svs>; }; opp-257000000 { opp-hz = /bits/ 64 <257000000>; - opp-level = ; - opp-supported-hw = <0xff>; + required-opps = <&rpmpd_opp_svs>; }; }; }; From patchwork Wed Mar 29 19:17:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 668336 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B3CE4C74A5B for ; Wed, 29 Mar 2023 19:18:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230320AbjC2TR7 (ORCPT ); Wed, 29 Mar 2023 15:17:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53726 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230232AbjC2TRw (ORCPT ); Wed, 29 Mar 2023 15:17:52 -0400 Received: from mail-lj1-x22d.google.com (mail-lj1-x22d.google.com [IPv6:2a00:1450:4864:20::22d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 087F165BB for ; Wed, 29 Mar 2023 12:17:42 -0700 (PDT) Received: by mail-lj1-x22d.google.com with SMTP id e11so17260606lji.8 for ; Wed, 29 Mar 2023 12:17:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680117460; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=ViLPrFFT9b2xN8fTsQ82odoC+1YzAduaFKgrDzgE2N4=; b=TmKvhDjGEbK7ITJhW4r6/CTbtHiKWtyrpJPDMJwZfFyX6EHkUEH5D1grLtTGdkKJ7/ EkhzYL0LV6JbuuJYpYRUdlUcu/kW3v0sPj6tmd5ou3BTMw9P8xTsykZnO+V9hEACebCe reln6sZ0oY9x39Oz4CZ6M1Sh15TFl/cdMBHwm38w7Whspxk5VUxX4+bYObs7joy2pzEr s7ftr0VJsp5dXO+SmotjZnrTzRjPkOj1K4U/DumWZhGG/cZCBfj0z5yZSAd0Qw4kW+Sk qZHHWgW4C0zDgQkL9luC96KruGbBlpb/nLiB0Cd1Hv/WSmfgVCwMwp/peokhgXlthW77 MpPg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680117460; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ViLPrFFT9b2xN8fTsQ82odoC+1YzAduaFKgrDzgE2N4=; b=aSu01+gxAttq6LxeDFaN8nNhSCJicD356Mtb3MqVuhw/hsi9WoO+8M4E38el0A12YN gcIlJLrd+f0AbZ87Qz2Upxzonywd7nzhXsFwyfixOVT6zLQq0w/zgrldDoysb/GcTPso HhqUUaVxeWx8nKaSCM27N9eBN4lWz8rtPTHffJtu8IxKN3deHqoW6OPOVkisXVtqqzih qaNy09u41pDD5ORAh5i0R4so/yAG8JIlTMUnGo65XU04IeehdYNwDAhu6mawTTFERJCW QlyFDJc0h2lAX51dyaWm26ON/TP/8xchpfyDnglUAviVorvR1FWvYJ4vug9vSM10sWO7 rkPg== X-Gm-Message-State: AAQBX9egGPd7Bko1J3X/O6jxUCgL3TTD7WYEI8DmQmHZs/DbJYk9TGl4 RDFQn5Mm2BnGaK/LzUYFrmyiZg== X-Google-Smtp-Source: AKy350Y1ZQ1nM53sJv20DLlfGDuxW/q4qG1NtiQSjtVJrZ/QzCXz769W2Edvn0mJmIiDjfS46Yo+CQ== X-Received: by 2002:a05:651c:22d:b0:29b:6521:8869 with SMTP id z13-20020a05651c022d00b0029b65218869mr6141744ljn.20.1680117460348; Wed, 29 Mar 2023 12:17:40 -0700 (PDT) Received: from [192.168.1.101] (abxj225.neoplus.adsl.tpnet.pl. [83.9.3.225]) by smtp.gmail.com with ESMTPSA id f4-20020a2e3804000000b0029ad1fc89b3sm5189658lja.60.2023.03.29.12.17.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Mar 2023 12:17:40 -0700 (PDT) From: Konrad Dybcio Date: Wed, 29 Mar 2023 21:17:30 +0200 Subject: [PATCH 3/4] arm64: dts: qcom: msm8996: Improve GPU OPP table MIME-Version: 1.0 Message-Id: <20230329-topic-adreno_opp-v1-3-24d34ac6f007@linaro.org> References: <20230329-topic-adreno_opp-v1-0-24d34ac6f007@linaro.org> In-Reply-To: <20230329-topic-adreno_opp-v1-0-24d34ac6f007@linaro.org> To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , AngeloGioacchino Del Regno , Jordan Crouse , Srinivas Kandagatla , Vivek Gautam , Vinod Koul , Rob Clark , Stephen Boyd Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Andy Gross , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1680117452; l=2100; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=HHs9XUkau//fB7qwICGVh9A9wHhqzyRvVAVcwO4KDfs=; b=78jckBmXgNXovF2Ypqr1OD6fjvfwgaTJPmXe+Ex0iTBQcKoz9mv8K8UM4YxbtIL5EcHHQOAtW9iT FXeHmfBjATuEPj7/i+Ciw/ONUdUNPpV84+0+3EDe0sM4abfpIaOw X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Remove the self-explanatory comment about opp-supported-hw contents, add required-opps to ensure reasonable power domain levels are voted for (currently we've been piggybacking off of miracles and MDP votes) and add newlines between each subnode. Fixes: 69cc3114ab0f ("arm64: dts: Add Adreno GPU definitions") Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 4dd37f72e018..62ad30e94f40 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -1244,37 +1244,45 @@ gpu: gpu@b00000 { gpu_opp_table: opp-table { compatible = "operating-points-v2"; - /* - * 624Mhz is only available on speed bins 0 and 3. - * 560Mhz is only available on speed bins 0, 2 and 3. - * All the rest are available on all bins of the hardware. - */ opp-624000000 { opp-hz = /bits/ 64 <624000000>; + required-opps = <&rpmpd_opp_turbo>; opp-supported-hw = <0x09>; }; + opp-560000000 { opp-hz = /bits/ 64 <560000000>; + required-opps = <&rpmpd_opp_turbo>; opp-supported-hw = <0x0d>; }; + opp-510000000 { opp-hz = /bits/ 64 <510000000>; + required-opps = <&rpmpd_opp_nom>; opp-supported-hw = <0xff>; }; + opp-401800000 { opp-hz = /bits/ 64 <401800000>; + required-opps = <&rpmpd_opp_nom>; opp-supported-hw = <0xff>; }; + opp-315000000 { opp-hz = /bits/ 64 <315000000>; + required-opps = <&rpmpd_opp_svs>; opp-supported-hw = <0xff>; }; + opp-214000000 { opp-hz = /bits/ 64 <214000000>; + required-opps = <&rpmpd_opp_svs>; opp-supported-hw = <0xff>; }; + opp-133000000 { opp-hz = /bits/ 64 <133000000>; + required-opps = <&rpmpd_opp_svs>; opp-supported-hw = <0xff>; }; };