From patchwork Wed May 22 16:19:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 164839 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp1060136ili; Wed, 22 May 2019 09:21:08 -0700 (PDT) X-Google-Smtp-Source: APXvYqxYr/6XqNkDw8hGTUgqpMek5OepolF7kdcn8FXO/69+KmcaMgBOBTH4BFyHWF+Kdr4CKsZv X-Received: by 2002:aa7:9203:: with SMTP id 3mr97737853pfo.123.1558542068234; Wed, 22 May 2019 09:21:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1558542068; cv=none; d=google.com; s=arc-20160816; b=QraHEVAaFM6X5ytC/fg2wE9UTnxeOpJqMY+ByeluVI7x6ZH41XRVbdHxbEoROvFLmw n/og0vZrOW905nVo2FCEVFIVu3qj4PLjWG+fZ/38iFJ3m3qtJ2c59ZSAzQNsmlDlJCxB pUyHHGrQDbAYYryZXeodwA2qS9VOjhXq78cNYXGGwwVGArRMmtNvKbhoOdERK10Au8+c agwJRStBu/FOgoME3IxxTaZ4jlBbof8XpbYrxEIlpztp1noGW3h/zg+FvtMEcBPvBSfR rwF7BiX82Qh3iBW9Ga6ViQKUDB386WhHamiBuYN+4x9PnDeqI+ILz8iwejtX1A191qRt yrxw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=f/DgD/v6sg4vKR8gO+PKcIYXb0uoL9WzlNtRu2fAVGs=; b=YAPG8VcQjPItpZHWwfn0a0OBwoWszqQRztyRP6qoopKYH3qqGrZAcN0NaibNW0pGOD u7cxoQiQsyEv5BgSolB0b8y2sYmPevUueispSnTs7zA73hXST+R3+uFZfgf02LSVezSI bXu4cbDK+SIQ5w6I4t0hSyEevOiVC7ZNQPrhKJgMhbVHcKuWj7v1cjOQEfkynJAqOjym R9o6kOdzMOK1i0iWI4vek966GU6Z/O4qlx0cu65lSFxT7RvxCTquXRrntpYF+h9tZpwe E8SD1g3lGTeKffFiawF2yeJILiypKbUGHbbptsUJF7aR+MUz3enpEV1xQtFG1sG7732M EnvA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=QwSZ8tNL; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Wed, 22 May 2019 11:20:38 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id x4MGKceB104536; Wed, 22 May 2019 11:20:38 -0500 From: Nishanth Menon To: Arnd Bergmann , Olof Johansson , Santosh Shilimkar , Will Deacon , Catalin Marinas , Greg Kroah-Hartman , Mark Rutland , Rob Herring CC: , , , , Tony Lindgren , Russell King , Tero Kristo , Nishanth Menon Subject: [PATCH 4/6] soc: ti: Add Support for J721E SoC config option Date: Wed, 22 May 2019 11:19:19 -0500 Message-ID: <20190522161921.20750-5-nm@ti.com> X-Mailer: git-send-email 2.21.0.777.g83232e38648b In-Reply-To: <20190522161921.20750-1-nm@ti.com> References: <20190522161921.20750-1-nm@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add option to build J721E SoC specific components Signed-off-by: Nishanth Menon --- drivers/soc/ti/Kconfig | 5 +++++ 1 file changed, 5 insertions(+) -- 2.21.0.777.g83232e38648b diff --git a/drivers/soc/ti/Kconfig b/drivers/soc/ti/Kconfig index dbd6c60b81db..a51beac6751f 100644 --- a/drivers/soc/ti/Kconfig +++ b/drivers/soc/ti/Kconfig @@ -8,6 +8,11 @@ config ARCH_K3_AM6_SOC help Enable support for TI's AM6 SoC Family support +config ARCH_K3_J721E_SOC + bool "K3 J721E SoC" + help + Enable support for TI's J721E SoC Family support + endif endif From patchwork Wed May 22 16:19:20 2019 Content-Type: text/plain; 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[209.132.180.67]) by mx.google.com with ESMTP id k5si8588855pll.53.2019.05.22.09.21.08; Wed, 22 May 2019 09:21:08 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=fhNn1wp8; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729588AbfEVQVH (ORCPT + 7 others); Wed, 22 May 2019 12:21:07 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:45622 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728638AbfEVQVH (ORCPT ); Wed, 22 May 2019 12:21:07 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x4MGKd5N073728; Wed, 22 May 2019 11:20:39 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1558542039; bh=QXG5XFuSCA/eKjm6eAz/ccN4peIXTQp3/Ud3QfKb6II=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=fhNn1wp8crWYJ6iDZgNwO2GuexbMHyGTxN8IiSUFy8sFhz/W+eLyLpWbXp/9wM7PD 7uKO72YIa5m2NnVkv/CA4AtRbukV8LigCUVocLtBPLDRRG9YM6AfRiB3njXUVZRqQW e8SD7cNCyG1sgQRmF4WGED8BCsB5CAHINy1VJduM= Received: from DLEE106.ent.ti.com (dlee106.ent.ti.com [157.170.170.36]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x4MGKdcQ103304 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 22 May 2019 11:20:39 -0500 Received: from DLEE110.ent.ti.com (157.170.170.21) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Wed, 22 May 2019 11:20:38 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Wed, 22 May 2019 11:20:38 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x4MGKc2P122874; Wed, 22 May 2019 11:20:38 -0500 From: Nishanth Menon To: Arnd Bergmann , Olof Johansson , Santosh Shilimkar , Will Deacon , Catalin Marinas , Greg Kroah-Hartman , Mark Rutland , Rob Herring CC: , , , , Tony Lindgren , Russell King , Tero Kristo , Nishanth Menon Subject: [PATCH 5/6] arm64: dts: ti: Add support for J721E Common Processor Board Date: Wed, 22 May 2019 11:19:20 -0500 Message-ID: <20190522161921.20750-6-nm@ti.com> X-Mailer: git-send-email 2.21.0.777.g83232e38648b In-Reply-To: <20190522161921.20750-1-nm@ti.com> References: <20190522161921.20750-1-nm@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add Support for J721E Common Processor board support. The EVM architecture is as follows: +------------------------------------------------------+ | +-------------------------------------------+ | | | | | | | Add-on Card 1 Options | | | | | | | +-------------------------------------------+ | | | | | | +-------------------+ | | | | | | | SOM | | | +--------------+ | | | | | | | | | | | Add-on | +-------------------+ | | | Card 2 | | Power Supply | | Options | | | | | | | | | +--------------+ | <--- +------------------------------------------------------+ Common Processor Board Common Processor board is the baseboard that has most of the actual connectors, power supply etc. A SOM (System on Module) is plugged on to the common processor board and this contains the SoC, PMIC, DDR and basic high speed components necessary for functionality. Add-n card options add further functionality (such as additional Audio, Display, networking options). Note: A) The minimum configuration required to boot up the board is System On Module(SOM) + Common Processor Board. B) Since there is just a single SOM and Common Processor Board, we are maintaining common processor board as the base dts and SOM as the dtsi that we include. In the future as more SOM's appear, we should move common processor board as a dtsi and include configurations as dts. C) All daughter cards beyond the basic boards shall be maintained as overlays. Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/Makefile | 2 + .../dts/ti/k3-j721e-common-proc-board.dts | 50 +++++++++++++++++++ arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 29 +++++++++++ 3 files changed, 81 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts create mode 100644 arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi -- 2.21.0.777.g83232e38648b diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 63e619d0b5b8..b397945fdf73 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -7,3 +7,5 @@ # dtb-$(CONFIG_ARCH_K3_AM6_SOC) += k3-am654-base-board.dtb + +dtb-$(CONFIG_ARCH_K3_J721E_SOC) += k3-j721e-common-proc-board.dtb diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts new file mode 100644 index 000000000000..c680123f067c --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; + +#include "k3-j721e-som-p0.dtsi" + +/ { + chosen { + stdout-path = "serial2:115200n8"; + bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000"; + }; +}; + +&wkup_uart0 { + /* Wakeup UART is used by System firmware */ + status = "disabled"; +}; + +&main_uart3 { + /* UART not brought out */ + status = "disabled"; +}; + +&main_uart5 { + /* UART not brought out */ + status = "disabled"; +}; + +&main_uart6 { + /* UART not brought out */ + status = "disabled"; +}; + +&main_uart7 { + /* UART not brought out */ + status = "disabled"; +}; + +&main_uart8 { + /* UART not brought out */ + status = "disabled"; +}; + +&main_uart9 { + /* UART not brought out */ + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi new file mode 100644 index 000000000000..1884fc70148f --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; + +#include "k3-j721e.dtsi" + +/ { + memory@80000000 { + device_type = "memory"; + /* 4G RAM */ + reg = <0x00000000 0x80000000 0x00000000 0x80000000>, + <0x00000008 0x80000000 0x00000000 0x80000000>; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + secure_ddr: optee@9e800000 { + reg = <0x00 0x9e800000 0x00 0x01800000>; + alignment = <0x1000>; + no-map; + }; + }; +};