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[83.9.3.225]) by smtp.gmail.com with ESMTPSA id f10-20020ac24e4a000000b004db3e330dcesm5008471lfr.178.2023.03.28.03.03.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Mar 2023 03:03:01 -0700 (PDT) From: Konrad Dybcio Date: Tue, 28 Mar 2023 12:02:52 +0200 Subject: [PATCH 1/2] dt-bindings: interrupt-controller: mpm: Allow passing reg through phandle MIME-Version: 1.0 Message-Id: <20230328-topic-msgram_mpm-v1-1-1b788a5f5a33@linaro.org> References: <20230328-topic-msgram_mpm-v1-0-1b788a5f5a33@linaro.org> In-Reply-To: <20230328-topic-msgram_mpm-v1-0-1b788a5f5a33@linaro.org> To: Andy Gross , Bjorn Andersson , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Shawn Guo Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1679997779; l=1381; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=C4N0Ev8VKX3zoI5LrzMOtOGVDcPvF0sVmEyLrmGffDM=; b=5VTz0TXYou6dESAd20JbdSqHQfvEqtSex/DVC7nsLbDDDFk1MRXmIhegfP3UUOj0Hwa28Li2VIg9 7jVFDEIBCvVhPHyP1gldQPvO0g3ZxbeD9i8Zi4xH2OVWQZcnicj1 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Due to the wild nature of the Qualcomm RPM Message RAM, we can't really use 'reg' to point to the MPM's slice of Message RAM without cutting into an already-defined RPM MSG RAM node used for GLINK and SMEM. Document passing the register space as a slice of SRAM through the qcom,rpm-msg-ram property. This also makes 'reg' no longer required. Signed-off-by: Konrad Dybcio --- .../devicetree/bindings/interrupt-controller/qcom,mpm.yaml | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,mpm.yaml b/Documentation/devicetree/bindings/interrupt-controller/qcom,mpm.yaml index 509d20c091af..77fe5e0b378f 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/qcom,mpm.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,mpm.yaml @@ -30,6 +30,11 @@ properties: description: Specifies the base address and size of vMPM registers in RPM MSG RAM. + qcom,rpm-msg-ram: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the APSS MPM slice of the RPM Message RAM + interrupts: maxItems: 1 description: @@ -64,7 +69,6 @@ properties: required: - compatible - - reg - interrupts - mboxes - interrupt-controller From patchwork Tue Mar 28 10:02:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 668229 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A7525C76196 for ; Tue, 28 Mar 2023 10:03:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231493AbjC1KDK (ORCPT ); Tue, 28 Mar 2023 06:03:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53600 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232832AbjC1KDG (ORCPT ); Tue, 28 Mar 2023 06:03:06 -0400 Received: from mail-lf1-x130.google.com (mail-lf1-x130.google.com [IPv6:2a00:1450:4864:20::130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E41EC618B for ; Tue, 28 Mar 2023 03:03:04 -0700 (PDT) Received: by mail-lf1-x130.google.com with SMTP id c9so4627592lfb.1 for ; Tue, 28 Mar 2023 03:03:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1679997783; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=Sl9kxXSw+Tz25eb85qCM7uxtmc76BHK03FRsB6nWKSE=; b=xqSEU/kqI0Diy4z4+MqEBldFOfHYnHjrn/VIcy+3OrcOcxOGBciCx4ARC7cjTGQupw hCWssqow5Tqz4t+ZlqXr1WHFFsx42NQoLKeOSwFlffd4Y9zrGCa4lYIWGuf68UZu61/c UgwEz0OZUDmXLkzceyoEi15VfMQCMsnihjZStKFER+zz3H6vGYYSPX0EFXCrVFmoEBpH YV75NCnqFqv5T+Dc54OkEgfToptxK9OB8Ea0r8JsGhDQkA/ztZmWY99+MQo1uPbwgB7p zqLcJnzzcxhN03+TSNChqJQSvw2PA4SWJiwEwLST55kJZj+bXdEvyQyzNrWr7KsQFDPC HUXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679997783; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Sl9kxXSw+Tz25eb85qCM7uxtmc76BHK03FRsB6nWKSE=; b=5DGVAB+E5zbctsoJiar0OHRWDnsh7D4nyxmW5pfnFT+uyWqgaSVAOY+ZcHqBR2WPVX jVUvmzvAj+Esn13rhwZQSKqTVeMdPjJYNAsx7d7IAUGOGfy/vHrHL/V3JdEfA5SSQw7G wxINjhWvB5QWxdXfcqBAZ0Q5aDJCZ0BPFbmqZBvP90c3gQg9UKV4WYsX/++/a5hErFxe s6b9PIX4nmr4xqjSH7dr64FuF8o9DntDlS7SbzxU32BmpMkKj6RlUNvtfMlAsIY5n2no X8IVKeZf2TakQTCINjza4K2KZiEuaFBw/V/UoRDd6Ke3MWRayMhGmAN8UqzFgWs8UyhO 9iYQ== X-Gm-Message-State: AAQBX9eYHF55bfPBRbos2V6xY7SHyK7sbFGqo88BsZvH3tu6l8iM4hwY lhnEP/5MQHham7zjIerSTxq+9A== X-Google-Smtp-Source: AKy350YMwE0ddyX51M/0yjHpBUptGp7dETGcgGbw3f2Xvu7upg2kzTEHZQUXY87LiX8lgJx8wcJJHQ== X-Received: by 2002:ac2:4f8d:0:b0:4e0:979d:56e8 with SMTP id z13-20020ac24f8d000000b004e0979d56e8mr4712169lfs.22.1679997783162; Tue, 28 Mar 2023 03:03:03 -0700 (PDT) Received: from [192.168.1.101] (abxj225.neoplus.adsl.tpnet.pl. [83.9.3.225]) by smtp.gmail.com with ESMTPSA id f10-20020ac24e4a000000b004db3e330dcesm5008471lfr.178.2023.03.28.03.03.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Mar 2023 03:03:02 -0700 (PDT) From: Konrad Dybcio Date: Tue, 28 Mar 2023 12:02:53 +0200 Subject: [PATCH 2/2] irqchip: irq-qcom-mpm: Support passing a slice of SRAM as reg space MIME-Version: 1.0 Message-Id: <20230328-topic-msgram_mpm-v1-2-1b788a5f5a33@linaro.org> References: <20230328-topic-msgram_mpm-v1-0-1b788a5f5a33@linaro.org> In-Reply-To: <20230328-topic-msgram_mpm-v1-0-1b788a5f5a33@linaro.org> To: Andy Gross , Bjorn Andersson , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Shawn Guo Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1679997779; l=3266; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=j53C+GXyNrDcAD6z2W1lAVzYENLhZdbwFZ4vxEDuGZ0=; b=7kBk95MhrZI4VdrM3PLJSqOqrg5k4VerCssvwUKsN3a3wwSN2HQpGfazNjS67qCZqX6v05Gnbbt5 0oAHWK3MBdG7T7VAurc9V+VPfvEqc7s/93tfWzENjWAcIpfw9SWj X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The MPM hardware is accessible to us from the ARM CPUs through a shared memory region (RPM MSG RAM) that's also concurrently accessed by other kinds of cores on the system (like modem, ADSP etc.). Modeling this relation in a (somewhat) sane manner in the device tree basically requires us to either present the MPM as a child of said memory region (which makes little sense, as a mapped memory carveout is not a bus), define nodes which bleed their register spaces into one another, or passing their slice of the MSG RAM through some kind of a property. Go with the third option and add a way to map a region passed through the "qcom,rpm-msg-ram" property as our register space. The current way of using 'reg' is preserved for ABI reasons. Signed-off-by: Konrad Dybcio --- drivers/irqchip/irq-qcom-mpm.c | 30 +++++++++++++++++++++++++----- 1 file changed, 25 insertions(+), 5 deletions(-) diff --git a/drivers/irqchip/irq-qcom-mpm.c b/drivers/irqchip/irq-qcom-mpm.c index d30614661eea..6fe59f4deef4 100644 --- a/drivers/irqchip/irq-qcom-mpm.c +++ b/drivers/irqchip/irq-qcom-mpm.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -322,8 +323,10 @@ static int qcom_mpm_init(struct device_node *np, struct device_node *parent) struct device *dev = &pdev->dev; struct irq_domain *parent_domain; struct generic_pm_domain *genpd; + struct device_node *msgram_np; struct qcom_mpm_priv *priv; unsigned int pin_cnt; + struct resource res; int i, irq; int ret; @@ -374,9 +377,21 @@ static int qcom_mpm_init(struct device_node *np, struct device_node *parent) raw_spin_lock_init(&priv->lock); - priv->base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(priv->base)) - return PTR_ERR(priv->base); + /* If we have a handle to an RPM message ram partition, use it. */ + msgram_np = of_parse_phandle(np, "qcom,rpm-msg-ram", 0); + if (msgram_np) { + ret = of_address_to_resource(msgram_np, 0, &res); + /* Don't use devm_ioremap_resource, as we're accessing a shared region. */ + priv->base = ioremap(res.start, resource_size(&res)); + of_node_put(msgram_np); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + } else { + /* Otherwise, fall back to simple MMIO. */ + priv->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + } for (i = 0; i < priv->reg_stride; i++) { qcom_mpm_write(priv, MPM_REG_ENABLE, i, 0); @@ -387,8 +402,10 @@ static int qcom_mpm_init(struct device_node *np, struct device_node *parent) } irq = platform_get_irq(pdev, 0); - if (irq < 0) - return irq; + if (irq < 0) { + ret = irq; + goto unmap_base; + } genpd = &priv->genpd; genpd->flags = GENPD_FLAG_IRQ_SAFE; @@ -451,6 +468,9 @@ static int qcom_mpm_init(struct device_node *np, struct device_node *parent) mbox_free_channel(priv->mbox_chan); remove_genpd: pm_genpd_remove(genpd); +unmap_base: + if (res.start) + iounmap(priv->base); return ret; }