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Tue, 28 Mar 2023 10:31:26 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Halil Pasic , David Gibson , Daniel Henrique Barboza , qemu-ppc@nongnu.org, Yanan Wang , David Hildenbrand , Christian Borntraeger , Eduardo Habkost , Paolo Bonzini , Marcel Apfelbaum , Greg Kurz , kvm@vger.kernel.org, Ilya Leoshkevich , Peter Maydell , Fabiano Rosas , =?utf-8?q?Alex_Benn=C3=A9e?= , Thomas Huth , Richard Henderson , qemu-s390x@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?C?= =?utf-8?q?=C3=A9dric_Le_Goater?= Subject: [PATCH-for-8.0 v2 1/3] softmmu: Restrict cpu_check_watchpoint / address_matches to TCG accel Date: Tue, 28 Mar 2023 19:31:15 +0200 Message-Id: <20230328173117.15226-2-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230328173117.15226-1-philmd@linaro.org> References: <20230328173117.15226-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=philmd@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Both cpu_check_watchpoint() and cpu_watchpoint_address_matches() are specific to TCG system emulation. Declare them in "tcg-cpu-ops.h" to be sure accessing them from non-TCG code is a compilation error. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Fabiano Rosas --- include/hw/core/cpu.h | 37 ------------------------------ include/hw/core/tcg-cpu-ops.h | 43 +++++++++++++++++++++++++++++++++++ target/arm/tcg/mte_helper.c | 1 + target/arm/tcg/sve_helper.c | 1 + target/s390x/tcg/mem_helper.c | 1 + 5 files changed, 46 insertions(+), 37 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 821e937020..ce312745d5 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -970,17 +970,6 @@ static inline void cpu_watchpoint_remove_by_ref(CPUState *cpu, static inline void cpu_watchpoint_remove_all(CPUState *cpu, int mask) { } - -static inline void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len, - MemTxAttrs atr, int fl, uintptr_t ra) -{ -} - -static inline int cpu_watchpoint_address_matches(CPUState *cpu, - vaddr addr, vaddr len) -{ - return 0; -} #else int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, int flags, CPUWatchpoint **watchpoint); @@ -988,32 +977,6 @@ int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len, int flags); void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint); void cpu_watchpoint_remove_all(CPUState *cpu, int mask); - -/** - * cpu_check_watchpoint: - * @cpu: cpu context - * @addr: guest virtual address - * @len: access length - * @attrs: memory access attributes - * @flags: watchpoint access type - * @ra: unwind return address - * - * Check for a watchpoint hit in [addr, addr+len) of the type - * specified by @flags. Exit via exception with a hit. - */ -void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len, - MemTxAttrs attrs, int flags, uintptr_t ra); - -/** - * cpu_watchpoint_address_matches: - * @cpu: cpu context - * @addr: guest virtual address - * @len: access length - * - * Return the watchpoint flags that apply to [addr, addr+len). - * If no watchpoint is registered for the range, the result is 0. - */ -int cpu_watchpoint_address_matches(CPUState *cpu, vaddr addr, vaddr len); #endif /** diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index 20e3c0ffbb..0ae08df47e 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -175,4 +175,47 @@ struct TCGCPUOps { }; +#if defined(CONFIG_USER_ONLY) + +static inline void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len, + MemTxAttrs atr, int fl, uintptr_t ra) +{ +} + +static inline int cpu_watchpoint_address_matches(CPUState *cpu, + vaddr addr, vaddr len) +{ + return 0; +} + +#else + +/** + * cpu_check_watchpoint: + * @cpu: cpu context + * @addr: guest virtual address + * @len: access length + * @attrs: memory access attributes + * @flags: watchpoint access type + * @ra: unwind return address + * + * Check for a watchpoint hit in [addr, addr+len) of the type + * specified by @flags. Exit via exception with a hit. + */ +void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len, + MemTxAttrs attrs, int flags, uintptr_t ra); + +/** + * cpu_watchpoint_address_matches: + * @cpu: cpu context + * @addr: guest virtual address + * @len: access length + * + * Return the watchpoint flags that apply to [addr, addr+len). + * If no watchpoint is registered for the range, the result is 0. + */ +int cpu_watchpoint_address_matches(CPUState *cpu, vaddr addr, vaddr len); + +#endif + #endif /* TCG_CPU_OPS_H */ diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c index fee3c7eb96..a4f3f92bc0 100644 --- a/target/arm/tcg/mte_helper.c +++ b/target/arm/tcg/mte_helper.c @@ -25,6 +25,7 @@ #include "exec/ram_addr.h" #include "exec/cpu_ldst.h" #include "exec/helper-proto.h" +#include "hw/core/tcg-cpu-ops.h" #include "qapi/error.h" #include "qemu/guest-random.h" diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c index 9a8951afa4..ccf5e5beca 100644 --- a/target/arm/tcg/sve_helper.c +++ b/target/arm/tcg/sve_helper.c @@ -27,6 +27,7 @@ #include "tcg/tcg.h" #include "vec_internal.h" #include "sve_ldst_internal.h" +#include "hw/core/tcg-cpu-ops.h" /* Return a value for NZCV as per the ARM PredTest pseudofunction. diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index b93dbd3dad..8b58b8d88d 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -26,6 +26,7 @@ #include "exec/helper-proto.h" #include "exec/exec-all.h" #include "exec/cpu_ldst.h" +#include "hw/core/tcg-cpu-ops.h" #include "qemu/int128.h" #include "qemu/atomic128.h" #include "trace.h" From patchwork Tue Mar 28 17:31:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 667869 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d08:0:0:0:0:0 with SMTP id z8csp1799340wrt; Tue, 28 Mar 2023 10:32:38 -0700 (PDT) X-Google-Smtp-Source: AKy350biYArH9Fo+93CwWuIS9wPthbu3Zu6rqd80+f9v/QfbxVvcesStgcd7rg1f9cG56AOQMlKl X-Received: by 2002:a05:622a:5cf:b0:3e3:8ed5:a475 with SMTP id d15-20020a05622a05cf00b003e38ed5a475mr28863149qtb.47.1680024758016; Tue, 28 Mar 2023 10:32:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680024758; cv=none; d=google.com; s=arc-20160816; b=dpml6hZ578oDiGr7wGY/6ifd3+l5jz1/yYQrRrit/YtpXrBaNcBVfd+o7Ymfgc2ntE os7CxcXBbtAiz+mAMV5vwONeUAErKZ1C4jJ4Q+Cp+pMY4rLJMlPhPX10EmRb7mvvpTGP qdkdhIotzUKNd46vxx6EbzxOgh8Bu3I4awWqWPbSWBbUMREFlwd23VFQlIrDx4gWzv/F igAOPjOAULDcCSouqDi0L/vQWXXzj4A0Kq+bN+18H9W/Og21I2LyqLdq0/k4o6VNRJEr Xnd5gPRUftzN6SvWOOxaVnlovO8jUhNduyK3Png1sbMiTpFscZCBj7cRQK/MsYSWnBEP ewGg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=dtiprwlUv8RpyZHXqJVAug6oqdjSRp6/2zuWFlQJTRs=; b=o3rIGBhCEMkVtnfMPx572+XmBlHPz4VNL35Thpg+DkGaisO8zb1XRi7zPWrkRPu4Rs mk5Ushr07DZJn4cPothKs+iWRyz18Wvz3wVC0yoJevP3ys8dGoScyVVgR+g4nW3swIs8 dOJOaU1eML+me+QQIaMUczobOpojMt61BstNzeibeh8MvnDf0vs+EdFr046Z5GKMgaxf LSIvTDkgxv3HLo6pB8xqHZrMTpnUaZ7MiOrABsgymcFpsfJd+QWmwraZU1zW9AEPfUK6 R8X46h6nuggAEi/Ofk7gXo6mg0hZPpmixjiwsjXf9x37EGjtvkKRC/SZoBMbfNHC2DAp 02KQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jRrDLlb5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Tue, 28 Mar 2023 10:31:32 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Halil Pasic , David Gibson , Daniel Henrique Barboza , qemu-ppc@nongnu.org, Yanan Wang , David Hildenbrand , Christian Borntraeger , Eduardo Habkost , Paolo Bonzini , Marcel Apfelbaum , Greg Kurz , kvm@vger.kernel.org, Ilya Leoshkevich , Peter Maydell , Fabiano Rosas , =?utf-8?q?Alex_Benn=C3=A9e?= , Thomas Huth , Richard Henderson , qemu-s390x@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?C?= =?utf-8?q?=C3=A9dric_Le_Goater?= Subject: [PATCH-for-8.0 v2 2/3] softmmu/watchpoint: Add missing 'qemu/error-report.h' include Date: Tue, 28 Mar 2023 19:31:16 +0200 Message-Id: <20230328173117.15226-3-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230328173117.15226-1-philmd@linaro.org> References: <20230328173117.15226-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=philmd@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org cpu_watchpoint_insert() calls error_report() which is declared in "qemu/error-report.h". When moving this code in commit 2609ec2868 ("softmmu: Extract watchpoint API from physmem.c") we neglected to include this header. This works so far because it is indirectly included by TCG headers -> "qemu/plugin.h" -> "qemu/error-report.h". Currently cpu_watchpoint_insert() is only built with the TCG accelerator. When building it with other ones (or without TCG) we get: softmmu/watchpoint.c:38:9: error: implicit declaration of function 'error_report' is invalid in C99 [-Werror,-Wimplicit-function-declaration] error_report("tried to set invalid watchpoint at %" ^ Include "qemu/error-report.h" in order to fix this for non-TCG builds. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Fabiano Rosas --- softmmu/watchpoint.c | 1 + 1 file changed, 1 insertion(+) diff --git a/softmmu/watchpoint.c b/softmmu/watchpoint.c index ad58736787..9d6ae68499 100644 --- a/softmmu/watchpoint.c +++ b/softmmu/watchpoint.c @@ -19,6 +19,7 @@ #include "qemu/osdep.h" #include "qemu/main-loop.h" +#include "qemu/error-report.h" #include "exec/exec-all.h" #include "exec/translate-all.h" #include "sysemu/tcg.h" From patchwork Tue Mar 28 17:31:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 667871 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d08:0:0:0:0:0 with SMTP id z8csp1799524wrt; Tue, 28 Mar 2023 10:32:59 -0700 (PDT) X-Google-Smtp-Source: AKy350aNCWXcDuPpFMchw0n9itb8X+me5AV0qWSXh76pMNxU5ZPEB1njxHq0/q7WTem9rH/pOYOx X-Received: by 2002:ac8:5c8e:0:b0:3e4:e79c:55e0 with SMTP id r14-20020ac85c8e000000b003e4e79c55e0mr14551788qta.8.1680024779235; Tue, 28 Mar 2023 10:32:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680024779; cv=none; d=google.com; s=arc-20160816; b=ZsAnFfRU0eQTajbZkk8gK9ZgPO7Ro6iWXBlhQb5ePJ7YDULDQy2WLoBv2w4HKSyyZU aAcLSWOWRVceibwBCPnGI1T9m/mvcCk2MiVpV9H5v05X+gKYFQIIuinbKLiWLtYOpGtP u5eUt3FQSweDgLQTWFvRXS+FgpZLiSn4Z/mqx1CFnrLe164Fiz/e7EMM37rV/oIwrGQU iH1LursHo0ANxpQx3QNFgBEOBTzLJLnEWQkVJgac95F5mMJtWcGWQq5bxrWlhkU+iazX cqLec4E4tfd8dxnIHzY0ajGkeddeKuaUvyqcQecHn3CZpawBOVQf3vqgDvaE4TWK9ZO+ ZWjQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=6MbnN+0f617dsehwYtlh7IWt8dwxE1cjBMBOmowF/jo=; b=PXI2uWNckmLJV6rJAgmnWhsNeq3HiYZxv3NWNTngjo8GohkMDARn+JvZOAkbGwN9DZ srLQ3ZMZUHMUlEHcRGzan5kLcygW4hagHvh2TuXdGuLCXNzOz8FcZXXN+A3AdoLy+zHa bVlMibdo3P58GJ/u6Z/dNfoVrIf3yn7NhLbXaQP4dXwa2SAL3GMVW4oKcVptdPTCVHrk 3kGITy+XCu0FUcFv0q+rasxSyvd2APCqOG0z7+Y9hoTxs3+yeiqlfsRy+MBFSFYlLidb RyEla8A3oeNLZpES1Sumj33gMkrCLvEa20o52BEaF7JyknjlHdod25HstgSeGv8/1WH4 YYpQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Vi8NBOJN; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Tue, 28 Mar 2023 10:31:39 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Halil Pasic , David Gibson , Daniel Henrique Barboza , qemu-ppc@nongnu.org, Yanan Wang , David Hildenbrand , Christian Borntraeger , Eduardo Habkost , Paolo Bonzini , Marcel Apfelbaum , Greg Kurz , kvm@vger.kernel.org, Ilya Leoshkevich , Peter Maydell , Fabiano Rosas , =?utf-8?q?Alex_Benn=C3=A9e?= , Thomas Huth , Richard Henderson , qemu-s390x@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?C?= =?utf-8?q?=C3=A9dric_Le_Goater?= Subject: [PATCH-for-8.0 v2 3/3] softmmu: Restore use of CPU watchpoint for all accelerators Date: Tue, 28 Mar 2023 19:31:17 +0200 Message-Id: <20230328173117.15226-4-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230328173117.15226-1-philmd@linaro.org> References: <20230328173117.15226-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org CPU watchpoints can be use by non-TCG accelerators. KVM uses them: $ git grep CPUWatchpoint|fgrep kvm target/arm/kvm64.c:1558: CPUWatchpoint *wp = find_hw_watchpoint(cs, debug_exit->far); target/i386/kvm/kvm.c:5216:static CPUWatchpoint hw_watchpoint; target/ppc/kvm.c:443:static CPUWatchpoint hw_watchpoint; target/s390x/kvm/kvm.c:139:static CPUWatchpoint hw_watchpoint; See for example commit e4482ab7e3 ("target-arm: kvm - add support for HW assisted debug"): This adds basic support for HW assisted debug. The ioctl interface to KVM allows us to pass an implementation defined number of break and watch point registers. [...] This partially reverts commit 2609ec2868e6c286e755a73b4504714a0296a. Fixes: 2609ec2868 ("softmmu: Extract watchpoint API from physmem.c") Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Fabiano Rosas --- include/hw/core/cpu.h | 2 +- softmmu/watchpoint.c | 4 ++++ softmmu/meson.build | 2 +- 3 files changed, 6 insertions(+), 2 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index ce312745d5..397fd3ac68 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -949,7 +949,7 @@ static inline bool cpu_breakpoint_test(CPUState *cpu, vaddr pc, int mask) return false; } -#if !defined(CONFIG_TCG) || defined(CONFIG_USER_ONLY) +#if defined(CONFIG_USER_ONLY) static inline int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, int flags, CPUWatchpoint **watchpoint) { diff --git a/softmmu/watchpoint.c b/softmmu/watchpoint.c index 9d6ae68499..5350163385 100644 --- a/softmmu/watchpoint.c +++ b/softmmu/watchpoint.c @@ -104,6 +104,8 @@ void cpu_watchpoint_remove_all(CPUState *cpu, int mask) } } +#ifdef CONFIG_TCG + /* * Return true if this watchpoint address matches the specified * access (ie the address range covered by the watchpoint overlaps @@ -220,3 +222,5 @@ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len, } } } + +#endif /* CONFIG_TCG */ diff --git a/softmmu/meson.build b/softmmu/meson.build index 0180577517..1a7c7ac089 100644 --- a/softmmu/meson.build +++ b/softmmu/meson.build @@ -5,11 +5,11 @@ specific_ss.add(when: 'CONFIG_SOFTMMU', if_true: [files( 'physmem.c', 'qtest.c', 'dirtylimit.c', + 'watchpoint.c', )]) specific_ss.add(when: ['CONFIG_SOFTMMU', 'CONFIG_TCG'], if_true: [files( 'icount.c', - 'watchpoint.c', )]) softmmu_ss.add(files(