From patchwork Mon Mar 27 03:13:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Moudy Ho X-Patchwork-Id: 667735 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 739FFC74A5B for ; Mon, 27 Mar 2023 03:14:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232109AbjC0DOd (ORCPT ); Sun, 26 Mar 2023 23:14:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49020 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232180AbjC0DN7 (ORCPT ); Sun, 26 Mar 2023 23:13:59 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 375964EF8; Sun, 26 Mar 2023 20:13:46 -0700 (PDT) X-UUID: 5dedcab8cc4d11edb6b9f13eb10bd0fe-20230327 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=O8crC6JDN1PDEzgJDHyrRI9+0OjAu60qsAfWD7/5X4k=; b=AcWWF9n3+0l0/h3Q6BfVnQHz8Gk7XOnazVDM82CGFzJkGWdBnUdiZNxzaZ9+2PJ4ku8dpOxXsy6Mbz0WuqxEseNGehanNv0L8+X5d4vBjpfGsKJBzr/VeSPPw+4o50GamCgu/JVpoDpvpBP4qM9dicC7rakGIZLuQfkeq/GLoCg=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.22, REQID:0a4f5521-33da-451f-aa39-c32e202670cb, IP:0, U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTI ON:release,TS:70 X-CID-INFO: VERSION:1.1.22, REQID:0a4f5521-33da-451f-aa39-c32e202670cb, IP:0, URL :0,TC:0,Content:-25,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTI ON:quarantine,TS:70 X-CID-META: VersionHash:120426c, CLOUDID:baf870b4-beed-4dfc-bd9c-e1b22fa6ccc4, B ulkID:23032711134027KRD96O,BulkQuantity:0,Recheck:0,SF:38|29|28|17|19|48,T C:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 ,OSI:0,OSA:0,AV:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-UUID: 5dedcab8cc4d11edb6b9f13eb10bd0fe-20230327 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 41898669; Mon, 27 Mar 2023 11:13:37 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.25; Mon, 27 Mar 2023 11:13:36 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.25 via Frontend Transport; Mon, 27 Mar 2023 11:13:36 +0800 From: Moudy Ho To: Mauro Carvalho Chehab , Matthias Brugger , Hans Verkuil , Ping-Hsun Wu CC: , , , , , Moudy Ho Subject: [PATCH v7 04/12] media: platform: mtk-mdp3: chip config split about subcomponents Date: Mon, 27 Mar 2023 11:13:27 +0800 Message-ID: <20230327031335.9663-5-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230327031335.9663-1-moudy.ho@mediatek.com> References: <20230327031335.9663-1-moudy.ho@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Integrate subcomponent related information into specific config file for further multi-chip compatibility. Signed-off-by: Moudy Ho --- .../media/platform/mediatek/mdp3/mdp_cfg_data.c | 12 ++++++++++++ .../media/platform/mediatek/mdp3/mtk-mdp3-comp.c | 14 ++------------ .../media/platform/mediatek/mdp3/mtk-mdp3-core.h | 1 + 3 files changed, 15 insertions(+), 12 deletions(-) diff --git a/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c b/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c index 4bf721957937..82e2e690a767 100644 --- a/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c +++ b/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c @@ -144,12 +144,24 @@ static const struct mdp_comp_data mt8183_mdp_comp_data[MDP_MAX_COMP_COUNT] = { }, }; +static const struct of_device_id mt8183_sub_comp_dt_ids[] = { + { + .compatible = "mediatek,mt8183-mdp3-wdma", + .data = (void *)MDP_COMP_TYPE_PATH, + }, { + .compatible = "mediatek,mt8183-mdp3-wrot", + .data = (void *)MDP_COMP_TYPE_PATH, + }, + {} +}; + const struct mtk_mdp_driver_data mt8183_mdp_driver_data = { .mdp_probe_infra = mt8183_mdp_probe_infra, .mdp_cfg = &mt8183_plat_cfg, .mdp_mutex_table_idx = mt8183_mutex_idx, .comp_data = mt8183_mdp_comp_data, .comp_data_len = ARRAY_SIZE(mt8183_mdp_comp_data), + .mdp_sub_comp_dt_ids = mt8183_sub_comp_dt_ids, }; s32 mdp_cfg_get_id_inner(struct mdp_dev *mdp_dev, enum mtk_mdp_comp_id id) diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c index 86aa031789d6..49bfe0094b19 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c @@ -610,17 +610,6 @@ static const struct of_device_id mdp_comp_dt_ids[] = { {} }; -static const struct of_device_id mdp_sub_comp_dt_ids[] = { - { - .compatible = "mediatek,mt8183-mdp3-wdma", - .data = (void *)MDP_COMP_TYPE_PATH, - }, { - .compatible = "mediatek,mt8183-mdp3-wrot", - .data = (void *)MDP_COMP_TYPE_PATH, - }, - {} -}; - static inline bool is_dma_capable(const enum mdp_comp_type type) { return (type == MDP_COMP_TYPE_RDMA || @@ -871,6 +860,7 @@ static int mdp_comp_sub_create(struct mdp_dev *mdp) { struct device *dev = &mdp->pdev->dev; struct device_node *node, *parent; + const struct mtk_mdp_driver_data *data = mdp->mdp_data; parent = dev->of_node->parent; @@ -880,7 +870,7 @@ static int mdp_comp_sub_create(struct mdp_dev *mdp) int id, alias_id; struct mdp_comp *comp; - of_id = of_match_node(mdp_sub_comp_dt_ids, node); + of_id = of_match_node(data->mdp_sub_comp_dt_ids, node); if (!of_id) continue; if (!of_device_is_available(node)) { diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h index 0c398ef75616..41eeba49fb42 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h @@ -56,6 +56,7 @@ struct mtk_mdp_driver_data { const u32 *mdp_mutex_table_idx; const struct mdp_comp_data *comp_data; unsigned int comp_data_len; + const struct of_device_id *mdp_sub_comp_dt_ids; }; struct mdp_dev { From patchwork Mon Mar 27 03:13:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Moudy Ho X-Patchwork-Id: 667738 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5D465C74A5B for ; Mon, 27 Mar 2023 03:14:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232186AbjC0DOC (ORCPT ); Sun, 26 Mar 2023 23:14:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48694 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232192AbjC0DNz (ORCPT ); Sun, 26 Mar 2023 23:13:55 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 95F285252; Sun, 26 Mar 2023 20:13:41 -0700 (PDT) X-UUID: 5e2235a0cc4d11eda9a90f0bb45854f4-20230327 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=37feK4H352MLzFfVmA6c0Q9gaAVyebOImg/IcUbn+wg=; b=JqvkGLJnGEiiwAHKz0hc+b0fhdlFQ81S6lwr4iZbv6JDeTXNI35tJErNQfsIrhzLxGC/iYTNsovxRKswzwDJZ5LvMVaPAsp9XrQsNTFipcgHg2bMSRTkHfXd4RMz7FSuAuFemeguP6Dq5Se8fAlHy5o6n6YFAex43fHqB6OO05c=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.22, REQID:85967be7-b793-4126-906c-b54174f8e003, IP:0, U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-25 X-CID-META: VersionHash:120426c, CLOUDID:b4d38f29-564d-42d9-9875-7c868ee415ec, B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-UUID: 5e2235a0cc4d11eda9a90f0bb45854f4-20230327 Received: from mtkmbs13n2.mediatek.inc [(172.21.101.108)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1999047032; Mon, 27 Mar 2023 11:13:38 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.25; Mon, 27 Mar 2023 11:13:36 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.25 via Frontend Transport; Mon, 27 Mar 2023 11:13:36 +0800 From: Moudy Ho To: Mauro Carvalho Chehab , Matthias Brugger , Hans Verkuil , Ping-Hsun Wu CC: , , , , , Moudy Ho Subject: [PATCH v7 06/12] media: platform: mtk-mdp3: chip config split about resolution limitations Date: Mon, 27 Mar 2023 11:13:29 +0800 Message-ID: <20230327031335.9663-7-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230327031335.9663-1-moudy.ho@mediatek.com> References: <20230327031335.9663-1-moudy.ho@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Due to differences in hardware design, the supported max and min resolutions and scaling capabilities will vary, and should be integrated into specific config file. Signed-off-by: Moudy Ho --- .../platform/mediatek/mdp3/mdp_cfg_data.c | 20 ++++++++++++++++++ .../platform/mediatek/mdp3/mtk-mdp3-core.h | 1 + .../platform/mediatek/mdp3/mtk-mdp3-m2m.c | 5 +++-- .../platform/mediatek/mdp3/mtk-mdp3-regs.c | 21 +------------------ 4 files changed, 25 insertions(+), 22 deletions(-) diff --git a/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c b/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c index 46c005b7447f..1769bce2871e 100644 --- a/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c +++ b/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c @@ -381,6 +381,25 @@ static const struct mdp_format mt8183_formats[] = { } }; +static const struct mdp_limit mt8183_mdp_def_limit = { + .out_limit = { + .wmin = 16, + .hmin = 16, + .wmax = 8176, + .hmax = 8176, + }, + .cap_limit = { + .wmin = 2, + .hmin = 2, + .wmax = 8176, + .hmax = 8176, + }, + .h_scale_up_max = 32, + .v_scale_up_max = 32, + .h_scale_down_max = 20, + .v_scale_down_max = 128, +}; + const struct mtk_mdp_driver_data mt8183_mdp_driver_data = { .mdp_probe_infra = mt8183_mdp_probe_infra, .mdp_cfg = &mt8183_plat_cfg, @@ -390,6 +409,7 @@ const struct mtk_mdp_driver_data mt8183_mdp_driver_data = { .mdp_sub_comp_dt_ids = mt8183_sub_comp_dt_ids, .format = mt8183_formats, .format_len = ARRAY_SIZE(mt8183_formats), + .def_limit = &mt8183_mdp_def_limit, }; s32 mdp_cfg_get_id_inner(struct mdp_dev *mdp_dev, enum mtk_mdp_comp_id id) diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h index 327da00dd1fc..a312c1007e96 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h @@ -59,6 +59,7 @@ struct mtk_mdp_driver_data { const struct of_device_id *mdp_sub_comp_dt_ids; const struct mdp_format *format; unsigned int format_len; + const struct mdp_limit *def_limit; }; struct mdp_dev { diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-m2m.c b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-m2m.c index f708fca228a7..27e1b1b8c6b4 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-m2m.c +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-m2m.c @@ -558,6 +558,7 @@ static int mdp_m2m_open(struct file *file) struct device *dev = &mdp->pdev->dev; int ret; struct v4l2_format default_format = {}; + const struct mdp_limit *limit = mdp->mdp_data->def_limit; ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); if (!ctx) @@ -605,8 +606,8 @@ static int mdp_m2m_open(struct file *file) /* Default format */ default_format.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; - default_format.fmt.pix_mp.width = 32; - default_format.fmt.pix_mp.height = 32; + default_format.fmt.pix_mp.width = limit->out_limit.wmin; + default_format.fmt.pix_mp.height = limit->out_limit.hmin; default_format.fmt.pix_mp.pixelformat = V4L2_PIX_FMT_YUV420M; mdp_m2m_s_fmt_mplane(file, &ctx->fh, &default_format); default_format.type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-regs.c b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-regs.c index c6fecb089687..9b436b911d92 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-regs.c +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-regs.c @@ -12,25 +12,6 @@ #include "mtk-mdp3-regs.h" #include "mtk-mdp3-m2m.h" -static const struct mdp_limit mdp_def_limit = { - .out_limit = { - .wmin = 16, - .hmin = 16, - .wmax = 8176, - .hmax = 8176, - }, - .cap_limit = { - .wmin = 2, - .hmin = 2, - .wmax = 8176, - .hmax = 8176, - }, - .h_scale_up_max = 32, - .v_scale_up_max = 32, - .h_scale_down_max = 20, - .v_scale_down_max = 128, -}; - static const struct mdp_format *mdp_find_fmt(const struct mtk_mdp_driver_data *mdp_data, u32 pixelformat, u32 type) { @@ -487,7 +468,7 @@ int mdp_frameparam_init(struct mdp_dev *mdp, struct mdp_frameparam *param) return -EINVAL; INIT_LIST_HEAD(¶m->list); - param->limit = &mdp_def_limit; + param->limit = mdp->mdp_data->def_limit; param->type = MDP_STREAM_TYPE_BITBLT; frame = ¶m->output; From patchwork Mon Mar 27 03:13:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Moudy Ho X-Patchwork-Id: 667734 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9CCCFC77B6C for ; Mon, 27 Mar 2023 03:14:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232237AbjC0DOh (ORCPT ); Sun, 26 Mar 2023 23:14:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48678 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230020AbjC0DOA (ORCPT ); Sun, 26 Mar 2023 23:14:00 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5B9515249; Sun, 26 Mar 2023 20:13:47 -0700 (PDT) X-UUID: 5d9ad646cc4d11edb6b9f13eb10bd0fe-20230327 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=WByBskY3OQfVkoYwoTQ6lsScT1N3NV3SSj3FxZ7ZqV8=; b=lI5EF5e5wyQb/6jshQlVsBacEelYgGo5iPygo6u6UkTSDQLDQ6Nef+x9yargOx5sxod+/90H9zrTdGTjyVLDbHMsrBP563ih7m2mvjvWFz1r+Kvkzj0ShFoExda8u2Ue05EX25LOH0wsxUHdTZolzcwq4sQUg+FAdUNt/VG4Z2E=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.22, REQID:6311defb-813f-495f-ba22-eae2e6493b14, IP:0, U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:95 X-CID-INFO: VERSION:1.1.22, REQID:6311defb-813f-495f-ba22-eae2e6493b14, IP:0, URL :0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTION :quarantine,TS:95 X-CID-META: VersionHash:120426c, CLOUDID:bcf870b4-beed-4dfc-bd9c-e1b22fa6ccc4, B ulkID:230327111340F3DP9NF4,BulkQuantity:0,Recheck:0,SF:38|29|28|17|19|48,T C:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 ,OSI:0,OSA:0,AV:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-UUID: 5d9ad646cc4d11edb6b9f13eb10bd0fe-20230327 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1861320625; Mon, 27 Mar 2023 11:13:37 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.25; Mon, 27 Mar 2023 11:13:36 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.25 via Frontend Transport; Mon, 27 Mar 2023 11:13:36 +0800 From: Moudy Ho To: Mauro Carvalho Chehab , Matthias Brugger , Hans Verkuil , "Ping-Hsun Wu" CC: , , , , , Moudy Ho Subject: [PATCH v7 07/12] media: platform: mtk-mdp3: chip config split about pipe info Date: Mon, 27 Mar 2023 11:13:30 +0800 Message-ID: <20230327031335.9663-8-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230327031335.9663-1-moudy.ho@mediatek.com> References: <20230327031335.9663-1-moudy.ho@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org In MDP3, a pipe is used to represent a data path which consisting of different components and MUTEX, as shown in the following diagram: +----------------------------+ | MUTEX [*1] | +----------------------------+ S ^ S ^ S ^ S ^ S ^ | | | | | | | | | | | | | | | | | | | | +--------------+ | | | | | | | | +-------------+ | +--------------+ | | | | | | +-------------+ | | | +------+ | | | | +------+ | | | | | +------+ | | +------+ | | | | | | | | | | | | | | | | | | | | | | | v E v E v E v E v E +-------+ +-----+ +-------+ +-----+ +-------+ B>--->| RDMA0 |>-->| PQ |>-->| RSZ0 |>-->| PQ |>-->| WROT0 |>-->B +-------+ +-----+ +-------+ +-----+ +-------+ [*1] MUTEX is SOF/EOF signal controller [*2] S = Start of frame (SOF) [*3] E = End of frame (EOF) [*4] B = frame buffer More pipes will be introduced in future chips for applications such as higher frame rate frequency, which should integrate and reorder related information into specific chip config file. Signed-off-by: Moudy Ho --- .../platform/mediatek/mdp3/mdp_cfg_data.c | 9 ++++++++ .../platform/mediatek/mdp3/mtk-mdp3-cmdq.c | 23 ++++++++++++------- .../platform/mediatek/mdp3/mtk-mdp3-core.c | 15 +++++++----- .../platform/mediatek/mdp3/mtk-mdp3-core.h | 11 +++++++-- 4 files changed, 42 insertions(+), 16 deletions(-) diff --git a/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c b/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c index 1769bce2871e..cf97ba70fddd 100644 --- a/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c +++ b/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c @@ -400,6 +400,13 @@ static const struct mdp_limit mt8183_mdp_def_limit = { .v_scale_down_max = 128, }; +static const struct mdp_pipe_info mt8183_pipe_info[] = { + [MDP_PIPE_WPEI] = {MDP_PIPE_WPEI, 0}, + [MDP_PIPE_WPEI2] = {MDP_PIPE_WPEI2, 1}, + [MDP_PIPE_IMGI] = {MDP_PIPE_IMGI, 2}, + [MDP_PIPE_RDMA0] = {MDP_PIPE_RDMA0, 3} +}; + const struct mtk_mdp_driver_data mt8183_mdp_driver_data = { .mdp_probe_infra = mt8183_mdp_probe_infra, .mdp_cfg = &mt8183_plat_cfg, @@ -410,6 +417,8 @@ const struct mtk_mdp_driver_data mt8183_mdp_driver_data = { .format = mt8183_formats, .format_len = ARRAY_SIZE(mt8183_formats), .def_limit = &mt8183_mdp_def_limit, + .pipe_info = mt8183_pipe_info, + .pipe_info_len = ARRAY_SIZE(mt8183_pipe_info), }; s32 mdp_cfg_get_id_inner(struct mdp_dev *mdp_dev, enum mtk_mdp_comp_id id) diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c index dcd77f65b0e3..bff14e4944c5 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c @@ -50,21 +50,22 @@ static int mdp_path_subfrm_require(const struct mdp_path *path, /* Decide which mutex to use based on the current pipeline */ switch (path->comps[0].comp->public_id) { case MDP_COMP_RDMA0: - *mutex_id = MDP_PIPE_RDMA0; + index = MDP_PIPE_RDMA0; break; case MDP_COMP_ISP_IMGI: - *mutex_id = MDP_PIPE_IMGI; + index = MDP_PIPE_IMGI; break; case MDP_COMP_WPEI: - *mutex_id = MDP_PIPE_WPEI; + index = MDP_PIPE_WPEI; break; case MDP_COMP_WPEI2: - *mutex_id = MDP_PIPE_WPEI2; + index = MDP_PIPE_WPEI2; break; default: dev_err(dev, "Unknown pipeline and no mutex is assigned"); return -EINVAL; } + *mutex_id = data->pipe_info[index].mutex_id; /* Set mutex mod */ for (index = 0; index < config->num_components; index++) { @@ -286,11 +287,13 @@ static void mdp_auto_release_work(struct work_struct *work) { struct mdp_cmdq_cmd *cmd; struct mdp_dev *mdp; + int id; cmd = container_of(work, struct mdp_cmdq_cmd, auto_release_work); mdp = cmd->mdp; - mtk_mutex_unprepare(mdp->mdp_mutex[MDP_PIPE_RDMA0]); + id = mdp->mdp_data->pipe_info[MDP_PIPE_RDMA0].mutex_id; + mtk_mutex_unprepare(mdp->mdp_mutex[id]); mdp_comp_clocks_off(&mdp->pdev->dev, cmd->comps, cmd->num_comps); @@ -310,6 +313,7 @@ static void mdp_handle_cmdq_callback(struct mbox_client *cl, void *mssg) struct cmdq_cb_data *data; struct mdp_dev *mdp; struct device *dev; + int id; if (!mssg) { pr_info("%s:no callback data\n", __func__); @@ -335,7 +339,8 @@ static void mdp_handle_cmdq_callback(struct mbox_client *cl, void *mssg) INIT_WORK(&cmd->auto_release_work, mdp_auto_release_work); if (!queue_work(mdp->clock_wq, &cmd->auto_release_work)) { dev_err(dev, "%s:queue_work fail!\n", __func__); - mtk_mutex_unprepare(mdp->mdp_mutex[MDP_PIPE_RDMA0]); + id = mdp->mdp_data->pipe_info[MDP_PIPE_RDMA0].mutex_id; + mtk_mutex_unprepare(mdp->mdp_mutex[id]); mdp_comp_clocks_off(&mdp->pdev->dev, cmd->comps, cmd->num_comps); @@ -387,7 +392,8 @@ int mdp_cmdq_send(struct mdp_dev *mdp, struct mdp_cmdq_param *param) goto err_free_comps; } - ret = mtk_mutex_prepare(mdp->mdp_mutex[MDP_PIPE_RDMA0]); + i = mdp->mdp_data->pipe_info[MDP_PIPE_RDMA0].mutex_id; + ret = mtk_mutex_prepare(mdp->mdp_mutex[i]); if (ret) { dev_err(dev, "Fail to enable mutex clk\n"); goto err_free_path; @@ -453,7 +459,8 @@ int mdp_cmdq_send(struct mdp_dev *mdp, struct mdp_cmdq_param *param) mdp_comp_clocks_off(&mdp->pdev->dev, cmd->comps, cmd->num_comps); err_free_path: - mtk_mutex_unprepare(mdp->mdp_mutex[MDP_PIPE_RDMA0]); + i = mdp->mdp_data->pipe_info[MDP_PIPE_RDMA0].mutex_id; + mtk_mutex_unprepare(mdp->mdp_mutex[i]); kfree(path); err_free_comps: kfree(comps); diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c index 745cb06cc8bc..1c798da1df2c 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c @@ -153,7 +153,7 @@ static int mdp_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct mdp_dev *mdp; struct platform_device *mm_pdev; - int ret, i; + int ret, i, mutex_id; mdp = kzalloc(sizeof(*mdp), GFP_KERNEL); if (!mdp) { @@ -176,10 +176,13 @@ static int mdp_probe(struct platform_device *pdev) ret = -ENODEV; goto err_destroy_device; } - for (i = 0; i < MDP_PIPE_MAX; i++) { - mdp->mdp_mutex[i] = mtk_mutex_get(&mm_pdev->dev); - if (IS_ERR(mdp->mdp_mutex[i])) { - ret = PTR_ERR(mdp->mdp_mutex[i]); + for (i = 0; i < mdp->mdp_data->pipe_info_len; i++) { + mutex_id = mdp->mdp_data->pipe_info[i].mutex_id; + if (!IS_ERR_OR_NULL(mdp->mdp_mutex[mutex_id])) + continue; + mdp->mdp_mutex[mutex_id] = mtk_mutex_get(&mm_pdev->dev); + if (IS_ERR(mdp->mdp_mutex[mutex_id])) { + ret = PTR_ERR(mdp->mdp_mutex[mutex_id]); goto err_free_mutex; } } @@ -259,7 +262,7 @@ static int mdp_probe(struct platform_device *pdev) err_deinit_comp: mdp_comp_destroy(mdp); err_free_mutex: - for (i = 0; i < MDP_PIPE_MAX; i++) + for (i = 0; i < mdp->mdp_data->pipe_info_len; i++) if (!IS_ERR_OR_NULL(mdp->mdp_mutex[i])) mtk_mutex_put(mdp->mdp_mutex[i]); err_destroy_device: diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h index a312c1007e96..59a1c88d8184 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h @@ -43,10 +43,10 @@ struct mdp_platform_config { /* indicate which mutex is used by each pipepline */ enum mdp_pipe_id { - MDP_PIPE_RDMA0, - MDP_PIPE_IMGI, MDP_PIPE_WPEI, MDP_PIPE_WPEI2, + MDP_PIPE_IMGI, + MDP_PIPE_RDMA0, MDP_PIPE_MAX }; @@ -60,6 +60,8 @@ struct mtk_mdp_driver_data { const struct mdp_format *format; unsigned int format_len; const struct mdp_limit *def_limit; + const struct mdp_pipe_info *pipe_info; + unsigned int pipe_info_len; }; struct mdp_dev { @@ -91,6 +93,11 @@ struct mdp_dev { atomic_t job_count; }; +struct mdp_pipe_info { + enum mdp_pipe_id pipe_id; + u32 mutex_id; +}; + int mdp_vpu_get_locked(struct mdp_dev *mdp); void mdp_vpu_put_locked(struct mdp_dev *mdp); int mdp_vpu_register(struct mdp_dev *mdp); From patchwork Mon Mar 27 03:13:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Moudy Ho X-Patchwork-Id: 667737 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 56D29C77B61 for ; Mon, 27 Mar 2023 03:14:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232252AbjC0DOF (ORCPT ); Sun, 26 Mar 2023 23:14:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48974 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232209AbjC0DN4 (ORCPT ); Sun, 26 Mar 2023 23:13:56 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 45CBF5242; Sun, 26 Mar 2023 20:13:45 -0700 (PDT) X-UUID: 5ddc740ccc4d11eda9a90f0bb45854f4-20230327 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=PaK2Ax1nukBsK7RDktlgDq7qAPbABrE9aD80ZftMZu4=; b=rBVWvUALrJ+RitkWMhaWhh4Zzd6kgnbExEvXeEvlJcBElD2YtUXnqnMHhBPipklMy+e26MXtUJiTegS2qG6jIizcJPp+zbEF/Wdb4ZkTHl7UYI7ewJGZ7Ob3w4IyN314QRYzGGxIjX7z3kP1V3ZrREhDqJstsZpHEaeYKSioFA4=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.22, REQID:408c0613-0c13-436a-a31a-0bdcdaed2e25, IP:0, U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:95 X-CID-INFO: VERSION:1.1.22, REQID:408c0613-0c13-436a-a31a-0bdcdaed2e25, IP:0, URL :0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTION :quarantine,TS:95 X-CID-META: VersionHash:120426c, CLOUDID:b298fef6-ddba-41c3-91d9-10eeade8eac7, B ulkID:2303271113409PQ9IH6Y,BulkQuantity:0,Recheck:0,SF:38|29|28|17|19|48,T C:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 ,OSI:0,OSA:0,AV:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-UUID: 5ddc740ccc4d11eda9a90f0bb45854f4-20230327 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 441849732; Mon, 27 Mar 2023 11:13:37 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.25; Mon, 27 Mar 2023 11:13:37 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.25 via Frontend Transport; Mon, 27 Mar 2023 11:13:37 +0800 From: Moudy Ho To: Mauro Carvalho Chehab , Matthias Brugger , Hans Verkuil , Ping-Hsun Wu CC: , , , , , Moudy Ho Subject: [PATCH v7 09/12] media: platform: mtk-mdp3: dynamically allocate component clocks Date: Mon, 27 Mar 2023 11:13:32 +0800 Message-ID: <20230327031335.9663-10-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230327031335.9663-1-moudy.ho@mediatek.com> References: <20230327031335.9663-1-moudy.ho@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org For extensibility of adding more MDP3 components in the further, the magic number is removed by dynamically allocating component clocks. Signed-off-by: Moudy Ho --- .../platform/mediatek/mdp3/mtk-mdp3-comp.c | 50 +++++++++++-------- .../platform/mediatek/mdp3/mtk-mdp3-comp.h | 3 +- 2 files changed, 31 insertions(+), 22 deletions(-) diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c index 49bfe0094b19..d9963f265a07 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c @@ -641,7 +641,8 @@ int mdp_comp_clock_on(struct device *dev, struct mdp_comp *comp) { int i, ret; - if (comp->comp_dev) { + /* Only DMA capable components need the pm control */ + if (comp->comp_dev && is_dma_capable(comp->type)) { ret = pm_runtime_resume_and_get(comp->comp_dev); if (ret < 0) { dev_err(dev, @@ -651,7 +652,7 @@ int mdp_comp_clock_on(struct device *dev, struct mdp_comp *comp) } } - for (i = 0; i < ARRAY_SIZE(comp->clks); i++) { + for (i = 0; i < comp->clk_num; i++) { if (IS_ERR_OR_NULL(comp->clks[i])) continue; ret = clk_prepare_enable(comp->clks[i]); @@ -671,7 +672,7 @@ int mdp_comp_clock_on(struct device *dev, struct mdp_comp *comp) continue; clk_disable_unprepare(comp->clks[i]); } - if (comp->comp_dev) + if (comp->comp_dev && is_dma_capable(comp->type)) pm_runtime_put_sync(comp->comp_dev); return ret; @@ -681,13 +682,13 @@ void mdp_comp_clock_off(struct device *dev, struct mdp_comp *comp) { int i; - for (i = 0; i < ARRAY_SIZE(comp->clks); i++) { + for (i = 0; i < comp->clk_num; i++) { if (IS_ERR_OR_NULL(comp->clks[i])) continue; clk_disable_unprepare(comp->clks[i]); } - if (comp->comp_dev) + if (comp->comp_dev && is_dma_capable(comp->type)) pm_runtime_put(comp->comp_dev); } @@ -766,7 +767,7 @@ static int mdp_comp_init(struct mdp_dev *mdp, struct device_node *node, struct mdp_comp *comp, enum mtk_mdp_comp_id id) { struct device *dev = &mdp->pdev->dev; - int clk_num; + struct platform_device *pdev_c; int clk_ofst; int i; s32 event; @@ -776,6 +777,14 @@ static int mdp_comp_init(struct mdp_dev *mdp, struct device_node *node, return -EINVAL; } + pdev_c = of_find_device_by_node(node); + if (!pdev_c) { + dev_warn(dev, "can't find platform device of node:%s\n", + node->name); + return -ENODEV; + } + + comp->comp_dev = &pdev_c->dev; comp->public_id = id; comp->type = mdp->mdp_data->comp_data[id].match.type; comp->inner_id = mdp->mdp_data->comp_data[id].match.inner_id; @@ -783,10 +792,15 @@ static int mdp_comp_init(struct mdp_dev *mdp, struct device_node *node, comp->ops = mdp_comp_ops[comp->type]; __mdp_comp_init(mdp, node, comp); - clk_num = mdp->mdp_data->comp_data[id].info.clk_num; + comp->clk_num = mdp->mdp_data->comp_data[id].info.clk_num; + comp->clks = devm_kzalloc(dev, sizeof(struct clk *) * comp->clk_num, + GFP_KERNEL); + if (!comp->clks) + return -ENOMEM; + clk_ofst = mdp->mdp_data->comp_data[id].info.clk_ofst; - for (i = 0; i < clk_num; i++) { + for (i = 0; i < comp->clk_num; i++) { comp->clks[i] = of_clk_get(node, i + clk_ofst); if (IS_ERR(comp->clks[i])) break; @@ -823,6 +837,11 @@ static void mdp_comp_deinit(struct mdp_comp *comp) if (!comp) return; + if (comp->comp_dev && comp->clks) { + devm_kfree(&comp->mdp_dev->pdev->dev, comp->clks); + comp->clks = NULL; + } + if (comp->regs) iounmap(comp->regs); } @@ -904,7 +923,8 @@ void mdp_comp_destroy(struct mdp_dev *mdp) for (i = 0; i < ARRAY_SIZE(mdp->comp); i++) { if (mdp->comp[i]) { - pm_runtime_disable(mdp->comp[i]->comp_dev); + if (is_dma_capable(mdp->comp[i]->type)) + pm_runtime_disable(mdp->comp[i]->comp_dev); mdp_comp_deinit(mdp->comp[i]); devm_kfree(mdp->comp[i]->comp_dev, mdp->comp[i]); mdp->comp[i] = NULL; @@ -916,7 +936,6 @@ int mdp_comp_config(struct mdp_dev *mdp) { struct device *dev = &mdp->pdev->dev; struct device_node *node, *parent; - struct platform_device *pdev; int ret; memset(mdp_comp_alias_id, 0, sizeof(mdp_comp_alias_id)); @@ -957,19 +976,8 @@ int mdp_comp_config(struct mdp_dev *mdp) } /* Only DMA capable components need the pm control */ - comp->comp_dev = NULL; if (!is_dma_capable(comp->type)) continue; - - pdev = of_find_device_by_node(node); - if (!pdev) { - dev_warn(dev, "can't find platform device of node:%s\n", - node->name); - ret = -ENODEV; - goto err_init_comps; - } - - comp->comp_dev = &pdev->dev; pm_runtime_enable(comp->comp_dev); } diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.h b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.h index 3de994d7ef1c..20d2bcb77ef9 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.h +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.h @@ -159,7 +159,8 @@ struct mdp_comp { void __iomem *regs; phys_addr_t reg_base; u8 subsys_id; - struct clk *clks[6]; + u8 clk_num; + struct clk **clks; struct device *comp_dev; enum mdp_comp_type type; enum mtk_mdp_comp_id public_id; From patchwork Mon Mar 27 03:13:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Moudy Ho X-Patchwork-Id: 667736 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4F14FC77B61 for ; Mon, 27 Mar 2023 03:14:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232173AbjC0DO3 (ORCPT ); Sun, 26 Mar 2023 23:14:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49002 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232215AbjC0DN6 (ORCPT ); Sun, 26 Mar 2023 23:13:58 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 08D9F5589; Sun, 26 Mar 2023 20:13:45 -0700 (PDT) X-UUID: 5def37f4cc4d11edb6b9f13eb10bd0fe-20230327 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=KpS7zOQiS8xm+MgSXF0zo7YlE8zlcISMKY7OkefTdQ8=; b=LiSVo88otfiZLIsH6j3xwIVh5vgqzIcqPlCxFeyKGcWZaCUtye1tKOQPOMUqqJU9NA80Y/RsXdOnPGdM2/2WzImix8EnzRUpY1wXl/05/l44Q/lyKxB1GqrwYPGIdekmnjkdAEjfs8AKjw1MekwNZJESQkn4XVMQRT5O7AiFd58=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.22, REQID:9f1b5251-3baf-4810-915d-4a004a9f1c44, IP:0, U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:95 X-CID-INFO: VERSION:1.1.22, REQID:9f1b5251-3baf-4810-915d-4a004a9f1c44, IP:0, URL :0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTION :quarantine,TS:95 X-CID-META: VersionHash:120426c, CLOUDID:b9f870b4-beed-4dfc-bd9c-e1b22fa6ccc4, B ulkID:230327111339EGEJ7AOR,BulkQuantity:0,Recheck:0,SF:38|29|28|17|19|48,T C:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 ,OSI:0,OSA:0,AV:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-UUID: 5def37f4cc4d11edb6b9f13eb10bd0fe-20230327 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 277477412; Mon, 27 Mar 2023 11:13:37 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.25; Mon, 27 Mar 2023 11:13:37 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.25 via Frontend Transport; Mon, 27 Mar 2023 11:13:37 +0800 From: Moudy Ho To: Mauro Carvalho Chehab , Matthias Brugger , Hans Verkuil , Ping-Hsun Wu CC: , , , , , Moudy Ho Subject: [PATCH v7 10/12] media: platform: mtk-mdp3: Split general definitions used in MDP3 Date: Mon, 27 Mar 2023 11:13:33 +0800 Message-ID: <20230327031335.9663-11-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230327031335.9663-1-moudy.ho@mediatek.com> References: <20230327031335.9663-1-moudy.ho@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Separate the generic definitions used in MDP3 to avoid recursive includes when splitting chip-related definitions in further. Signed-off-by: Moudy Ho --- .../platform/mediatek/mdp3/mtk-img-ipi.h | 46 +--------------- .../platform/mediatek/mdp3/mtk-mdp3-type.h | 53 +++++++++++++++++++ 2 files changed, 54 insertions(+), 45 deletions(-) create mode 100644 drivers/media/platform/mediatek/mdp3/mtk-mdp3-type.h diff --git a/drivers/media/platform/mediatek/mdp3/mtk-img-ipi.h b/drivers/media/platform/mediatek/mdp3/mtk-img-ipi.h index c7f231f8ea3e..f5296994137a 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-img-ipi.h +++ b/drivers/media/platform/mediatek/mdp3/mtk-img-ipi.h @@ -8,7 +8,7 @@ #ifndef __MTK_IMG_IPI_H__ #define __MTK_IMG_IPI_H__ -#include +#include "mtk-mdp3-type.h" /* * ISP-MDP generic input information @@ -16,12 +16,6 @@ * 6da52bdcf4bf76a0983b313e1d4745d6 */ -#define IMG_MAX_HW_INPUTS 3 - -#define IMG_MAX_HW_OUTPUTS 4 - -#define IMG_MAX_PLANES 3 - #define IMG_IPI_INIT 1 #define IMG_IPI_DEINIT 2 #define IMG_IPI_FRAME 3 @@ -71,17 +65,6 @@ struct img_image_buffer { #define IMG_SUBPIXEL_SHIFT 20 -struct img_crop { - s32 left; - s32 top; - u32 width; - u32 height; - u32 left_subpix; - u32 top_subpix; - u32 width_subpix; - u32 height_subpix; -} __packed; - #define IMG_CTRL_FLAG_HFLIP BIT(0) #define IMG_CTRL_FLAG_DITHER BIT(1) #define IMG_CTRL_FLAG_SHARPNESS BIT(4) @@ -146,20 +129,6 @@ struct img_comp_frame { u32 out_total_width; } __packed; -struct img_region { - s32 left; - s32 right; - s32 top; - s32 bottom; -} __packed; - -struct img_offset { - s32 left; - s32 top; - u32 left_subpix; - u32 top_subpix; -} __packed; - struct img_comp_subfrm { u32 tile_disable; struct img_region in; @@ -267,19 +236,6 @@ struct img_compparam { }; } __packed; -#define IMG_MAX_COMPONENTS 20 - -struct img_mux { - u32 reg; - u32 value; - u32 subsys_id; -} __packed; - -struct img_mmsys_ctrl { - struct img_mux sets[IMG_MAX_COMPONENTS * 2]; - u32 num_sets; -} __packed; - struct img_config { struct img_compparam components[IMG_MAX_COMPONENTS]; u32 num_components; diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-type.h b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-type.h new file mode 100644 index 000000000000..ae0396806152 --- /dev/null +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-type.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2023 MediaTek Inc. + * Author: Ping-Hsun Wu + */ + +#ifndef __MTK_MDP3_TYPE_H__ +#define __MTK_MDP3_TYPE_H__ + +#include + +#define IMG_MAX_HW_INPUTS 3 +#define IMG_MAX_HW_OUTPUTS 4 +#define IMG_MAX_PLANES 3 +#define IMG_MAX_COMPONENTS 20 + +struct img_crop { + s32 left; + s32 top; + u32 width; + u32 height; + u32 left_subpix; + u32 top_subpix; + u32 width_subpix; + u32 height_subpix; +} __packed; + +struct img_region { + s32 left; + s32 right; + s32 top; + s32 bottom; +} __packed; + +struct img_offset { + s32 left; + s32 top; + u32 left_subpix; + u32 top_subpix; +} __packed; + +struct img_mux { + u32 reg; + u32 value; + u32 subsys_id; +} __packed; + +struct img_mmsys_ctrl { + struct img_mux sets[IMG_MAX_COMPONENTS * 2]; + u32 num_sets; +} __packed; + +#endif /* __MTK_MDP3_TYPE_H__ */ From patchwork Mon Mar 27 03:13:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Moudy Ho X-Patchwork-Id: 667732 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EB7B4C77B6D for ; Mon, 27 Mar 2023 03:14:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231950AbjC0DOk (ORCPT ); Sun, 26 Mar 2023 23:14:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49020 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232303AbjC0DOL (ORCPT ); Sun, 26 Mar 2023 23:14:11 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A3D74524A; Sun, 26 Mar 2023 20:13:48 -0700 (PDT) X-UUID: 5e43d002cc4d11eda9a90f0bb45854f4-20230327 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=LLY05QfMAClfY91M32t997VI4Tj6KOzBYaIJfd4/Tm0=; b=WxL/PhrbC5ENJDHXGm2jahWmoxORl/brh8JEh6iQdiaY4Q1vF1B/RdTBfW9b84bwcteqkT/igO6yLOGq3AF3Oy3nZEcXN9MNlPucXBUrRuqaiXBJPM0LDxqJSTDk3IFYY5FKOkhqa1jvWGZick7pGR/b/kymbuu7dGWywFlF1L8=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.22, REQID:1e41f2e5-783b-4980-be23-1f20ac2fe617, IP:0, U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:-5 X-CID-META: VersionHash:120426c, CLOUDID:c8d38f29-564d-42d9-9875-7c868ee415ec, B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-UUID: 5e43d002cc4d11eda9a90f0bb45854f4-20230327 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 479668115; Mon, 27 Mar 2023 11:13:38 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.25; Mon, 27 Mar 2023 11:13:37 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.25 via Frontend Transport; Mon, 27 Mar 2023 11:13:37 +0800 From: Moudy Ho To: Mauro Carvalho Chehab , Matthias Brugger , Hans Verkuil , "Ping-Hsun Wu" CC: , , , , , Moudy Ho Subject: [PATCH v7 11/12] media: platform: mtk-mdp3: decompose hardware-related information in shared memory Date: Mon, 27 Mar 2023 11:13:34 +0800 Message-ID: <20230327031335.9663-12-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230327031335.9663-1-moudy.ho@mediatek.com> References: <20230327031335.9663-1-moudy.ho@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org The communication between the MDP3 kernel driver and SCP is to pass a shared memory through the cooperation of "mtk-mdp3-vpu.c" and remoteproc driver. The data structure of this shared memory is defined in "mtk-img-ipi.h", as shown below: vpu->work_addr -> +-----------------------------------------+ | | | To SCP : Input frame parameters | | (struct img_ipi_frameparam) | | | vpu->pool -> +-----------------------------------------+ | | | From SCP : Output component config pool | | (struct img_config) | | | | *struct img_config 1 | | | | | | | | v | | *struct img_config N | | (N = MDP_CONFIG_POOL_SIZE) | +-----------------------------------------+ One output component configuration contains the components currently used by the pipeline, and has the register settings that each component needs to set. Since the quantity, type and function of components on each chip will vary, the effect is that the size of the "struct img_config" and its substructures will be different on each chip. In addition, all chips will have to update their SCP firmware for every change if the output component config structure is defined and shared by a common header. Therefore, all functions that operate on "struct img_config" and its substructures must be separated by chips and so are the relevant definations. Signed-off-by: Moudy Ho --- .../platform/mediatek/mdp3/mdp_cfg_data.c | 2 + .../platform/mediatek/mdp3/mdp_sm_mt8183.h | 144 +++++++ .../platform/mediatek/mdp3/mtk-img-ipi.h | 143 ++----- .../platform/mediatek/mdp3/mtk-mdp3-cmdq.c | 121 ++++-- .../platform/mediatek/mdp3/mtk-mdp3-comp.c | 364 +++++++++++++----- .../platform/mediatek/mdp3/mtk-mdp3-core.h | 1 + 6 files changed, 526 insertions(+), 249 deletions(-) create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_sm_mt8183.h diff --git a/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c b/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c index cf97ba70fddd..502eeae0bfdc 100644 --- a/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c +++ b/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c @@ -4,6 +4,7 @@ * Author: Ping-Hsun Wu */ +#include "mtk-img-ipi.h" #include "mtk-mdp3-cfg.h" #include "mtk-mdp3-core.h" #include "mtk-mdp3-comp.h" @@ -408,6 +409,7 @@ static const struct mdp_pipe_info mt8183_pipe_info[] = { }; const struct mtk_mdp_driver_data mt8183_mdp_driver_data = { + .mdp_plat_id = MT8183, .mdp_probe_infra = mt8183_mdp_probe_infra, .mdp_cfg = &mt8183_plat_cfg, .mdp_mutex_table_idx = mt8183_mutex_idx, diff --git a/drivers/media/platform/mediatek/mdp3/mdp_sm_mt8183.h b/drivers/media/platform/mediatek/mdp3/mdp_sm_mt8183.h new file mode 100644 index 000000000000..effc75615af9 --- /dev/null +++ b/drivers/media/platform/mediatek/mdp3/mdp_sm_mt8183.h @@ -0,0 +1,144 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2023 MediaTek Inc. + * Author: Ping-Hsun Wu + */ + +#ifndef __MDP_SM_MT8183_H__ +#define __MDP_SM_MT8183_H__ + +#include "mtk-mdp3-type.h" + +/* + * ISP-MDP generic output information + * MD5 of the target SCP blob: + * 6da52bdcf4bf76a0983b313e1d4745d6 + */ + +#define IMG_MAX_SUBFRAMES_8183 14 + +struct img_comp_frame_8183 { + u32 output_disable:1; + u32 bypass:1; + u16 in_width; + u16 in_height; + u16 out_width; + u16 out_height; + struct img_crop crop; + u16 in_total_width; + u16 out_total_width; +} __packed; + +struct img_comp_subfrm_8183 { + u32 tile_disable:1; + struct img_region in; + struct img_region out; + struct img_offset luma; + struct img_offset chroma; + s16 out_vertical; /* Output vertical index */ + s16 out_horizontal; /* Output horizontal index */ +} __packed; + +struct mdp_rdma_subfrm_8183 { + u32 offset[IMG_MAX_PLANES]; + u32 offset_0_p; + u32 src; + u32 clip; + u32 clip_ofst; +} __packed; + +struct mdp_rdma_data_8183 { + u32 src_ctrl; + u32 control; + u32 iova[IMG_MAX_PLANES]; + u32 iova_end[IMG_MAX_PLANES]; + u32 mf_bkgd; + u32 mf_bkgd_in_pxl; + u32 sf_bkgd; + u32 ufo_dec_y; + u32 ufo_dec_c; + u32 transform; + struct mdp_rdma_subfrm_8183 subfrms[IMG_MAX_SUBFRAMES_8183]; +} __packed; + +struct mdp_rsz_subfrm_8183 { + u32 control2; + u32 src; + u32 clip; +} __packed; + +struct mdp_rsz_data_8183 { + u32 coeff_step_x; + u32 coeff_step_y; + u32 control1; + u32 control2; + struct mdp_rsz_subfrm_8183 subfrms[IMG_MAX_SUBFRAMES_8183]; +} __packed; + +struct mdp_wrot_subfrm_8183 { + u32 offset[IMG_MAX_PLANES]; + u32 src; + u32 clip; + u32 clip_ofst; + u32 main_buf; +} __packed; + +struct mdp_wrot_data_8183 { + u32 iova[IMG_MAX_PLANES]; + u32 control; + u32 stride[IMG_MAX_PLANES]; + u32 mat_ctrl; + u32 fifo_test; + u32 filter; + struct mdp_wrot_subfrm_8183 subfrms[IMG_MAX_SUBFRAMES_8183]; +} __packed; + +struct mdp_wdma_subfrm_8183 { + u32 offset[IMG_MAX_PLANES]; + u32 src; + u32 clip; + u32 clip_ofst; +} __packed; + +struct mdp_wdma_data_8183 { + u32 wdma_cfg; + u32 iova[IMG_MAX_PLANES]; + u32 w_in_byte; + u32 uv_stride; + struct mdp_wdma_subfrm_8183 subfrms[IMG_MAX_SUBFRAMES_8183]; +} __packed; + +struct isp_data_8183 { + u64 dl_flags; /* 1 << (enum mdp_comp_type) */ + u32 smxi_iova[4]; + u32 cq_idx; + u32 cq_iova; + u32 tpipe_iova[IMG_MAX_SUBFRAMES_8183]; +} __packed; + +struct img_compparam_8183 { + u16 type; /* enum mdp_comp_id */ + u16 id; /* engine alias_id */ + u32 input; + u32 outputs[IMG_MAX_HW_OUTPUTS]; + u32 num_outputs; + struct img_comp_frame_8183 frame; + struct img_comp_subfrm_8183 subfrms[IMG_MAX_SUBFRAMES_8183]; + u32 num_subfrms; + union { + struct mdp_rdma_data_8183 rdma; + struct mdp_rsz_data_8183 rsz; + struct mdp_wrot_data_8183 wrot; + struct mdp_wdma_data_8183 wdma; + struct isp_data_8183 isp; + }; +} __packed; + +struct img_config_8183 { + struct img_compparam_8183 components[IMG_MAX_COMPONENTS]; + u32 num_components; + struct img_mmsys_ctrl ctrls[IMG_MAX_SUBFRAMES_8183]; + u32 num_subfrms; +} __packed; + +#endif /* __MDP_SM_MT8183_H__ */ diff --git a/drivers/media/platform/mediatek/mdp3/mtk-img-ipi.h b/drivers/media/platform/mediatek/mdp3/mtk-img-ipi.h index f5296994137a..22b8b9a10ef7 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-img-ipi.h +++ b/drivers/media/platform/mediatek/mdp3/mtk-img-ipi.h @@ -8,13 +8,11 @@ #ifndef __MTK_IMG_IPI_H__ #define __MTK_IMG_IPI_H__ +#include +#include "mdp_sm_mt8183.h" #include "mtk-mdp3-type.h" -/* - * ISP-MDP generic input information - * MD5 of the target SCP blob: - * 6da52bdcf4bf76a0983b313e1d4745d6 - */ +/* ISP-MDP generic input information */ #define IMG_IPI_INIT 1 #define IMG_IPI_DEINIT 2 @@ -115,132 +113,37 @@ struct img_frameparam { struct img_ipi_frameparam frameparam; } __packed; -/* ISP-MDP generic output information */ +/* Platform config indicator */ +#define MT8183 8183 -struct img_comp_frame { - u32 output_disable; - u32 bypass; - u32 in_width; - u32 in_height; - u32 out_width; - u32 out_height; - struct img_crop crop; - u32 in_total_width; - u32 out_total_width; -} __packed; +#define CFG_CHECK(plat, p_id) ((plat) == (p_id)) -struct img_comp_subfrm { - u32 tile_disable; - struct img_region in; - struct img_region out; - struct img_offset luma; - struct img_offset chroma; - s32 out_vertical; /* Output vertical index */ - s32 out_horizontal; /* Output horizontal index */ -} __packed; +#define _CFG_OFST(plat, cfg, ofst) ((void *)(&((cfg)->config_##plat) + (ofst))) +#define CFG_OFST(plat, cfg, ofst) \ + (IS_ERR_OR_NULL(cfg) ? NULL : _CFG_OFST(plat, cfg, ofst)) -#define IMG_MAX_SUBFRAMES 14 +#define _CFG_ADDR(plat, cfg, mem) (&((cfg)->config_##plat.mem)) +#define CFG_ADDR(plat, cfg, mem) \ + (IS_ERR_OR_NULL(cfg) ? NULL : _CFG_ADDR(plat, cfg, mem)) -struct mdp_rdma_subfrm { - u32 offset[IMG_MAX_PLANES]; - u32 offset_0_p; - u32 src; - u32 clip; - u32 clip_ofst; -} __packed; +#define _CFG_GET(plat, cfg, mem) ((cfg)->config_##plat.mem) +#define CFG_GET(plat, cfg, mem) \ + (IS_ERR_OR_NULL(cfg) ? 0 : _CFG_GET(plat, cfg, mem)) -struct mdp_rdma_data { - u32 src_ctrl; - u32 control; - u32 iova[IMG_MAX_PLANES]; - u32 iova_end[IMG_MAX_PLANES]; - u32 mf_bkgd; - u32 mf_bkgd_in_pxl; - u32 sf_bkgd; - u32 ufo_dec_y; - u32 ufo_dec_c; - u32 transform; - struct mdp_rdma_subfrm subfrms[IMG_MAX_SUBFRAMES]; -} __packed; +#define _CFG_COMP(plat, comp, mem) ((comp)->comp_##plat.mem) +#define CFG_COMP(plat, comp, mem) \ + (IS_ERR_OR_NULL(comp) ? 0 : _CFG_COMP(plat, comp, mem)) -struct mdp_rsz_subfrm { - u32 control2; - u32 src; - u32 clip; -} __packed; - -struct mdp_rsz_data { - u32 coeff_step_x; - u32 coeff_step_y; - u32 control1; - u32 control2; - struct mdp_rsz_subfrm subfrms[IMG_MAX_SUBFRAMES]; -} __packed; - -struct mdp_wrot_subfrm { - u32 offset[IMG_MAX_PLANES]; - u32 src; - u32 clip; - u32 clip_ofst; - u32 main_buf; -} __packed; - -struct mdp_wrot_data { - u32 iova[IMG_MAX_PLANES]; - u32 control; - u32 stride[IMG_MAX_PLANES]; - u32 mat_ctrl; - u32 fifo_test; - u32 filter; - struct mdp_wrot_subfrm subfrms[IMG_MAX_SUBFRAMES]; -} __packed; - -struct mdp_wdma_subfrm { - u32 offset[IMG_MAX_PLANES]; - u32 src; - u32 clip; - u32 clip_ofst; -} __packed; - -struct mdp_wdma_data { - u32 wdma_cfg; - u32 iova[IMG_MAX_PLANES]; - u32 w_in_byte; - u32 uv_stride; - struct mdp_wdma_subfrm subfrms[IMG_MAX_SUBFRAMES]; -} __packed; - -struct isp_data { - u64 dl_flags; /* 1 << (enum mdp_comp_type) */ - u32 smxi_iova[4]; - u32 cq_idx; - u32 cq_iova; - u32 tpipe_iova[IMG_MAX_SUBFRAMES]; +struct img_config { + union { + struct img_config_8183 config_8183; + }; } __packed; struct img_compparam { - u32 type; /* enum mdp_comp_id */ - u32 id; /* engine alias_id */ - u32 input; - u32 outputs[IMG_MAX_HW_OUTPUTS]; - u32 num_outputs; - struct img_comp_frame frame; - struct img_comp_subfrm subfrms[IMG_MAX_SUBFRAMES]; - u32 num_subfrms; union { - struct mdp_rdma_data rdma; - struct mdp_rsz_data rsz; - struct mdp_wrot_data wrot; - struct mdp_wdma_data wdma; - struct isp_data isp; + struct img_compparam_8183 comp_8183; }; } __packed; -struct img_config { - struct img_compparam components[IMG_MAX_COMPONENTS]; - u32 num_components; - struct img_mmsys_ctrl ctrls[IMG_MAX_SUBFRAMES]; - u32 num_subfrms; -} __packed; - #endif /* __MTK_IMG_IPI_H__ */ diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c index bff14e4944c5..3177592490be 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c @@ -10,6 +10,7 @@ #include "mtk-mdp3-comp.h" #include "mtk-mdp3-core.h" #include "mtk-mdp3-m2m.h" +#include "mtk-img-ipi.h" #define MDP_PATH_MAX_COMPS IMG_MAX_COMPONENTS @@ -28,24 +29,35 @@ struct mdp_path { #define call_op(ctx, op, ...) \ (has_op(ctx, op) ? (ctx)->comp->ops->op(ctx, ##__VA_ARGS__) : 0) -static bool is_output_disabled(const struct img_compparam *param, u32 count) +static bool is_output_disabled(int p_id, const struct img_compparam *param, u32 count) { - return (count < param->num_subfrms) ? - (param->frame.output_disable || - param->subfrms[count].tile_disable) : - true; + u32 num = 0; + bool dis_output = false; + bool dis_tile = false; + + if (CFG_CHECK(MT8183, p_id)) { + num = CFG_COMP(MT8183, param, num_subfrms); + dis_output = CFG_COMP(MT8183, param, frame.output_disable); + dis_tile = CFG_COMP(MT8183, param, frame.output_disable); + } + + return (count < num) ? (dis_output || dis_tile) : true; } static int mdp_path_subfrm_require(const struct mdp_path *path, struct mdp_cmdq_cmd *cmd, s32 *mutex_id, u32 count) { - const struct img_config *config = path->config; + const int p_id = path->mdp_dev->mdp_data->mdp_plat_id; const struct mdp_comp_ctx *ctx; const struct mtk_mdp_driver_data *data = path->mdp_dev->mdp_data; struct device *dev = &path->mdp_dev->pdev->dev; struct mtk_mutex **mutex = path->mdp_dev->mdp_mutex; int id, index; + u32 num_comp = 0; + + if (CFG_CHECK(MT8183, p_id)) + num_comp = CFG_GET(MT8183, path->config, num_components); /* Decide which mutex to use based on the current pipeline */ switch (path->comps[0].comp->public_id) { @@ -68,9 +80,9 @@ static int mdp_path_subfrm_require(const struct mdp_path *path, *mutex_id = data->pipe_info[index].mutex_id; /* Set mutex mod */ - for (index = 0; index < config->num_components; index++) { + for (index = 0; index < num_comp; index++) { ctx = &path->comps[index]; - if (is_output_disabled(ctx->param, count)) + if (is_output_disabled(p_id, ctx->param, count)) continue; id = ctx->comp->public_id; mtk_mutex_write_mod(mutex[*mutex_id], @@ -87,11 +99,12 @@ static int mdp_path_subfrm_run(const struct mdp_path *path, struct mdp_cmdq_cmd *cmd, s32 *mutex_id, u32 count) { - const struct img_config *config = path->config; + const int p_id = path->mdp_dev->mdp_data->mdp_plat_id; const struct mdp_comp_ctx *ctx; struct device *dev = &path->mdp_dev->pdev->dev; struct mtk_mutex **mutex = path->mdp_dev->mdp_mutex; int index; + u32 num_comp = 0; s32 event; if (-1 == *mutex_id) { @@ -99,11 +112,14 @@ static int mdp_path_subfrm_run(const struct mdp_path *path, return -EINVAL; } + if (CFG_CHECK(MT8183, p_id)) + num_comp = CFG_GET(MT8183, path->config, num_components); + /* Wait WROT SRAM shared to DISP RDMA */ /* Clear SOF event for each engine */ - for (index = 0; index < config->num_components; index++) { + for (index = 0; index < num_comp; index++) { ctx = &path->comps[index]; - if (is_output_disabled(ctx->param, count)) + if (is_output_disabled(p_id, ctx->param, count)) continue; event = ctx->comp->gce_event[MDP_GCE_EVENT_SOF]; if (event != MDP_GCE_NO_EVENT) @@ -114,9 +130,9 @@ static int mdp_path_subfrm_run(const struct mdp_path *path, mtk_mutex_enable_by_cmdq(mutex[*mutex_id], (void *)&cmd->pkt); /* Wait SOF events and clear mutex modules (optional) */ - for (index = 0; index < config->num_components; index++) { + for (index = 0; index < num_comp; index++) { ctx = &path->comps[index]; - if (is_output_disabled(ctx->param, count)) + if (is_output_disabled(p_id, ctx->param, count)) continue; event = ctx->comp->gce_event[MDP_GCE_EVENT_SOF]; if (event != MDP_GCE_NO_EVENT) @@ -128,16 +144,22 @@ static int mdp_path_subfrm_run(const struct mdp_path *path, static int mdp_path_ctx_init(struct mdp_dev *mdp, struct mdp_path *path) { - const struct img_config *config = path->config; + const int p_id = mdp->mdp_data->mdp_plat_id; + void *param = NULL; int index, ret; + u32 num_comp = 0; - if (config->num_components < 1) + if (CFG_CHECK(MT8183, p_id)) + num_comp = CFG_GET(MT8183, path->config, num_components); + + if (num_comp < 1) return -EINVAL; - for (index = 0; index < config->num_components; index++) { + for (index = 0; index < num_comp; index++) { + if (CFG_CHECK(MT8183, p_id)) + param = (void *)CFG_ADDR(MT8183, path->config, components[index]); ret = mdp_comp_ctx_config(mdp, &path->comps[index], - &config->components[index], - path->param); + param, path->param); if (ret) return ret; } @@ -148,12 +170,19 @@ static int mdp_path_ctx_init(struct mdp_dev *mdp, struct mdp_path *path) static int mdp_path_config_subfrm(struct mdp_cmdq_cmd *cmd, struct mdp_path *path, u32 count) { - const struct img_config *config = path->config; - const struct img_mmsys_ctrl *ctrl = &config->ctrls[count]; + const int p_id = path->mdp_dev->mdp_data->mdp_plat_id; + const struct img_mmsys_ctrl *ctrl = NULL; const struct img_mux *set; struct mdp_comp_ctx *ctx; s32 mutex_id; int index, ret; + u32 num_comp = 0; + + if (CFG_CHECK(MT8183, p_id)) + num_comp = CFG_GET(MT8183, path->config, num_components); + + if (CFG_CHECK(MT8183, p_id)) + ctrl = CFG_ADDR(MT8183, path->config, ctrls[count]); /* Acquire components */ ret = mdp_path_subfrm_require(path, cmd, &mutex_id, count); @@ -166,9 +195,9 @@ static int mdp_path_config_subfrm(struct mdp_cmdq_cmd *cmd, set->value, 0xFFFFFFFF); } /* Config sub-frame information */ - for (index = (config->num_components - 1); index >= 0; index--) { + for (index = (num_comp - 1); index >= 0; index--) { ctx = &path->comps[index]; - if (is_output_disabled(ctx->param, count)) + if (is_output_disabled(p_id, ctx->param, count)) continue; ret = call_op(ctx, config_subfrm, cmd, count); if (ret) @@ -179,16 +208,16 @@ static int mdp_path_config_subfrm(struct mdp_cmdq_cmd *cmd, if (ret) return ret; /* Wait components done */ - for (index = 0; index < config->num_components; index++) { + for (index = 0; index < num_comp; index++) { ctx = &path->comps[index]; - if (is_output_disabled(ctx->param, count)) + if (is_output_disabled(p_id, ctx->param, count)) continue; ret = call_op(ctx, wait_comp_event, cmd); if (ret) return ret; } /* Advance to the next sub-frame */ - for (index = 0; index < config->num_components; index++) { + for (index = 0; index < num_comp; index++) { ctx = &path->comps[index]; ret = call_op(ctx, advance_subfrm, cmd, count); if (ret) @@ -207,23 +236,35 @@ static int mdp_path_config_subfrm(struct mdp_cmdq_cmd *cmd, static int mdp_path_config(struct mdp_dev *mdp, struct mdp_cmdq_cmd *cmd, struct mdp_path *path) { - const struct img_config *config = path->config; + const int p_id = mdp->mdp_data->mdp_plat_id; struct mdp_comp_ctx *ctx; int index, count, ret; + u32 num_comp = 0; + u32 num_sub = 0; + + if (CFG_CHECK(MT8183, p_id)) + num_comp = CFG_GET(MT8183, path->config, num_components); + + if (CFG_CHECK(MT8183, p_id)) + num_sub = CFG_GET(MT8183, path->config, num_subfrms); /* Config path frame */ /* Reset components */ - for (index = 0; index < config->num_components; index++) { + for (index = 0; index < num_comp; index++) { ctx = &path->comps[index]; ret = call_op(ctx, init_comp, cmd); if (ret) return ret; } /* Config frame mode */ - for (index = 0; index < config->num_components; index++) { - const struct v4l2_rect *compose = - path->composes[ctx->param->outputs[0]]; + for (index = 0; index < num_comp; index++) { + const struct v4l2_rect *compose; + u32 out = 0; + + if (CFG_CHECK(MT8183, p_id)) + out = CFG_COMP(MT8183, ctx->param, outputs[0]); + compose = path->composes[out]; ctx = &path->comps[index]; ret = call_op(ctx, config_frame, cmd, compose); if (ret) @@ -231,13 +272,13 @@ static int mdp_path_config(struct mdp_dev *mdp, struct mdp_cmdq_cmd *cmd, } /* Config path sub-frames */ - for (count = 0; count < config->num_subfrms; count++) { + for (count = 0; count < num_sub; count++) { ret = mdp_path_config_subfrm(cmd, path, count); if (ret) return ret; } /* Post processing information */ - for (index = 0; index < config->num_components; index++) { + for (index = 0; index < num_comp; index++) { ctx = &path->comps[index]; ret = call_op(ctx, post_process, cmd); if (ret) @@ -361,7 +402,9 @@ int mdp_cmdq_send(struct mdp_dev *mdp, struct mdp_cmdq_param *param) struct mdp_cmdq_cmd *cmd = NULL; struct mdp_comp *comps = NULL; struct device *dev = &mdp->pdev->dev; + const int p_id = mdp->mdp_data->mdp_plat_id; int i, ret; + u32 num_comp = 0; atomic_inc(&mdp->job_count); if (atomic_read(&mdp->suspended)) { @@ -379,8 +422,13 @@ int mdp_cmdq_send(struct mdp_dev *mdp, struct mdp_cmdq_param *param) if (ret) goto err_free_cmd; - comps = kcalloc(param->config->num_components, sizeof(*comps), - GFP_KERNEL); + if (CFG_CHECK(MT8183, p_id)) { + num_comp = CFG_GET(MT8183, param->config, num_components); + } else { + ret = -EINVAL; + goto err_destroy_pkt; + } + comps = kcalloc(num_comp, sizeof(*comps), GFP_KERNEL); if (!comps) { ret = -ENOMEM; goto err_destroy_pkt; @@ -412,7 +460,6 @@ int mdp_cmdq_send(struct mdp_dev *mdp, struct mdp_cmdq_param *param) path->composes[i] = param->composes[i] ? param->composes[i] : &path->bounds[i]; } - ret = mdp_path_ctx_init(mdp, path); if (ret) { dev_err(dev, "mdp_path_ctx_init error\n"); @@ -426,7 +473,7 @@ int mdp_cmdq_send(struct mdp_dev *mdp, struct mdp_cmdq_param *param) } cmdq_pkt_finalize(&cmd->pkt); - for (i = 0; i < param->config->num_components; i++) + for (i = 0; i < num_comp; i++) memcpy(&comps[i], path->comps[i].comp, sizeof(struct mdp_comp)); @@ -435,7 +482,7 @@ int mdp_cmdq_send(struct mdp_dev *mdp, struct mdp_cmdq_param *param) cmd->user_cmdq_cb = param->cmdq_cb; cmd->user_cb_data = param->cb_data; cmd->comps = comps; - cmd->num_comps = param->config->num_components; + cmd->num_comps = num_comp; cmd->mdp_ctx = param->mdp_ctx; ret = mdp_comp_clocks_on(&mdp->pdev->dev, cmd->comps, cmd->num_comps); diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c index d9963f265a07..75c92e282fa2 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c @@ -20,6 +20,7 @@ #include "mdp_reg_wdma.h" static u32 mdp_comp_alias_id[MDP_COMP_TYPE_COUNT]; +static int p_id; static inline const struct mdp_platform_config * __get_plat_cfg(const struct mdp_comp_ctx *ctx) @@ -78,13 +79,13 @@ static int config_rdma_frame(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd, const struct v4l2_rect *compose) { - const struct mdp_rdma_data *rdma = &ctx->param->rdma; const struct mdp_platform_config *mdp_cfg = __get_plat_cfg(ctx); u32 colorformat = ctx->input->buffer.format.colorformat; bool block10bit = MDP_COLOR_IS_10BIT_PACKED(colorformat); bool en_ufo = MDP_COLOR_IS_UFP(colorformat); phys_addr_t base = ctx->comp->reg_base; u8 subsys_id = ctx->comp->subsys_id; + u32 reg = 0; if (mdp_cfg && mdp_cfg->rdma_support_10bit) { if (block10bit) @@ -102,49 +103,78 @@ static int config_rdma_frame(struct mdp_comp_ctx *ctx, 0x00030071); /* Setup source frame info */ - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_CON, rdma->src_ctrl, + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, rdma.src_ctrl); + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_CON, reg, 0x03C8FE0F); if (mdp_cfg) if (mdp_cfg->rdma_support_10bit && en_ufo) { /* Setup source buffer base */ + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, rdma.ufo_dec_y); MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_UFO_DEC_LENGTH_BASE_Y, - rdma->ufo_dec_y, 0xFFFFFFFF); + reg, 0xFFFFFFFF); + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, rdma.ufo_dec_c); MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_UFO_DEC_LENGTH_BASE_C, - rdma->ufo_dec_c, 0xFFFFFFFF); + reg, 0xFFFFFFFF); /* Set 10bit source frame pitch */ - if (block10bit) + if (block10bit) { + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, rdma.mf_bkgd_in_pxl); MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_MF_BKGD_SIZE_IN_PXL, - rdma->mf_bkgd_in_pxl, 0x001FFFFF); + reg, 0x001FFFFF); + } } - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_CON, rdma->control, + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, rdma.control); + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_CON, reg, 0x1110); /* Setup source buffer base */ - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_BASE_0, rdma->iova[0], + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, rdma.iova[0]); + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_BASE_0, reg, 0xFFFFFFFF); - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_BASE_1, rdma->iova[1], + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, rdma.iova[1]); + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_BASE_1, reg, 0xFFFFFFFF); - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_BASE_2, rdma->iova[2], + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, rdma.iova[2]); + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_BASE_2, reg, 0xFFFFFFFF); /* Setup source buffer end */ + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, rdma.iova_end[0]); MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_END_0, - rdma->iova_end[0], 0xFFFFFFFF); + reg, 0xFFFFFFFF); + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, rdma.iova_end[1]); MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_END_1, - rdma->iova_end[1], 0xFFFFFFFF); + reg, 0xFFFFFFFF); + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, rdma.iova_end[2]); MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_END_2, - rdma->iova_end[2], 0xFFFFFFFF); + reg, 0xFFFFFFFF); /* Setup source frame pitch */ + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, rdma.mf_bkgd); MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_MF_BKGD_SIZE_IN_BYTE, - rdma->mf_bkgd, 0x001FFFFF); + reg, 0x001FFFFF); + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, rdma.sf_bkgd); MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SF_BKGD_SIZE_IN_BYTE, - rdma->sf_bkgd, 0x001FFFFF); + reg, 0x001FFFFF); /* Setup color transform */ + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, rdma.transform); MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_TRANSFORM_0, - rdma->transform, 0x0F110000); + reg, 0x0F110000); return 0; } @@ -152,47 +182,67 @@ static int config_rdma_frame(struct mdp_comp_ctx *ctx, static int config_rdma_subfrm(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd, u32 index) { - const struct mdp_rdma_subfrm *subfrm = &ctx->param->rdma.subfrms[index]; - const struct img_comp_subfrm *csf = &ctx->param->subfrms[index]; const struct mdp_platform_config *mdp_cfg = __get_plat_cfg(ctx); u32 colorformat = ctx->input->buffer.format.colorformat; bool block10bit = MDP_COLOR_IS_10BIT_PACKED(colorformat); bool en_ufo = MDP_COLOR_IS_UFP(colorformat); phys_addr_t base = ctx->comp->reg_base; u8 subsys_id = ctx->comp->subsys_id; + u32 csf_l = 0, csf_r = 0; + u32 reg = 0; /* Enable RDMA */ MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_EN, BIT(0), BIT(0)); /* Set Y pixel offset */ + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].offset[0]); MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_OFFSET_0, - subfrm->offset[0], 0xFFFFFFFF); + reg, 0xFFFFFFFF); /* Set 10bit UFO mode */ - if (mdp_cfg) - if (mdp_cfg->rdma_support_10bit && block10bit && en_ufo) + if (mdp_cfg) { + if (mdp_cfg->rdma_support_10bit && block10bit && en_ufo) { + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].offset_0_p); MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_OFFSET_0_P, - subfrm->offset_0_p, 0xFFFFFFFF); + reg, 0xFFFFFFFF); + } + } /* Set U pixel offset */ + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].offset[1]); MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_OFFSET_1, - subfrm->offset[1], 0xFFFFFFFF); + reg, 0xFFFFFFFF); /* Set V pixel offset */ + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].offset[2]); MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_OFFSET_2, - subfrm->offset[2], 0xFFFFFFFF); + reg, 0xFFFFFFFF); /* Set source size */ - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_MF_SRC_SIZE, subfrm->src, + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].src); + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_MF_SRC_SIZE, reg, 0x1FFF1FFF); /* Set target size */ + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].clip); MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_MF_CLIP_SIZE, - subfrm->clip, 0x1FFF1FFF); + reg, 0x1FFF1FFF); /* Set crop offset */ + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].clip_ofst); MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_MF_OFFSET_1, - subfrm->clip_ofst, 0x003F001F); + reg, 0x003F001F); + if (CFG_CHECK(MT8183, p_id)) { + csf_l = CFG_COMP(MT8183, ctx->param, subfrms[index].in.left); + csf_r = CFG_COMP(MT8183, ctx->param, subfrms[index].in.right); + } if (mdp_cfg && mdp_cfg->rdma_upsample_repeat_only) - if ((csf->in.right - csf->in.left + 1) > 320) + if ((csf_r - csf_l + 1) > 320) MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_RESV_DUMMY_0, BIT(2), BIT(2)); @@ -240,63 +290,97 @@ static int config_rsz_frame(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd, const struct v4l2_rect *compose) { - const struct mdp_rsz_data *rsz = &ctx->param->rsz; phys_addr_t base = ctx->comp->reg_base; u8 subsys_id = ctx->comp->subsys_id; + bool bypass = FALSE; + u32 reg = 0; - if (ctx->param->frame.bypass) { + if (CFG_CHECK(MT8183, p_id)) + bypass = CFG_COMP(MT8183, ctx->param, frame.bypass); + + if (bypass) { /* Disable RSZ */ MM_REG_WRITE(cmd, subsys_id, base, PRZ_ENABLE, 0x0, BIT(0)); return 0; } - MM_REG_WRITE(cmd, subsys_id, base, PRZ_CONTROL_1, rsz->control1, + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, rsz.control1); + MM_REG_WRITE(cmd, subsys_id, base, PRZ_CONTROL_1, reg, 0x03FFFDF3); - MM_REG_WRITE(cmd, subsys_id, base, PRZ_CONTROL_2, rsz->control2, + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, rsz.control2); + MM_REG_WRITE(cmd, subsys_id, base, PRZ_CONTROL_2, reg, 0x0FFFC290); + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, rsz.coeff_step_x); MM_REG_WRITE(cmd, subsys_id, base, PRZ_HORIZONTAL_COEFF_STEP, - rsz->coeff_step_x, 0x007FFFFF); + reg, 0x007FFFFF); + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, rsz.coeff_step_y); MM_REG_WRITE(cmd, subsys_id, base, PRZ_VERTICAL_COEFF_STEP, - rsz->coeff_step_y, 0x007FFFFF); + reg, 0x007FFFFF); return 0; } static int config_rsz_subfrm(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd, u32 index) { - const struct mdp_rsz_subfrm *subfrm = &ctx->param->rsz.subfrms[index]; - const struct img_comp_subfrm *csf = &ctx->param->subfrms[index]; const struct mdp_platform_config *mdp_cfg = __get_plat_cfg(ctx); phys_addr_t base = ctx->comp->reg_base; u8 subsys_id = ctx->comp->subsys_id; + u32 csf_l = 0, csf_r = 0; + u32 reg = 0; - MM_REG_WRITE(cmd, subsys_id, base, PRZ_CONTROL_2, subfrm->control2, + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, rsz.subfrms[index].control2); + MM_REG_WRITE(cmd, subsys_id, base, PRZ_CONTROL_2, reg, 0x00003800); - MM_REG_WRITE(cmd, subsys_id, base, PRZ_INPUT_IMAGE, subfrm->src, + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, rsz.subfrms[index].src); + MM_REG_WRITE(cmd, subsys_id, base, PRZ_INPUT_IMAGE, reg, 0xFFFFFFFF); + if (CFG_CHECK(MT8183, p_id)) { + csf_l = CFG_COMP(MT8183, ctx->param, subfrms[index].in.left); + csf_r = CFG_COMP(MT8183, ctx->param, subfrms[index].in.right); + } if (mdp_cfg && mdp_cfg->rsz_disable_dcm_small_sample) - if ((csf->in.right - csf->in.left + 1) <= 16) + if ((csf_r - csf_l + 1) <= 16) MM_REG_WRITE(cmd, subsys_id, base, PRZ_CONTROL_1, BIT(27), BIT(27)); + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, subfrms[index].luma.left); MM_REG_WRITE(cmd, subsys_id, base, PRZ_LUMA_HORIZONTAL_INTEGER_OFFSET, - csf->luma.left, 0xFFFF); + reg, 0xFFFF); + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, subfrms[index].luma.left_subpix); MM_REG_WRITE(cmd, subsys_id, base, PRZ_LUMA_HORIZONTAL_SUBPIXEL_OFFSET, - csf->luma.left_subpix, 0x1FFFFF); + reg, 0x1FFFFF); + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, subfrms[index].luma.top); MM_REG_WRITE(cmd, subsys_id, base, PRZ_LUMA_VERTICAL_INTEGER_OFFSET, - csf->luma.top, 0xFFFF); + reg, 0xFFFF); + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, subfrms[index].luma.top_subpix); MM_REG_WRITE(cmd, subsys_id, base, PRZ_LUMA_VERTICAL_SUBPIXEL_OFFSET, - csf->luma.top_subpix, 0x1FFFFF); + reg, 0x1FFFFF); + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, subfrms[index].chroma.left); MM_REG_WRITE(cmd, subsys_id, base, PRZ_CHROMA_HORIZONTAL_INTEGER_OFFSET, - csf->chroma.left, 0xFFFF); + reg, 0xFFFF); + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, subfrms[index].chroma.left_subpix); MM_REG_WRITE(cmd, subsys_id, base, PRZ_CHROMA_HORIZONTAL_SUBPIXEL_OFFSET, - csf->chroma.left_subpix, 0x1FFFFF); + reg, 0x1FFFFF); - MM_REG_WRITE(cmd, subsys_id, base, PRZ_OUTPUT_IMAGE, subfrm->clip, + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, rsz.subfrms[index].clip); + MM_REG_WRITE(cmd, subsys_id, base, PRZ_OUTPUT_IMAGE, reg, 0xFFFFFFFF); return 0; @@ -308,11 +392,16 @@ static int advance_rsz_subfrm(struct mdp_comp_ctx *ctx, const struct mdp_platform_config *mdp_cfg = __get_plat_cfg(ctx); if (mdp_cfg && mdp_cfg->rsz_disable_dcm_small_sample) { - const struct img_comp_subfrm *csf = &ctx->param->subfrms[index]; phys_addr_t base = ctx->comp->reg_base; u8 subsys_id = ctx->comp->subsys_id; + u32 csf_l = 0, csf_r = 0; - if ((csf->in.right - csf->in.left + 1) <= 16) + if (CFG_CHECK(MT8183, p_id)) { + csf_l = CFG_COMP(MT8183, ctx->param, subfrms[index].in.left); + csf_r = CFG_COMP(MT8183, ctx->param, subfrms[index].in.right); + } + + if ((csf_r - csf_l + 1) <= 16) MM_REG_WRITE(cmd, subsys_id, base, PRZ_CONTROL_1, 0x0, BIT(27)); } @@ -345,31 +434,47 @@ static int config_wrot_frame(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd, const struct v4l2_rect *compose) { - const struct mdp_wrot_data *wrot = &ctx->param->wrot; const struct mdp_platform_config *mdp_cfg = __get_plat_cfg(ctx); phys_addr_t base = ctx->comp->reg_base; u8 subsys_id = ctx->comp->subsys_id; + u32 reg = 0; /* Write frame base address */ - MM_REG_WRITE(cmd, subsys_id, base, VIDO_BASE_ADDR, wrot->iova[0], + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, wrot.iova[0]); + MM_REG_WRITE(cmd, subsys_id, base, VIDO_BASE_ADDR, reg, 0xFFFFFFFF); - MM_REG_WRITE(cmd, subsys_id, base, VIDO_BASE_ADDR_C, wrot->iova[1], + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, wrot.iova[1]); + MM_REG_WRITE(cmd, subsys_id, base, VIDO_BASE_ADDR_C, reg, 0xFFFFFFFF); - MM_REG_WRITE(cmd, subsys_id, base, VIDO_BASE_ADDR_V, wrot->iova[2], + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, wrot.iova[2]); + MM_REG_WRITE(cmd, subsys_id, base, VIDO_BASE_ADDR_V, reg, 0xFFFFFFFF); /* Write frame related registers */ - MM_REG_WRITE(cmd, subsys_id, base, VIDO_CTRL, wrot->control, + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, wrot.control); + MM_REG_WRITE(cmd, subsys_id, base, VIDO_CTRL, reg, 0xF131510F); /* Write frame Y pitch */ - MM_REG_WRITE(cmd, subsys_id, base, VIDO_STRIDE, wrot->stride[0], + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, wrot.stride[0]); + MM_REG_WRITE(cmd, subsys_id, base, VIDO_STRIDE, reg, 0x0000FFFF); /* Write frame UV pitch */ - MM_REG_WRITE(cmd, subsys_id, base, VIDO_STRIDE_C, wrot->stride[1], + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, wrot.stride[1]); + MM_REG_WRITE(cmd, subsys_id, base, VIDO_STRIDE_C, reg, 0xFFFF); - MM_REG_WRITE(cmd, subsys_id, base, VIDO_STRIDE_V, wrot->stride[2], + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, wrot.stride[2]); + MM_REG_WRITE(cmd, subsys_id, base, VIDO_STRIDE_V, reg, 0xFFFF); /* Write matrix control */ - MM_REG_WRITE(cmd, subsys_id, base, VIDO_MAT_CTRL, wrot->mat_ctrl, 0xF3); + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, wrot.mat_ctrl); + MM_REG_WRITE(cmd, subsys_id, base, VIDO_MAT_CTRL, reg, 0xF3); /* Set the fixed ALPHA as 0xFF */ MM_REG_WRITE(cmd, subsys_id, base, VIDO_DITHER, 0xFF000000, @@ -377,13 +482,18 @@ static int config_wrot_frame(struct mdp_comp_ctx *ctx, /* Set VIDO_EOL_SEL */ MM_REG_WRITE(cmd, subsys_id, base, VIDO_RSV_1, BIT(31), BIT(31)); /* Set VIDO_FIFO_TEST */ - if (wrot->fifo_test != 0) + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, wrot.fifo_test); + if (reg != 0) MM_REG_WRITE(cmd, subsys_id, base, VIDO_FIFO_TEST, - wrot->fifo_test, 0xFFF); + reg, 0xFFF); /* Filter enable */ - if (mdp_cfg && mdp_cfg->wrot_filter_constraint) + if (mdp_cfg && mdp_cfg->wrot_filter_constraint) { + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, wrot.filter); MM_REG_WRITE(cmd, subsys_id, base, VIDO_MAIN_BUF_SIZE, - wrot->filter, 0x77); + reg, 0x77); + } return 0; } @@ -391,30 +501,44 @@ static int config_wrot_frame(struct mdp_comp_ctx *ctx, static int config_wrot_subfrm(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd, u32 index) { - const struct mdp_wrot_subfrm *subfrm = &ctx->param->wrot.subfrms[index]; phys_addr_t base = ctx->comp->reg_base; u8 subsys_id = ctx->comp->subsys_id; + u32 reg = 0; /* Write Y pixel offset */ + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].offset[0]); MM_REG_WRITE(cmd, subsys_id, base, VIDO_OFST_ADDR, - subfrm->offset[0], 0x0FFFFFFF); + reg, 0x0FFFFFFF); /* Write U pixel offset */ + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].offset[1]); MM_REG_WRITE(cmd, subsys_id, base, VIDO_OFST_ADDR_C, - subfrm->offset[1], 0x0FFFFFFF); + reg, 0x0FFFFFFF); /* Write V pixel offset */ + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].offset[2]); MM_REG_WRITE(cmd, subsys_id, base, VIDO_OFST_ADDR_V, - subfrm->offset[2], 0x0FFFFFFF); + reg, 0x0FFFFFFF); /* Write source size */ - MM_REG_WRITE(cmd, subsys_id, base, VIDO_IN_SIZE, subfrm->src, + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].src); + MM_REG_WRITE(cmd, subsys_id, base, VIDO_IN_SIZE, reg, 0x1FFF1FFF); /* Write target size */ - MM_REG_WRITE(cmd, subsys_id, base, VIDO_TAR_SIZE, subfrm->clip, + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].clip); + MM_REG_WRITE(cmd, subsys_id, base, VIDO_TAR_SIZE, reg, 0x1FFF1FFF); - MM_REG_WRITE(cmd, subsys_id, base, VIDO_CROP_OFST, subfrm->clip_ofst, + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].clip_ofst); + MM_REG_WRITE(cmd, subsys_id, base, VIDO_CROP_OFST, reg, 0x1FFF1FFF); + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].main_buf); MM_REG_WRITE(cmd, subsys_id, base, VIDO_MAIN_BUF_SIZE, - subfrm->main_buf, 0x1FFF7F00); + reg, 0x1FFF7F00); /* Enable WROT */ MM_REG_WRITE(cmd, subsys_id, base, VIDO_ROT_EN, BIT(0), BIT(0)); @@ -468,29 +592,41 @@ static int config_wdma_frame(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd, const struct v4l2_rect *compose) { - const struct mdp_wdma_data *wdma = &ctx->param->wdma; phys_addr_t base = ctx->comp->reg_base; u8 subsys_id = ctx->comp->subsys_id; + u32 reg = 0; MM_REG_WRITE(cmd, subsys_id, base, WDMA_BUF_CON2, 0x10101050, 0xFFFFFFFF); /* Setup frame information */ - MM_REG_WRITE(cmd, subsys_id, base, WDMA_CFG, wdma->wdma_cfg, + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, wdma.wdma_cfg); + MM_REG_WRITE(cmd, subsys_id, base, WDMA_CFG, reg, 0x0F01B8F0); /* Setup frame base address */ - MM_REG_WRITE(cmd, subsys_id, base, WDMA_DST_ADDR, wdma->iova[0], + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, wdma.iova[0]); + MM_REG_WRITE(cmd, subsys_id, base, WDMA_DST_ADDR, reg, 0xFFFFFFFF); - MM_REG_WRITE(cmd, subsys_id, base, WDMA_DST_U_ADDR, wdma->iova[1], + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, wdma.iova[1]); + MM_REG_WRITE(cmd, subsys_id, base, WDMA_DST_U_ADDR, reg, 0xFFFFFFFF); - MM_REG_WRITE(cmd, subsys_id, base, WDMA_DST_V_ADDR, wdma->iova[2], + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, wdma.iova[2]); + MM_REG_WRITE(cmd, subsys_id, base, WDMA_DST_V_ADDR, reg, 0xFFFFFFFF); /* Setup Y pitch */ + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, wdma.w_in_byte); MM_REG_WRITE(cmd, subsys_id, base, WDMA_DST_W_IN_BYTE, - wdma->w_in_byte, 0x0000FFFF); + reg, 0x0000FFFF); /* Setup UV pitch */ + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, wdma.uv_stride); MM_REG_WRITE(cmd, subsys_id, base, WDMA_DST_UV_PITCH, - wdma->uv_stride, 0x0000FFFF); + reg, 0x0000FFFF); /* Set the fixed ALPHA as 0xFF */ MM_REG_WRITE(cmd, subsys_id, base, WDMA_ALPHA, 0x800000FF, 0x800000FF); @@ -501,27 +637,39 @@ static int config_wdma_frame(struct mdp_comp_ctx *ctx, static int config_wdma_subfrm(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd, u32 index) { - const struct mdp_wdma_subfrm *subfrm = &ctx->param->wdma.subfrms[index]; phys_addr_t base = ctx->comp->reg_base; u8 subsys_id = ctx->comp->subsys_id; + u32 reg = 0; /* Write Y pixel offset */ + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, wdma.subfrms[index].offset[0]); MM_REG_WRITE(cmd, subsys_id, base, WDMA_DST_ADDR_OFFSET, - subfrm->offset[0], 0x0FFFFFFF); + reg, 0x0FFFFFFF); /* Write U pixel offset */ + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, wdma.subfrms[index].offset[1]); MM_REG_WRITE(cmd, subsys_id, base, WDMA_DST_U_ADDR_OFFSET, - subfrm->offset[1], 0x0FFFFFFF); + reg, 0x0FFFFFFF); /* Write V pixel offset */ + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, wdma.subfrms[index].offset[2]); MM_REG_WRITE(cmd, subsys_id, base, WDMA_DST_V_ADDR_OFFSET, - subfrm->offset[2], 0x0FFFFFFF); + reg, 0x0FFFFFFF); /* Write source size */ - MM_REG_WRITE(cmd, subsys_id, base, WDMA_SRC_SIZE, subfrm->src, + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, wdma.subfrms[index].src); + MM_REG_WRITE(cmd, subsys_id, base, WDMA_SRC_SIZE, reg, 0x3FFF3FFF); /* Write target size */ - MM_REG_WRITE(cmd, subsys_id, base, WDMA_CLIP_SIZE, subfrm->clip, + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, wdma.subfrms[index].clip); + MM_REG_WRITE(cmd, subsys_id, base, WDMA_CLIP_SIZE, reg, 0x3FFF3FFF); /* Write clip offset */ - MM_REG_WRITE(cmd, subsys_id, base, WDMA_CLIP_COORD, subfrm->clip_ofst, + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, wdma.subfrms[index].clip_ofst); + MM_REG_WRITE(cmd, subsys_id, base, WDMA_CLIP_COORD, reg, 0x3FFF3FFF); /* Enable WDMA */ @@ -564,13 +712,21 @@ static int init_ccorr(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd) static int config_ccorr_subfrm(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd, u32 index) { - const struct img_comp_subfrm *csf = &ctx->param->subfrms[index]; phys_addr_t base = ctx->comp->reg_base; u8 subsys_id = ctx->comp->subsys_id; + u32 csf_l = 0, csf_r = 0; + u32 csf_t = 0, csf_b = 0; u32 hsize, vsize; - hsize = csf->in.right - csf->in.left + 1; - vsize = csf->in.bottom - csf->in.top + 1; + if (CFG_CHECK(MT8183, p_id)) { + csf_l = CFG_COMP(MT8183, ctx->param, subfrms[index].in.left); + csf_r = CFG_COMP(MT8183, ctx->param, subfrms[index].in.right); + csf_t = CFG_COMP(MT8183, ctx->param, subfrms[index].in.top); + csf_b = CFG_COMP(MT8183, ctx->param, subfrms[index].in.bottom); + } + + hsize = csf_r - csf_l + 1; + vsize = csf_b - csf_t + 1; MM_REG_WRITE(cmd, subsys_id, base, MDP_CCORR_SIZE, (hsize << 16) + (vsize << 0), 0x1FFF1FFF); return 0; @@ -939,6 +1095,7 @@ int mdp_comp_config(struct mdp_dev *mdp) int ret; memset(mdp_comp_alias_id, 0, sizeof(mdp_comp_alias_id)); + p_id = mdp->mdp_data->mdp_plat_id; parent = dev->of_node->parent; /* Iterate over sibling MDP function blocks */ @@ -998,9 +1155,19 @@ int mdp_comp_ctx_config(struct mdp_dev *mdp, struct mdp_comp_ctx *ctx, { struct device *dev = &mdp->pdev->dev; enum mtk_mdp_comp_id public_id = MDP_COMP_NONE; - int i; + u32 arg; + int i, idx; - public_id = mdp_cfg_get_id_public(mdp, param->type); + if (!param) { + dev_err(dev, "Invalid component param"); + return -EINVAL; + } + + if (CFG_CHECK(MT8183, p_id)) + arg = CFG_COMP(MT8183, param, type); + else + return -EINVAL; + public_id = mdp_cfg_get_id_public(mdp, arg); if (public_id < 0) { dev_err(dev, "Invalid component id %d", public_id); return -EINVAL; @@ -1008,13 +1175,26 @@ int mdp_comp_ctx_config(struct mdp_dev *mdp, struct mdp_comp_ctx *ctx, ctx->comp = mdp->comp[public_id]; if (!ctx->comp) { - dev_err(dev, "Uninit component inner id %d", param->type); + dev_err(dev, "Uninit component inner id %d", arg); return -EINVAL; } ctx->param = param; - ctx->input = &frame->inputs[param->input]; - for (i = 0; i < param->num_outputs; i++) - ctx->outputs[i] = &frame->outputs[param->outputs[i]]; + if (CFG_CHECK(MT8183, p_id)) + arg = CFG_COMP(MT8183, param, input); + else + return -EINVAL; + ctx->input = &frame->inputs[arg]; + if (CFG_CHECK(MT8183, p_id)) + idx = CFG_COMP(MT8183, param, num_outputs); + else + return -EINVAL; + for (i = 0; i < idx; i++) { + if (CFG_CHECK(MT8183, p_id)) + arg = CFG_COMP(MT8183, param, outputs[i]); + else + return -EINVAL; + ctx->outputs[i] = &frame->outputs[arg]; + } return 0; } diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h index 59a1c88d8184..7e21d226ceb8 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h @@ -51,6 +51,7 @@ enum mdp_pipe_id { }; struct mtk_mdp_driver_data { + const int mdp_plat_id; const struct of_device_id *mdp_probe_infra; const struct mdp_platform_config *mdp_cfg; const u32 *mdp_mutex_table_idx; From patchwork Mon Mar 27 03:13:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Moudy Ho X-Patchwork-Id: 667733 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 38442C77B71 for ; Mon, 27 Mar 2023 03:14:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232314AbjC0DOn (ORCPT ); Sun, 26 Mar 2023 23:14:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48694 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232318AbjC0DON (ORCPT ); Sun, 26 Mar 2023 23:14:13 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3F90449D4; Sun, 26 Mar 2023 20:13:50 -0700 (PDT) X-UUID: 5e9fba8ecc4d11edb6b9f13eb10bd0fe-20230327 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=jSagPzDdp3s9C8kqWieBA8h2cxt7J5Zsd2dAJbKfjEY=; b=P1CfO+FB53j9T7ff70BMPKDtrarcpnZHzbtgbBrhGfvyF6IHkCpNPDaPHz4Qt6o3Bdt2JOr7NXgw6lebdHJK/mo2durZ/Bg2/yU6JWhgNCAYiPZQvi6qWR9MESGmZxOeHe4kExofFVmnWoij2pMNnsk6Q7PsxPeXWy9TEGoBs0c=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.22, REQID:55c96e31-1cf7-41f4-8c74-336666175ecf, IP:0, U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-25 X-CID-META: VersionHash:120426c, CLOUDID:bff870b4-beed-4dfc-bd9c-e1b22fa6ccc4, B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-UUID: 5e9fba8ecc4d11edb6b9f13eb10bd0fe-20230327 Received: from mtkmbs13n2.mediatek.inc [(172.21.101.108)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1501530321; Mon, 27 Mar 2023 11:13:39 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.25; Mon, 27 Mar 2023 11:13:37 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.25 via Frontend Transport; Mon, 27 Mar 2023 11:13:37 +0800 From: Moudy Ho To: Mauro Carvalho Chehab , Matthias Brugger , Hans Verkuil , Ping-Hsun Wu CC: , , , , , Moudy Ho Subject: [PATCH v7 12/12] media: platform: mtk-mdp3: reconfigure shared memory Date: Mon, 27 Mar 2023 11:13:35 +0800 Message-ID: <20230327031335.9663-13-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230327031335.9663-1-moudy.ho@mediatek.com> References: <20230327031335.9663-1-moudy.ho@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org For performance and multi-chip support, use dynamic layout instead of statically configured pools. Divide the shared memory into the 3 64-bit aligned layouts listed below: vpu->param_addr -> +-----------------------------------------+ | | | To SCP : Input frame parameters | | (struct img_ipi_frameparam) | | | +-----------------------------------------+ vpu->work_addr -> +-----------------------------------------+ | | | In SCP : Reserve for SCP calculation | | | +-----------------------------------------+ vpu->config_addr -> +-----------------------------------------+ | | | From SCP : Output component config | | (struct img_config) | | | +-----------------------------------------+ Signed-off-by: Moudy Ho --- .../platform/mediatek/mdp3/mdp_sm_mt8183.h | 4 +- .../platform/mediatek/mdp3/mtk-mdp3-m2m.c | 13 +- .../platform/mediatek/mdp3/mtk-mdp3-m2m.h | 1 - .../platform/mediatek/mdp3/mtk-mdp3-vpu.c | 193 ++++++++---------- .../platform/mediatek/mdp3/mtk-mdp3-vpu.h | 29 +-- 5 files changed, 95 insertions(+), 145 deletions(-) diff --git a/drivers/media/platform/mediatek/mdp3/mdp_sm_mt8183.h b/drivers/media/platform/mediatek/mdp3/mdp_sm_mt8183.h index effc75615af9..85637084520f 100644 --- a/drivers/media/platform/mediatek/mdp3/mdp_sm_mt8183.h +++ b/drivers/media/platform/mediatek/mdp3/mdp_sm_mt8183.h @@ -11,8 +11,8 @@ /* * ISP-MDP generic output information - * MD5 of the target SCP blob: - * 6da52bdcf4bf76a0983b313e1d4745d6 + * MD5 of the target SCP prebuild: + * 2d995ddb5c3b0cf26e96d6a823481886 */ #define IMG_MAX_SUBFRAMES_8183 14 diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-m2m.c b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-m2m.c index 27e1b1b8c6b4..a298c1b15b9e 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-m2m.c +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-m2m.c @@ -87,14 +87,14 @@ static void mdp_m2m_device_run(void *priv) dst_vb = v4l2_m2m_next_dst_buf(ctx->m2m_ctx); mdp_set_dst_config(¶m.outputs[0], frame, &dst_vb->vb2_buf); - ret = mdp_vpu_process(&ctx->vpu, ¶m); + ret = mdp_vpu_process(&ctx->mdp_dev->vpu, ¶m); if (ret) { dev_err(&ctx->mdp_dev->pdev->dev, "VPU MDP process failed: %d\n", ret); goto worker_end; } - task.config = ctx->vpu.config; + task.config = ctx->mdp_dev->vpu.config; task.param = ¶m; task.composes[0] = &frame->compose; task.cmdq_cb = NULL; @@ -150,11 +150,6 @@ static int mdp_m2m_start_streaming(struct vb2_queue *q, unsigned int count) if (!mdp_m2m_ctx_is_state_set(ctx, MDP_VPU_INIT)) { ret = mdp_vpu_get_locked(ctx->mdp_dev); - if (ret) - return ret; - - ret = mdp_vpu_ctx_init(&ctx->vpu, &ctx->mdp_dev->vpu, - MDP_DEV_M2M); if (ret) { dev_err(&ctx->mdp_dev->pdev->dev, "VPU init failed %d\n", ret); @@ -641,10 +636,8 @@ static int mdp_m2m_release(struct file *file) mutex_lock(&mdp->m2m_lock); v4l2_m2m_ctx_release(ctx->m2m_ctx); - if (mdp_m2m_ctx_is_state_set(ctx, MDP_VPU_INIT)) { - mdp_vpu_ctx_deinit(&ctx->vpu); + if (mdp_m2m_ctx_is_state_set(ctx, MDP_VPU_INIT)) mdp_vpu_put_locked(mdp); - } v4l2_ctrl_handler_free(&ctx->ctrl_handler); v4l2_fh_del(&ctx->fh); diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-m2m.h b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-m2m.h index 61ddbaf1bf13..dfc59e5b3b87 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-m2m.h +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-m2m.h @@ -33,7 +33,6 @@ struct mdp_m2m_ctx { struct v4l2_ctrl_handler ctrl_handler; struct mdp_m2m_ctrls ctrls; struct v4l2_m2m_ctx *m2m_ctx; - struct mdp_vpu_ctx vpu; u32 frame_count[MDP_M2M_MAX]; struct mdp_frameparam curr_param; diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c index a72bed927bb6..49fc2e9d45dd 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c @@ -10,7 +10,6 @@ #include "mtk-mdp3-core.h" #define MDP_VPU_MESSAGE_TIMEOUT 500U -#define vpu_alloc_size 0x600000 static inline struct mdp_dev *vpu_to_mdp(struct mdp_vpu_dev *vpu) { @@ -19,23 +18,63 @@ static inline struct mdp_dev *vpu_to_mdp(struct mdp_vpu_dev *vpu) static int mdp_vpu_shared_mem_alloc(struct mdp_vpu_dev *vpu) { - if (vpu->work && vpu->work_addr) - return 0; + struct device *dev; - vpu->work = dma_alloc_coherent(scp_get_device(vpu->scp), vpu_alloc_size, - &vpu->work_addr, GFP_KERNEL); + if (IS_ERR_OR_NULL(vpu)) + goto err_return; - if (!vpu->work) - return -ENOMEM; - else - return 0; + dev = scp_get_device(vpu->scp); + + if (!vpu->param) { + vpu->param = dma_alloc_wc(dev, vpu->param_size, + &vpu->param_addr, GFP_KERNEL); + if (!vpu->param) + goto err_return; + } + + if (!vpu->work) { + vpu->work = dma_alloc_wc(dev, vpu->work_size, + &vpu->work_addr, GFP_KERNEL); + if (!vpu->work) + goto err_free_param; + } + + if (!vpu->config) { + vpu->config = dma_alloc_wc(dev, vpu->config_size, + &vpu->config_addr, GFP_KERNEL); + if (!vpu->config) + goto err_free_work; + } + + return 0; + +err_free_work: + dma_free_wc(dev, vpu->work_size, vpu->work, vpu->work_addr); + vpu->work = NULL; +err_free_param: + dma_free_wc(dev, vpu->param_size, vpu->param, vpu->param_addr); + vpu->param = NULL; +err_return: + return -ENOMEM; } void mdp_vpu_shared_mem_free(struct mdp_vpu_dev *vpu) { + struct device *dev; + + if (IS_ERR_OR_NULL(vpu)) + return; + + dev = scp_get_device(vpu->scp); + + if (vpu->param && vpu->param_addr) + dma_free_wc(dev, vpu->param_size, vpu->param, vpu->param_addr); + if (vpu->work && vpu->work_addr) - dma_free_coherent(scp_get_device(vpu->scp), vpu_alloc_size, - vpu->work, vpu->work_addr); + dma_free_wc(dev, vpu->work_size, vpu->work, vpu->work_addr); + + if (vpu->config && vpu->config_addr) + dma_free_wc(dev, vpu->config_size, vpu->config, vpu->config_addr); } static void mdp_vpu_ipi_handle_init_ack(void *data, unsigned int len, @@ -69,16 +108,16 @@ static void mdp_vpu_ipi_handle_frame_ack(void *data, unsigned int len, struct img_sw_addr *addr = (struct img_sw_addr *)data; struct img_ipi_frameparam *param = (struct img_ipi_frameparam *)(unsigned long)addr->va; - struct mdp_vpu_ctx *ctx = - (struct mdp_vpu_ctx *)(unsigned long)param->drv_data; + struct mdp_vpu_dev *vpu = + (struct mdp_vpu_dev *)(unsigned long)param->drv_data; if (param->state) { - struct mdp_dev *mdp = vpu_to_mdp(ctx->vpu_dev); + struct mdp_dev *mdp = vpu_to_mdp(vpu); dev_err(&mdp->pdev->dev, "VPU MDP failure:%d\n", param->state); } - ctx->vpu_dev->status = param->state; - complete(&ctx->vpu_dev->ipi_acked); + vpu->status = param->state; + complete(&vpu->ipi_acked); } int mdp_vpu_register(struct mdp_dev *mdp) @@ -157,9 +196,6 @@ int mdp_vpu_dev_init(struct mdp_vpu_dev *vpu, struct mtk_scp *scp, struct mdp_ipi_init_msg msg = { .drv_data = (unsigned long)vpu, }; - size_t mem_size; - phys_addr_t pool; - const size_t pool_size = sizeof(struct mdp_config_pool); struct mdp_dev *mdp = vpu_to_mdp(vpu); int err; @@ -172,34 +208,29 @@ int mdp_vpu_dev_init(struct mdp_vpu_dev *vpu, struct mtk_scp *scp, goto err_work_size; /* vpu work_size was set in mdp_vpu_ipi_handle_init_ack */ - mem_size = vpu_alloc_size; + mutex_lock(vpu->lock); + vpu->work_size = ALIGN(vpu->work_size, 64); + vpu->param_size = ALIGN(sizeof(struct img_ipi_frameparam), 64); + vpu->config_size = ALIGN(sizeof(struct img_config), 64); err = mdp_vpu_shared_mem_alloc(vpu); + mutex_unlock(vpu->lock); if (err) { dev_err(&mdp->pdev->dev, "VPU memory alloc fail!"); goto err_mem_alloc; } - pool = ALIGN((uintptr_t)vpu->work + vpu->work_size, 8); - if (pool + pool_size - (uintptr_t)vpu->work > mem_size) { - dev_err(&mdp->pdev->dev, - "VPU memory insufficient: %zx + %zx > %zx", - vpu->work_size, pool_size, mem_size); - err = -ENOMEM; - goto err_mem_size; - } - dev_dbg(&mdp->pdev->dev, - "VPU work:%pK pa:%pad sz:%zx pool:%pa sz:%zx (mem sz:%zx)", + "VPU param:%pK pa:%pad sz:%zx, work:%pK pa:%pad sz:%zx, config:%pK pa:%pad sz:%zx", + vpu->param, &vpu->param_addr, vpu->param_size, vpu->work, &vpu->work_addr, vpu->work_size, - &pool, pool_size, mem_size); - vpu->pool = (struct mdp_config_pool *)(uintptr_t)pool; + vpu->config, &vpu->config_addr, vpu->config_size); + msg.work_addr = vpu->work_addr; msg.work_size = vpu->work_size; err = mdp_vpu_sendmsg(vpu, SCP_IPI_MDP_INIT, &msg, sizeof(msg)); if (err) goto err_work_size; - memset(vpu->pool, 0, sizeof(*vpu->pool)); return 0; err_work_size: @@ -212,7 +243,6 @@ int mdp_vpu_dev_init(struct mdp_vpu_dev *vpu, struct mtk_scp *scp, break; } return err; -err_mem_size: err_mem_alloc: return err; } @@ -227,88 +257,31 @@ int mdp_vpu_dev_deinit(struct mdp_vpu_dev *vpu) return mdp_vpu_sendmsg(vpu, SCP_IPI_MDP_DEINIT, &msg, sizeof(msg)); } -static struct img_config *mdp_config_get(struct mdp_vpu_dev *vpu, - enum mdp_config_id id, uint32_t *addr) +int mdp_vpu_process(struct mdp_vpu_dev *vpu, struct img_ipi_frameparam *param) { - struct img_config *config; - - if (id < 0 || id >= MDP_CONFIG_POOL_SIZE) - return ERR_PTR(-EINVAL); + struct mdp_dev *mdp = vpu_to_mdp(vpu); + struct img_sw_addr addr; mutex_lock(vpu->lock); - vpu->pool->cfg_count[id]++; - config = &vpu->pool->configs[id]; - *addr = vpu->work_addr + ((uintptr_t)config - (uintptr_t)vpu->work); - mutex_unlock(vpu->lock); - - return config; -} - -static int mdp_config_put(struct mdp_vpu_dev *vpu, - enum mdp_config_id id, - const struct img_config *config) -{ - int err = 0; - - if (id < 0 || id >= MDP_CONFIG_POOL_SIZE) - return -EINVAL; - if (vpu->lock) - mutex_lock(vpu->lock); - if (!vpu->pool->cfg_count[id] || config != &vpu->pool->configs[id]) - err = -EINVAL; - else - vpu->pool->cfg_count[id]--; - if (vpu->lock) + if (mdp_vpu_shared_mem_alloc(vpu)) { + dev_err(&mdp->pdev->dev, "VPU memory alloc fail!"); mutex_unlock(vpu->lock); - return err; -} - -int mdp_vpu_ctx_init(struct mdp_vpu_ctx *ctx, struct mdp_vpu_dev *vpu, - enum mdp_config_id id) -{ - ctx->config = mdp_config_get(vpu, id, &ctx->inst_addr); - if (IS_ERR(ctx->config)) { - int err = PTR_ERR(ctx->config); - - ctx->config = NULL; - return err; + return -ENOMEM; } - ctx->config_id = id; - ctx->vpu_dev = vpu; - return 0; -} -int mdp_vpu_ctx_deinit(struct mdp_vpu_ctx *ctx) -{ - int err = mdp_config_put(ctx->vpu_dev, ctx->config_id, ctx->config); + memset(vpu->param, 0, vpu->param_size); + memset(vpu->work, 0, vpu->work_size); + memset(vpu->config, 0, vpu->config_size); - ctx->config_id = 0; - ctx->config = NULL; - ctx->inst_addr = 0; - return err; -} + param->self_data.va = (unsigned long)vpu->work; + param->self_data.pa = vpu->work_addr; + param->config_data.va = (unsigned long)vpu->config; + param->config_data.pa = vpu->config_addr; + param->drv_data = (unsigned long)vpu; + memcpy(vpu->param, param, sizeof(*param)); -int mdp_vpu_process(struct mdp_vpu_ctx *ctx, struct img_ipi_frameparam *param) -{ - struct mdp_vpu_dev *vpu = ctx->vpu_dev; - struct mdp_dev *mdp = vpu_to_mdp(vpu); - struct img_sw_addr addr; - - if (!ctx->vpu_dev->work || !ctx->vpu_dev->work_addr) { - if (mdp_vpu_shared_mem_alloc(vpu)) { - dev_err(&mdp->pdev->dev, "VPU memory alloc fail!"); - return -ENOMEM; - } - } - memset((void *)ctx->vpu_dev->work, 0, ctx->vpu_dev->work_size); - memset(ctx->config, 0, sizeof(*ctx->config)); - param->config_data.va = (unsigned long)ctx->config; - param->config_data.pa = ctx->inst_addr; - param->drv_data = (unsigned long)ctx; - - memcpy((void *)ctx->vpu_dev->work, param, sizeof(*param)); - addr.pa = ctx->vpu_dev->work_addr; - addr.va = (uintptr_t)ctx->vpu_dev->work; - return mdp_vpu_sendmsg(ctx->vpu_dev, SCP_IPI_MDP_FRAME, - &addr, sizeof(addr)); + addr.pa = vpu->param_addr; + addr.va = (unsigned long)vpu->param; + mutex_unlock(vpu->lock); + return mdp_vpu_sendmsg(vpu, SCP_IPI_MDP_FRAME, &addr, sizeof(addr)); } diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.h b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.h index 244b3a32d689..ad3551bc0730 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.h +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.h @@ -37,42 +37,27 @@ struct mdp_ipi_deinit_msg { u32 work_addr; } __packed; -enum mdp_config_id { - MDP_DEV_M2M = 0, - MDP_CONFIG_POOL_SIZE /* ALWAYS keep at the end */ -}; - -struct mdp_config_pool { - u64 cfg_count[MDP_CONFIG_POOL_SIZE]; - struct img_config configs[MDP_CONFIG_POOL_SIZE]; -}; - struct mdp_vpu_dev { /* synchronization protect for accessing vpu working buffer info */ struct mutex *lock; struct mtk_scp *scp; struct completion ipi_acked; + void *param; + dma_addr_t param_addr; + size_t param_size; void *work; dma_addr_t work_addr; size_t work_size; - struct mdp_config_pool *pool; + void *config; + dma_addr_t config_addr; + size_t config_size; u32 status; }; -struct mdp_vpu_ctx { - struct mdp_vpu_dev *vpu_dev; - u32 config_id; - struct img_config *config; - u32 inst_addr; -}; - void mdp_vpu_shared_mem_free(struct mdp_vpu_dev *vpu); int mdp_vpu_dev_init(struct mdp_vpu_dev *vpu, struct mtk_scp *scp, struct mutex *lock /* for sync */); int mdp_vpu_dev_deinit(struct mdp_vpu_dev *vpu); -int mdp_vpu_ctx_init(struct mdp_vpu_ctx *ctx, struct mdp_vpu_dev *vpu, - enum mdp_config_id id); -int mdp_vpu_ctx_deinit(struct mdp_vpu_ctx *ctx); -int mdp_vpu_process(struct mdp_vpu_ctx *vpu, struct img_ipi_frameparam *param); +int mdp_vpu_process(struct mdp_vpu_dev *vpu, struct img_ipi_frameparam *param); #endif /* __MTK_MDP3_VPU_H__ */