From patchwork Thu Mar 23 12:29:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dhruva Gole X-Patchwork-Id: 666380 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 685AFC6FD1C for ; Thu, 23 Mar 2023 12:29:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230496AbjCWM3s (ORCPT ); Thu, 23 Mar 2023 08:29:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54248 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230216AbjCWM3r (ORCPT ); Thu, 23 Mar 2023 08:29:47 -0400 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 66856868B; Thu, 23 Mar 2023 05:29:44 -0700 (PDT) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 32NCTfn5129015; Thu, 23 Mar 2023 07:29:41 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1679574581; bh=WBtmHvLCnXFwimXJYXKj87tMDRRpgcs5A8ej9EYRbcw=; h=From:To:CC:Subject:Date; b=Daf6nrkjTVha6r2zrZ8D7JAq9IT5+ZVwIsW4AVEK16LcophOYeNO34mvWXZxgbxF7 zCzhq7w1fAw/g8xvkOU2hI0Evnadw2Z+fkawrikWqVsvMUZO9/sG9uiJOxs/Klq5kv 6P9Svc3j9Mmv5LQc/K06iO0fx3QnErazY2JdWdvE= Received: from DLEE102.ent.ti.com (dlee102.ent.ti.com [157.170.170.32]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 32NCTfU1031374 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 23 Mar 2023 07:29:41 -0500 Received: from DLEE103.ent.ti.com (157.170.170.33) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Thu, 23 Mar 2023 07:29:41 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Thu, 23 Mar 2023 07:29:41 -0500 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 32NCTeVY010812; Thu, 23 Mar 2023 07:29:40 -0500 From: Dhruva Gole To: Keerthy CC: Vibhore Vardhan , Dhruva Gole , Tony Lindgren , Vignesh , Linus Walleij , Bartosz Golaszewski , , , Devarsh Thakkar Subject: [RFC PATCH 1/2] gpio: davinci: Do not clear the bank intr enable bit in save_context Date: Thu, 23 Mar 2023 17:59:09 +0530 Message-ID: <20230323122910.991148-1-d-gole@ti.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The interrupt enable bits might be set if we want to use the GPIO as wakeup source. Clearing this will mean disabling of interrupts in the GPIO banks that we may want to wakeup from. Thus remove the line that was clearing this bit from the driver's save context function. Fixes: 0651a730924b ("gpio: davinci: Add support for system suspend/resume PM") Cc: Devarsh Thakkar Signed-off-by: Dhruva Gole Reviewed-by: Linus Walleij Acked-by: Keerthy --- drivers/gpio/gpio-davinci.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpio/gpio-davinci.c b/drivers/gpio/gpio-davinci.c index 7fc83057990a..d7595b39e8c4 100644 --- a/drivers/gpio/gpio-davinci.c +++ b/drivers/gpio/gpio-davinci.c @@ -639,9 +639,6 @@ static void davinci_gpio_save_context(struct davinci_gpio_controller *chips, context->set_falling = readl_relaxed(&g->set_falling); } - /* Clear Bank interrupt enable bit */ - writel_relaxed(0, base + BINTEN); - /* Clear all interrupt status registers */ writel_relaxed(GENMASK(31, 0), &g->intstat); } From patchwork Thu Mar 23 12:29:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dhruva Gole X-Patchwork-Id: 667093 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9AFE2C6FD1D for ; Thu, 23 Mar 2023 12:29:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231449AbjCWM3x (ORCPT ); Thu, 23 Mar 2023 08:29:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54346 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231357AbjCWM3v (ORCPT ); Thu, 23 Mar 2023 08:29:51 -0400 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9AB0386B6; Thu, 23 Mar 2023 05:29:47 -0700 (PDT) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 32NCTjRY129022; Thu, 23 Mar 2023 07:29:45 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1679574585; bh=jfAz3nNZtnM8wt/Xe8+Ol2GrO9qEEqrh7IFYH6+9tvI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=F4Npmk6XB15R4qhvjoMrOsFj1MLYc5fT2eYdcJXhvxjU1PvnRxBi9DZ7FK6YcOO38 5lYLSRZ6J13inonE9vkRHgUxX3dDYuk1Ao65MYd5pAFMya7sVGxGU1QYEIhHGyyrKQ hogZhsoUSmTrNozxThZt2N2RyeZQWnidRnK1NcyI= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 32NCTj6W038925 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 23 Mar 2023 07:29:45 -0500 Received: from DFLE109.ent.ti.com (10.64.6.30) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Thu, 23 Mar 2023 07:29:45 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Thu, 23 Mar 2023 07:29:45 -0500 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 32NCTicN019249; Thu, 23 Mar 2023 07:29:44 -0500 From: Dhruva Gole To: Keerthy CC: Vibhore Vardhan , Dhruva Gole , Tony Lindgren , Vignesh , Linus Walleij , Bartosz Golaszewski , , Subject: [RFC PATCH 2/2] gpio: davinci: Add irq chip flag to skip set wake Date: Thu, 23 Mar 2023 17:59:10 +0530 Message-ID: <20230323122910.991148-2-d-gole@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230323122910.991148-1-d-gole@ti.com> References: <20230323122910.991148-1-d-gole@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add the IRQCHIP_SKIP_SET_WAKE flag since there are no special IRQ Wake bits that can be set to enable wakeup IRQ. Fixes: 3d9edf09d452 ("[ARM] 4457/2: davinci: GPIO support") Signed-off-by: Dhruva Gole Reviewed-by: Linus Walleij --- drivers/gpio/gpio-davinci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpio/gpio-davinci.c b/drivers/gpio/gpio-davinci.c index d7595b39e8c4..aaaf61dc2632 100644 --- a/drivers/gpio/gpio-davinci.c +++ b/drivers/gpio/gpio-davinci.c @@ -322,7 +322,7 @@ static struct irq_chip gpio_irqchip = { .irq_enable = gpio_irq_enable, .irq_disable = gpio_irq_disable, .irq_set_type = gpio_irq_type, - .flags = IRQCHIP_SET_TYPE_MASKED, + .flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_SKIP_SET_WAKE, }; static void gpio_irq_handler(struct irq_desc *desc)