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Wed, 22 Mar 2023 09:02:57 +0000 From: haibo.chen@nxp.com To: broonie@kernel.org, han.xu@nxp.com Cc: linux-spi@vger.kernel.org, yogeshgaur.83@gmail.com, haibo.chen@nxp.com, linux-imx@nxp.com Subject: [PATCH 1/2] spi: spi-nxp-fspi: correct the comment for the DLL config Date: Wed, 22 Mar 2023 17:04:50 +0800 Message-Id: <20230322090451.3179431-1-haibo.chen@nxp.com> X-Mailer: git-send-email 2.34.1 X-ClientProxiedBy: SI2PR04CA0007.apcprd04.prod.outlook.com (2603:1096:4:197::19) To DB7PR04MB4010.eurprd04.prod.outlook.com (2603:10a6:5:21::30) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DB7PR04MB4010:EE_|DB9PR04MB8123:EE_ X-MS-Office365-Filtering-Correlation-Id: 82e63515-7b29-4a79-9621-08db2ab43a65 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: M28xyKDyqZU86m0Gg7VkCZ0gxVrtkaJx1otl74NyHmIk0iDH5nuZCjQAxUhx4jYfbKNBHRXXnj4Sh2nfvQjyebnC9afpbfvGF2WHZlMo9bNgCO4zaKhpvFa9sBUkiQDd5jnct+ql7gYIp43OsxnctXOnlu1ZYsGCno9XjlCK7npUoN06CWbmqfWL9iwHr/6nlk3If34Dv11HKZXzJIJ2T2uJ34cjPoU8DlZxf0fMjWhBEV2h5NEI0zistZ3+gsNZGwqro07RGs2Bvtv9rBFxL7yvDMWX6jJVLg3W67i0eXdE975S8FWo3ThqgAtCFDNxBeFMl9l3Ml7kUA6ox0m7+XSf8x0Bz/yiwKyWxUm2xMXX6ATDNSjqF6ly7SQMoG5kQwvPvNjeByGWLOlQnagM6b3I3erQSo+46n+PWQLC7EYROqm/6WxRnHzuwrvM+2Fe85Et6WNCLQwlDz4m35Ebnrze11Moc/GZkvrh/VTqo0zULMgYoTXUgMqdYW0e0RIZSgxfjOMbbM1sRejoj1UJqxBsthgyJdqqUbkwZYCecafYx9vOStrzsGRpDsKb4Xc8iPXstwSVAJ2IWNV7NSIEvLSIIOAeMtADiw8dlExsI4emXzIzXi6mD+R1WW4VYd9g9srt9gYQ09Yrisic/Hjudg8E/MZ4hIk6s6Fzj1mneSbJ+iHXI+NuZHIMBdSBQxl7HD39ulfu5ZLD/cK9Ye3WVw== X-Forefront-Antispam-Report: CIP:255.255.255.255; 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Signed-off-by: Haibo Chen --- drivers/spi/spi-nxp-fspi.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-nxp-fspi.c b/drivers/spi/spi-nxp-fspi.c index 76168cc1e00d..6735c22b9137 100644 --- a/drivers/spi/spi-nxp-fspi.c +++ b/drivers/spi/spi-nxp-fspi.c @@ -997,7 +997,11 @@ static int nxp_fspi_default_setup(struct nxp_fspi *f) /* Disable the module */ fspi_writel(f, FSPI_MCR0_MDIS, base + FSPI_MCR0); - /* Reset the DLL register to default value */ + /* + * Config the DLL register to default value, enable the slave clock delay + * line delay cell override mode, and use 1 fixed delay cell in DLL delay + * chain, this is the suggested setting when clock rate < 100MHz. + */ fspi_writel(f, FSPI_DLLACR_OVRDEN, base + FSPI_DLLACR); fspi_writel(f, FSPI_DLLBCR_OVRDEN, base + FSPI_DLLBCR); From patchwork Wed Mar 22 09:04:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bough Chen X-Patchwork-Id: 666090 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CF5D8C7619A for ; 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DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: N5TVVTGHA8RXZIC99DBIEtm0jWU6n5RrAiWjyFU1hrB1J8Sg/vW58XSGxeFs5Y+VcTcVmXZ7TIYXJ6uTP+Owwo0bYtg5lUokj6IQ13Y9fVT+M9lWSR25Lej4wH/sJKCUOsyg73CGC3XizdGRq/78ejoZBBssLyHp+0i5drYwcnJ5eW6CgWzO+7rxdMkpTPsKjBvnBrJhfdLS+L1pHq8PcteqxgKzWawSMO1zcyES7hl+JM3RGCuo4JTlkogJzY3QjwVeT5+USYFmLHTxFxHaRJIndGyOQnhPHj6MjGvtYwRjVz1XB4neiHJj20HIUr6zxp9gW3zTsLSM7aKISVbjydGW1LMqFOfIXx/Ek1vautv8u5CF9tazvGGRS5co2jZFBpCf5DqJRkqqNxO3xghHjogMyTN80uH1Y7bQLyyMB7kb75Hxit47DOOC8yrzlgMYhjzXMDCm8aC2t7yLF4p3CHv7U1kyBEUXpsA3mWhmHBRqIYdPmv7LCS/0QSAyQ0xRW7LLYWeUASzWavQ36zLmdtUS74ll9Oscpsf+ByJ1QNncUqetz/vTSdP9REy+PBKU4s7dihRuRlqCLSWeA4kcy4hFC1rtvNPhT+fgptHogtxOJumRGcaEh0/x03l1E2VO9YOZ2cZxOPsCeR+2n5vNmBLD+8Eh80DNakXTJZ+nKkzliygq0Vtvl0AcQnHYwPwKMCP95sGYGq4mhJnS0GnAIJPM/u0xAIh5hTtqvAxJ6bUjBRlv73O6Ow4uXUQYQZsiH33ccc2tLyc7MvkNaH9SRd5DevD5MFpIR/j+H6eVLn+aNH5IqOaMFq4/Z2Ktc9YOzINCl2S0+lIDJXfy3nmKtp0CMU70LUjgJfU0s1eNev9KCxQic6MR5LFvH6jXS61/B2NHhlFP99/yLH8Eh+KPgsY1jR9wKTTqHU+AIg2l5pfldJzNq2H1D14EdkrRusWJeJ/fBWx0hucqjXR0oC3jVkzRWjfPHZdmFUyYI1FeUyBECd8NMIgQRtz+fsgkftOcdtftAFD5M+dqbFF4SgXiMrVqzM7r35QZCSirlth45ak7adaVO5/0DD35FZ2TJWaVX79+Ik2I+6uRe0FP95ylyVb7KhYJBwXapnSKf35Wm0RhsiGxrjE7WW5WKLY+iFcE8BFu8VnImohqsXcLCPUT2a5xeomaucm3lVrXOFLIMTbCaTW42Kn16mroObxggrwArhFtHmHKxT0YnLhMj6Gd9ja9MI89Y4cmdanbyxdY3FqtZh8IKkNoQC4mwTMIlUCmwcLUHHmtN8McCidWlOK/o6jMAJSjv+rs1D6ztZoYlHyZoBa7sIRWX7spyXTMzVnMcEt8RImkZANw8x7BKTF+2Qao0VFsfjmcFCFkPjNMIrb4Fg2/yDLkeb07WaC5WBofPe9WDmsySw19wK/gj9awgaASWmK1+rwF8nz7ngQtnCK3lyFeOAIY156fwOdlNWbt+YSe6+joFnpo6zU9lcut8BTrqYQG+4r1zPhk+BKPO8DkJXKhimn3aMD9ElhVxfSalgaEL1PgMix+RYtI3d3nXgOP2HBQEtjxsE0JbAnrQ/Uer2O5Bbccp/8MLAS8IEsr X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: e94fe5f7-eac6-42a0-691c-08db2ab43be5 X-MS-Exchange-CrossTenant-AuthSource: DB7PR04MB4010.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Mar 2023 09:02:59.6364 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: hh+HdcflwoGkLmQRWeWMA6GmhXCTl/lUUVC1ZapkjjF6kE8BOlWQWDJ2fVhpfQ60okpFYXfCLdf/ujy/6+3IHQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9PR04MB8123 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Haibo Chen When clock rate > 100MHz, use the DLL calibration mode, and finally add the suggested half of the current clock cycle to sample the data. Signed-off-by: Haibo Chen Reviewed-by: Han Xu Tested-by: Han Xu --- drivers/spi/spi-nxp-fspi.c | 52 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/drivers/spi/spi-nxp-fspi.c b/drivers/spi/spi-nxp-fspi.c index 6735c22b9137..544017655787 100644 --- a/drivers/spi/spi-nxp-fspi.c +++ b/drivers/spi/spi-nxp-fspi.c @@ -214,9 +214,15 @@ #define FSPI_DLLACR 0xC0 #define FSPI_DLLACR_OVRDEN BIT(8) +#define FSPI_DLLACR_SLVDLY(x) ((x) << 3) +#define FSPI_DLLACR_DLLRESET BIT(1) +#define FSPI_DLLACR_DLLEN BIT(0) #define FSPI_DLLBCR 0xC4 #define FSPI_DLLBCR_OVRDEN BIT(8) +#define FSPI_DLLBCR_SLVDLY(x) ((x) << 3) +#define FSPI_DLLBCR_DLLRESET BIT(1) +#define FSPI_DLLBCR_DLLEN BIT(0) #define FSPI_STS0 0xE0 #define FSPI_STS0_DLPHB(x) ((x) << 8) @@ -231,6 +237,16 @@ #define FSPI_STS1_AHB_ERRCD(x) ((x) << 8) #define FSPI_STS1_AHB_ERRID(x) (x) +#define FSPI_STS2 0xE8 +#define FSPI_STS2_BREFLOCK BIT(17) +#define FSPI_STS2_BSLVLOCK BIT(16) +#define FSPI_STS2_AREFLOCK BIT(1) +#define FSPI_STS2_ASLVLOCK BIT(0) +#define FSPI_STS2_AB_LOCK (FSPI_STS2_BREFLOCK | \ + FSPI_STS2_BSLVLOCK | \ + FSPI_STS2_AREFLOCK | \ + FSPI_STS2_ASLVLOCK) + #define FSPI_AHBSPNST 0xEC #define FSPI_AHBSPNST_DATLFT(x) ((x) << 16) #define FSPI_AHBSPNST_BUFID(x) ((x) << 1) @@ -615,6 +631,35 @@ static int nxp_fspi_clk_disable_unprep(struct nxp_fspi *f) return 0; } +static void nxp_fspi_dll_calibration(struct nxp_fspi *f) +{ + int ret; + + /* Reset the DLL, set the DLLRESET to 1 and then set to 0 */ + fspi_writel(f, FSPI_DLLACR_DLLRESET, f->iobase + FSPI_DLLACR); + fspi_writel(f, FSPI_DLLBCR_DLLRESET, f->iobase + FSPI_DLLBCR); + fspi_writel(f, 0, f->iobase + FSPI_DLLACR); + fspi_writel(f, 0, f->iobase + FSPI_DLLBCR); + + /* + * Enable the DLL calibration mode. + * The delay target for slave delay line is: + * ((SLVDLYTARGET+1) * 1/32 * clock cycle of reference clock. + * When clock rate > 100MHz, recommend SLVDLYTARGET is 0xF, which + * means half of clock cycle of reference clock. + */ + fspi_writel(f, FSPI_DLLACR_DLLEN | FSPI_DLLACR_SLVDLY(0xF), + f->iobase + FSPI_DLLACR); + fspi_writel(f, FSPI_DLLBCR_DLLEN | FSPI_DLLBCR_SLVDLY(0xF), + f->iobase + FSPI_DLLBCR); + + /* Wait to get REF/SLV lock */ + ret = fspi_readl_poll_tout(f, f->iobase + FSPI_STS2, FSPI_STS2_AB_LOCK, + 0, POLL_TOUT, true); + if (ret) + dev_warn(f->dev, "DLL lock failed, please fix it!\n"); +} + /* * In FlexSPI controller, flash access is based on value of FSPI_FLSHXXCR0 * register and start base address of the slave device. @@ -690,6 +735,13 @@ static void nxp_fspi_select_mem(struct nxp_fspi *f, struct spi_device *spi) if (ret) return; + /* + * If clock rate > 100MHz, then switch from DLL override mode to + * DLL calibration mode. + */ + if (rate > 100000000) + nxp_fspi_dll_calibration(f); + f->selected = spi_get_chipselect(spi, 0); }