From patchwork Mon May 20 10:11:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "\(Exiting\) Baolin Wang" X-Patchwork-Id: 164582 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp93912ili; Mon, 20 May 2019 03:12:44 -0700 (PDT) X-Google-Smtp-Source: APXvYqyRVMVQ6CTDTRitII6JAsznRWTaWPwrQEEQxPHDrTmTu+Hwa93C3p6V5krv+nfsR3xEpjra X-Received: by 2002:a63:8149:: with SMTP id t70mr75646815pgd.134.1558347164035; Mon, 20 May 2019 03:12:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1558347164; cv=none; d=google.com; s=arc-20160816; b=egKr+TH91JnVcG3znR9mqQU485c/JtlHQzmtB+f7wtu5FJgwEudCObHLv+RDmBTuh7 6IXWMPhRpG7Kyx9axjZKakEdFjkkf+rfdePOzjuyxqPLsGcuNWVucxIEs2AYOqxt4zeR qKhhZlWcze/GXgMD9ZuixEZHqlGqkPDmZMmVzkF6Sh687URSKe0wpG5huV+nzfv88Y8e 1dLKCCVEbv/K5ewe+LTClPMcSkqkrZZkF688UBMmPwdMV4mYxjXlQyw2dvPjDVac6Uyq 9SH8s7f3PIP/cW4y2q4Gz9bnqr7P4l0OgGAmGklseDbON+YX8XQy5QIX9+iVzqdwiIIB /3PQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:references :in-reply-to:message-id:date:subject:cc:to:from:dkim-signature; bh=HpWLJW0AsyMzUk7aFfWV1G46hR6bm2Fq1Ta1KdUw0ic=; b=wTGxeqrdCxi/TEqryw3rOHaoa9ytIPLgi45629BwlCHgJxVCjmrrIYfwxiHzKzDwMw SNNyYCj8mEcsNVnJARVTYp8zPpzoyFPbRIjxFZbypZSa4KbD9rnd+RwrwlZESbmnIBuG ZmyzImB0MYZOnZU5jl1GlFkJgyphAC2eJi/DaoHcZWrN5ApcxN/awRlok84nLxyAYUYF dcZ1xUT/iIVcoU8Ca57XF2ZRs9sA3yymUe1eQsMdK2PjKDLOXoQnc1vXc/jd83b6KvYX qbO7qIoBFnnDRqjx/2QgmeEjLTrR5BwXOTrB+HfUI4AR/a6VQegoPSl+GrYbCTv+QY34 gqtA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="DTIHo9/m"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id n4si17101172pgq.69.2019.05.20.03.12.43; Mon, 20 May 2019 03:12:44 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="DTIHo9/m"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732470AbfETKMm (ORCPT + 30 others); Mon, 20 May 2019 06:12:42 -0400 Received: from mail-pf1-f193.google.com ([209.85.210.193]:35666 "EHLO mail-pf1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732445AbfETKMh (ORCPT ); Mon, 20 May 2019 06:12:37 -0400 Received: by mail-pf1-f193.google.com with SMTP id t87so6996051pfa.2 for ; Mon, 20 May 2019 03:12:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=HpWLJW0AsyMzUk7aFfWV1G46hR6bm2Fq1Ta1KdUw0ic=; b=DTIHo9/mhznHhmMPsPg2GreBFfHF6EqewzBibeH6J1rwd6xeG3CJaiSCAzzM0YX1tO rDYGkQdhqxkOfEx0wELCbz7sxgZ+bOojR87F94462mSYPW3J5rhmvbmhzad45atYa0WH 9hO34uiRK2xFzSLn3r61HSZ0Ru7VfMkZcb3mClqKzRsMRRr9QQ8RtgBlhpuWyVBDiIRm enY5MU3j77jwUVAX0AOhzawX9LeWp4YlatlPNLWMFrmF2sBHw97X6F6PS++hkNI1XozR PNaWJDkBBRlDIPXBgEIjqdEHxh6uIZLsAT3Zqhjy0nijV3nkFeIYannK9MLNIPhACU2C l+yw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=HpWLJW0AsyMzUk7aFfWV1G46hR6bm2Fq1Ta1KdUw0ic=; b=Io4rfPFb1bYjzbn5lhZHHCiVEeFMRSXsZ3gRL7u5cSNnm/8xkhlcZ/nG4Wp6jwQzZ1 dyhiM86mnrVe2i8Xdiq5x19c4DAnyjqmO9P3wCHSU5lyOaHCKl2n37m1znG80PUDzD3F nz5VDy5Dj3DZrLukocSDE20O6MTmDAmr0a0c/ggQM0yF4VPoJm8RvCG9wHKYoD/K1Rz9 SNp1sI9YwQiCLI11OL9YzD3JkBVbr/6TZoMucNq5xHql8YAPUvAOweY8ClR1RBcZ14rR iRugR5r9+RJPGSohYYmPaDsCHRQf59qJcXpAFLsJ+OMzQU2eMeOIgfCTpR1+pAdCwcgG Z/NQ== X-Gm-Message-State: APjAAAX5qmJfBdXkcvosO1hBBFrzIolXFvpxEiaG9UDFe+HiLRZJaqkJ 9D7atF1kpGMhwhmYTsRt5fbV1g== X-Received: by 2002:a63:e451:: with SMTP id i17mr74906860pgk.312.1558347156596; Mon, 20 May 2019 03:12:36 -0700 (PDT) Received: from baolinwangubtpc.spreadtrum.com ([117.18.48.102]) by smtp.gmail.com with ESMTPSA id b3sm30098127pfr.146.2019.05.20.03.12.32 (version=TLS1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 20 May 2019 03:12:36 -0700 (PDT) From: Baolin Wang To: adrian.hunter@intel.com, ulf.hansson@linaro.org, zhang.lyra@gmail.com, orsonzhai@gmail.com, robh+dt@kernel.org, mark.rutland@arm.com, arnd@arndb.de, olof@lixom.net Cc: baolin.wang@linaro.org, vincent.guittot@linaro.org, arm@kernel.org, linux-arm-kernel@lists.infradead.org, linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 3/9] mmc: sdhci-sprd: Add optional gate clock support Date: Mon, 20 May 2019 18:11:56 +0800 Message-Id: <16b895cf30c235dc656eeed5888069b6266ab5f8.1558346019.git.baolin.wang@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: References: In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org For the Spreadtrum SC9860 platform, we should enable another gate clock '2x_enable' to make the SD host controller work well. Signed-off-by: Baolin Wang --- drivers/mmc/host/sdhci-sprd.c | 35 +++++++++++++++++++++++++++++------ 1 file changed, 29 insertions(+), 6 deletions(-) -- 1.7.9.5 Acked-by: Adrian Hunter diff --git a/drivers/mmc/host/sdhci-sprd.c b/drivers/mmc/host/sdhci-sprd.c index e741491..31ba7d6 100644 --- a/drivers/mmc/host/sdhci-sprd.c +++ b/drivers/mmc/host/sdhci-sprd.c @@ -60,6 +60,7 @@ struct sdhci_sprd_host { u32 version; struct clk *clk_sdio; struct clk *clk_enable; + struct clk *clk_2x_enable; u32 base_rate; int flags; /* backup of host attribute */ }; @@ -364,6 +365,10 @@ static int sdhci_sprd_probe(struct platform_device *pdev) } sprd_host->clk_enable = clk; + clk = devm_clk_get(&pdev->dev, "2x_enable"); + if (!IS_ERR(clk)) + sprd_host->clk_2x_enable = clk; + ret = clk_prepare_enable(sprd_host->clk_sdio); if (ret) goto pltfm_free; @@ -372,6 +377,10 @@ static int sdhci_sprd_probe(struct platform_device *pdev) if (ret) goto clk_disable; + ret = clk_prepare_enable(sprd_host->clk_2x_enable); + if (ret) + goto clk_disable2; + sdhci_sprd_init_config(host); host->version = sdhci_readw(host, SDHCI_HOST_VERSION); sprd_host->version = ((host->version & SDHCI_VENDOR_VER_MASK) >> @@ -408,6 +417,9 @@ static int sdhci_sprd_probe(struct platform_device *pdev) pm_runtime_disable(&pdev->dev); pm_runtime_set_suspended(&pdev->dev); + clk_disable_unprepare(sprd_host->clk_2x_enable); + +clk_disable2: clk_disable_unprepare(sprd_host->clk_enable); clk_disable: @@ -427,6 +439,7 @@ static int sdhci_sprd_remove(struct platform_device *pdev) mmc_remove_host(mmc); clk_disable_unprepare(sprd_host->clk_sdio); clk_disable_unprepare(sprd_host->clk_enable); + clk_disable_unprepare(sprd_host->clk_2x_enable); mmc_free_host(mmc); @@ -449,6 +462,7 @@ static int sdhci_sprd_runtime_suspend(struct device *dev) clk_disable_unprepare(sprd_host->clk_sdio); clk_disable_unprepare(sprd_host->clk_enable); + clk_disable_unprepare(sprd_host->clk_2x_enable); return 0; } @@ -459,19 +473,28 @@ static int sdhci_sprd_runtime_resume(struct device *dev) struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); int ret; - ret = clk_prepare_enable(sprd_host->clk_enable); + ret = clk_prepare_enable(sprd_host->clk_2x_enable); if (ret) return ret; + ret = clk_prepare_enable(sprd_host->clk_enable); + if (ret) + goto clk_2x_disable; + ret = clk_prepare_enable(sprd_host->clk_sdio); - if (ret) { - clk_disable_unprepare(sprd_host->clk_enable); - return ret; - } + if (ret) + goto clk_disable; sdhci_runtime_resume_host(host); - return 0; + +clk_disable: + clk_disable_unprepare(sprd_host->clk_enable); + +clk_2x_disable: + clk_disable_unprepare(sprd_host->clk_2x_enable); + + return ret; } #endif From patchwork Mon May 20 10:11:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "\(Exiting\) Baolin Wang" X-Patchwork-Id: 164584 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp94047ili; Mon, 20 May 2019 03:12:53 -0700 (PDT) X-Google-Smtp-Source: APXvYqxKb/6aCB84KiiXCnyL3ZX742TJ1Gt99HfLGDV2h4rHYa0LNLXY/3pkkEJaJL+etjGn0ReA X-Received: by 2002:a17:902:1029:: with SMTP id b38mr34979495pla.72.1558347173294; Mon, 20 May 2019 03:12:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1558347173; cv=none; d=google.com; s=arc-20160816; b=fHQAJCALaf1zKQPLLWSBwaybsb69aEB3s4ossEOnfMNbsOIIp6B8bUq31K5Arswo21 WDRoGnwpXdqSrk6mt//3jUYmnOfUJBw9qDml/AKspQmg6kHAHHvvRwxIkVaZIZ2A2vZz mI7PzbxFPJ7VyE1VFb2c4wiFsP9q4To7AiNlY6MoePs4wpOsPdEsN9C0khrDhlyAT21Y hgsQGgWlJmriXvgrPt+FdDuyJQioWPD0fomxPIpeAFptxM3aJXf0rO8QmbkDvS68IEW5 aYjKH9WevZAgmC6bqwPmgcAGXKwVhjZjh1Sq2CiUKG3tohTp9k2AbgLnjjUCEE2N+4TT zspQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:references :in-reply-to:message-id:date:subject:cc:to:from:dkim-signature; bh=tBhcNYJtRLrxmBnBaA1yOUVcPiTzc/ssEh1mPTrnJ9A=; b=CeBfQYyj9fHa/UenoMQYySIrU5IO6n3BV/lWgimo9Xxc6u9J0yW1Fodr/adZG0i/YA F/NF2Sl9d/nvTVEEQZqLsFgsQlofOhYGUwiKnrgfkKOYgxyEwO+xdEP01XQ+8DKhkHUZ hT8JBCRfylTPx2DnGODbdaepFCaeHCwg3WjnIjTihljirZ7Af1mzFjeSzg2OzfVZ8EN0 uODsA9RFwyuzVfCt/o9GWyi4pIOMwa73ZtI58MceHuvo4eefpVNdW8Mfac1HxcLQyzZC f4Fl7Xt/JYxh8awvxU44oqJU+8CzPpYZiXrTjoCYIPpkC4AXslJjiyCw5RWTJjtu9WP7 BV2g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=LyscKN3A; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id j23si10798874pgn.507.2019.05.20.03.12.53; Mon, 20 May 2019 03:12:53 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=LyscKN3A; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732509AbfETKMw (ORCPT + 30 others); Mon, 20 May 2019 06:12:52 -0400 Received: from mail-pl1-f195.google.com ([209.85.214.195]:40273 "EHLO mail-pl1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732497AbfETKMt (ORCPT ); Mon, 20 May 2019 06:12:49 -0400 Received: by mail-pl1-f195.google.com with SMTP id g69so6502929plb.7 for ; Mon, 20 May 2019 03:12:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=tBhcNYJtRLrxmBnBaA1yOUVcPiTzc/ssEh1mPTrnJ9A=; b=LyscKN3AqfXVoetIgjkoE69HYU9HnAi1xdi1PsWubJiP8Qrv8OJyrz1r2HMdsL4FBb lQn9hJZO7LhXiuRReQ8WMnJHmvQGs73mt7wOAguu18mV051cJZf2rpUwMXUW0v5M7sX9 TvQolobA/OMQm2Qf0tBTfekBPWmgcCL6eG6yRhsfz2miwtlncfd8UJe5AxOATOoorLtg aKfpmc+QwDJvg2iLFU3gYYgI8aETuhnyGo4OvUdSKWAbXe9XZgN9iZW4BWb7f5B1mwcL Oq/7pqCRe+GigkPGu0MRkAyzZbtoql9Vlz0TruCFPEe35lqvZ5iuPcuIhdBuBcBlUgv3 +2sQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=tBhcNYJtRLrxmBnBaA1yOUVcPiTzc/ssEh1mPTrnJ9A=; b=pCZhfLT03Phbk6q3Q/K1yfPV+BTuUrsUqArXlex0EkoPWNTejEFd5fz2WROPrCo7lt 6C1sIa32xLm1BiClcfr/7cbjWuTNMfKNICkY8w1fgfucBgQszPAxWJaNX82TnUCPKrI4 /P5kOXbBIryp5kuuO3brdFuQKgPtGw33CP1/0H2FmLxsm0uBnV4emG+tnxt2XAsRxRSN eEdJIwIS4zfJxmNTGPLlmBSDIGNbDygqyAxZ/j2Gtd/u0hTR5vYLDQ1PzFg0dFKDBUIn sCdCxgxSIv38Z1PMMv0YpXzfrmY240JecytCZz00K4eCP3FshI/Xe8yA6rV5DbNiIwqo BTaA== X-Gm-Message-State: APjAAAWu46utRJB85gFm8pL5zekdDebN4dmD8Sju/wydwWZIamDeWKEf ZdZYaECW/yj92/41IMJHBlvTRg== X-Received: by 2002:a17:902:7202:: with SMTP id ba2mr21102932plb.177.1558347169203; Mon, 20 May 2019 03:12:49 -0700 (PDT) Received: from baolinwangubtpc.spreadtrum.com ([117.18.48.102]) by smtp.gmail.com with ESMTPSA id b3sm30098127pfr.146.2019.05.20.03.12.45 (version=TLS1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 20 May 2019 03:12:48 -0700 (PDT) From: Baolin Wang To: adrian.hunter@intel.com, ulf.hansson@linaro.org, zhang.lyra@gmail.com, orsonzhai@gmail.com, robh+dt@kernel.org, mark.rutland@arm.com, arnd@arndb.de, olof@lixom.net Cc: baolin.wang@linaro.org, vincent.guittot@linaro.org, arm@kernel.org, linux-arm-kernel@lists.infradead.org, linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 6/9] mmc: sdhci-sprd: Enable PHY DLL to make clock stable Date: Mon, 20 May 2019 18:11:59 +0800 Message-Id: <270e86bf6b1ce138e40830fb63c9bcf150440426.1558346019.git.baolin.wang@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: References: In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org For the Spreadtrum SD host controller, when we changed the clock to be more than 52M, we should enable the PHY DLL which is used to track the clock frequency to make the clock work more stable. Otherwise deviation may occur of the higher clock. Signed-off-by: Baolin Wang --- drivers/mmc/host/sdhci-sprd.c | 44 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 43 insertions(+), 1 deletion(-) -- 1.7.9.5 diff --git a/drivers/mmc/host/sdhci-sprd.c b/drivers/mmc/host/sdhci-sprd.c index edec197..e6eda13 100644 --- a/drivers/mmc/host/sdhci-sprd.c +++ b/drivers/mmc/host/sdhci-sprd.c @@ -22,6 +22,13 @@ /* SDHCI_ARGUMENT2 register high 16bit */ #define SDHCI_SPRD_ARG2_STUFF GENMASK(31, 16) +#define SDHCI_SPRD_REG_32_DLL_CFG 0x200 +#define SDHCI_SPRD_DLL_ALL_CPST_EN (BIT(18) | BIT(24) | BIT(25) | BIT(26) | BIT(27)) +#define SDHCI_SPRD_DLL_EN BIT(21) +#define SDHCI_SPRD_DLL_SEARCH_MODE BIT(16) +#define SDHCI_SPRD_DLL_INIT_COUNT 0xc00 +#define SDHCI_SPRD_DLL_PHASE_INTERNAL 0x3 + #define SDHCI_SPRD_REG_32_DLL_DLY_OFFSET 0x208 #define SDHCIBSPRD_IT_WR_DLY_INV BIT(5) #define SDHCI_SPRD_BIT_CMD_DLY_INV BIT(13) @@ -56,6 +63,7 @@ #define SDHCI_SPRD_CLK_MAX_DIV 1023 #define SDHCI_SPRD_CLK_DEF_RATE 26000000 +#define SDHCI_SPRD_PHY_DLL_CLK 52000000 struct sdhci_sprd_host { u32 version; @@ -200,9 +208,33 @@ static inline void _sdhci_sprd_set_clock(struct sdhci_host *host, } } +static void sdhci_sprd_enable_phy_dll(struct sdhci_host *host) +{ + u32 tmp; + + tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG); + tmp &= ~(SDHCI_SPRD_DLL_EN | SDHCI_SPRD_DLL_ALL_CPST_EN); + sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG); + /* wait 1ms */ + usleep_range(1000, 1250); + + tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG); + tmp |= SDHCI_SPRD_DLL_ALL_CPST_EN | SDHCI_SPRD_DLL_SEARCH_MODE | + SDHCI_SPRD_DLL_INIT_COUNT | SDHCI_SPRD_DLL_PHASE_INTERNAL; + sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG); + /* wait 1ms */ + usleep_range(1000, 1250); + + tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG); + tmp |= SDHCI_SPRD_DLL_EN; + sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG); + /* wait 1ms */ + usleep_range(1000, 1250); +} + static void sdhci_sprd_set_clock(struct sdhci_host *host, unsigned int clock) { - bool en = false; + bool en = false, clk_changed = false; if (clock == 0) { sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); @@ -214,9 +246,19 @@ static void sdhci_sprd_set_clock(struct sdhci_host *host, unsigned int clock) en = true; sdhci_sprd_set_dll_invert(host, SDHCI_SPRD_BIT_CMD_DLY_INV | SDHCI_SPRD_BIT_POSRD_DLY_INV, en); + clk_changed = true; } else { _sdhci_sprd_set_clock(host, clock); } + + /* + * According to the Spreadtrum SD host specification, when we changed + * the clock to be more than 52M, we should enable the PHY DLL which + * is used to track the clock frequency to make the clock work more + * stable. Otherwise deviation may occur of the higher clock. + */ + if (clk_changed && clock > SDHCI_SPRD_PHY_DLL_CLK) + sdhci_sprd_enable_phy_dll(host); } static unsigned int sdhci_sprd_get_max_clock(struct sdhci_host *host) From patchwork Mon May 20 10:12:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "\(Exiting\) Baolin Wang" X-Patchwork-Id: 164586 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp94205ili; Mon, 20 May 2019 03:13:02 -0700 (PDT) X-Google-Smtp-Source: APXvYqx8ggV6OlIG8gKS4n0GVPX+pmFWjlRKYGHxpTaVy+iVxnn/NaZ8WhKLpUqCPhvnb55H1Hmb X-Received: by 2002:a63:3c14:: with SMTP id j20mr74968795pga.410.1558347182567; Mon, 20 May 2019 03:13:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1558347182; cv=none; d=google.com; s=arc-20160816; b=AzodR9TdaTeEsnfYJBzrT/9xOb1YMu7lXEoDTaaIu2SjDUXMRdq7/gPFqhLE9k//SU w3BCaCDVedgfGmgjs8UbWOi+zhaBJq9HhCzbmg+crO3eDYF8dj7Z4XvyG9STUxiYYa3w ZaVZihscgJY6Om1aLqI0qBnGJjEYC0yj1t50jcXLOGP5I3tbngcJAMy6PFU8sopqMsOZ oRXj05y43HxBunngaOm3SlwqcODhmuUOnFwB5K/bzfihDppSjXMIsSq9oEIL7TLy8PWE PbQJheBUDUSWGGEtFKWRyXJzKgm38PNqiIIVo2hZgYbUSvJaVhHX76csnFTq0E9GrxlV V78Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:references :in-reply-to:message-id:date:subject:cc:to:from:dkim-signature; bh=xveO13FKhXzoL1lkYTFX11xifuYVV7+mJh5hbeM4mGk=; b=fw6WmRidYPaHK3leDQcFM4mnfwd0s/rmq7nuL0vXiF//3PAm2KNJZMvvip4FKtiVH0 Z/1r1bTla0VZJqOVUHViRUMn63CJMGq7+4v8QQSzjj204K1iq7lk/yRHQVzOYadxWBGa UiARdUX8+XcS6u8w0SBJTC+JP1tdHkdw9vew2Ai/Oo3jvQ82I/Bm2jaJIX2edGk+rM8v 6RiNDRpF3GXmIyVYj4wV8/wbHWr9ZGJGM6blB1SDH1Km9MLBeHWdHPXBCRkGW36X/4dF l/2qXE4AjbsjBuZ0rWNvFEVvyIMQ/BAd8kAC1JANFn3Av4c3ksFTbuvscscgtTpk/MOV gX6g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NKlJUoOf; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id h4si17557443pgm.571.2019.05.20.03.13.02; Mon, 20 May 2019 03:13:02 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NKlJUoOf; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732534AbfETKNB (ORCPT + 30 others); Mon, 20 May 2019 06:13:01 -0400 Received: from mail-pl1-f193.google.com ([209.85.214.193]:39107 "EHLO mail-pl1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732519AbfETKM7 (ORCPT ); Mon, 20 May 2019 06:12:59 -0400 Received: by mail-pl1-f193.google.com with SMTP id g9so6499414plm.6 for ; Mon, 20 May 2019 03:12:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=xveO13FKhXzoL1lkYTFX11xifuYVV7+mJh5hbeM4mGk=; b=NKlJUoOflJbwmEE4EZCwFYMT/ND4NmEVAhtO+YHos+oeGhc++olfTd8GSNmCw1X2u2 Y56AU27jDf0om7R+rK1/dPYEMO3cKEFC39QaTfkSuhz/kfimV4LgjQatrj+p4JDeq3lO Z5CVPpDBkRd4tye4QFnooifpUpXVPwMotVR+q6LNKCfzhDU9lj8aALZIwwvG3xuEEBXr ZbVwR3Tlv+3ykzIAFM273uPcq3V1Ma4kjga/p0LmeREn4wX+Lxw8hZJ0M33IEstvThKZ J3lN+eq6HRcbGULZmhdJJklGpONAeiFp4eOiYNCz58FpSFT4pJkFqyjbi89UxIYPMx88 iJGg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=xveO13FKhXzoL1lkYTFX11xifuYVV7+mJh5hbeM4mGk=; b=dkdo+d7Z9IqErz4bVyDfJhUu7Va6eC7nYP4Xl6Qs7BEPtAs5/w3zvSwkV7asmHjXJ4 Zgt+cIorbeNav+Yz6gvx+/5ShVLtancalcd6F6XPn2atKIR5P1CrkWgTNQ10nWUcMQsb NU2xCz+mZt05QirF9KDOkG81krrcvfY5RuMRLD/vstUf7mGhONUmIW9+29NIqzmpOX8a Z9smafap+A0b3CQju5AZ3GHHYtuR1E0EEatqN8OOfS983mVdqg53xMtvoXf5z1LgWeFH rjAYbMoVsSLdV9jgs4oCixSizaD3foUNE+jDhQnL3qdrtPdQQd6wYwmtyYBtQY9IOj1o JVnQ== X-Gm-Message-State: APjAAAVBtAvMdKsxnv/rqRlWowYC5QPn7QANP7JZYpa8SkIW9YntcTHK qxqF9Q2es+LIAzr3wKdBICCLpg== X-Received: by 2002:a17:902:3103:: with SMTP id w3mr470954plb.187.1558347178237; Mon, 20 May 2019 03:12:58 -0700 (PDT) Received: from baolinwangubtpc.spreadtrum.com ([117.18.48.102]) by smtp.gmail.com with ESMTPSA id b3sm30098127pfr.146.2019.05.20.03.12.54 (version=TLS1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 20 May 2019 03:12:57 -0700 (PDT) From: Baolin Wang To: adrian.hunter@intel.com, ulf.hansson@linaro.org, zhang.lyra@gmail.com, orsonzhai@gmail.com, robh+dt@kernel.org, mark.rutland@arm.com, arnd@arndb.de, olof@lixom.net Cc: baolin.wang@linaro.org, vincent.guittot@linaro.org, arm@kernel.org, linux-arm-kernel@lists.infradead.org, linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 8/9] mmc: sdhci-sprd: Add PHY DLL delay configuration Date: Mon, 20 May 2019 18:12:01 +0800 Message-Id: X-Mailer: git-send-email 1.7.9.5 In-Reply-To: References: In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Set the PHY DLL delay for each timing mode, which is used to sample the clock accurately and make the clock more stable. Signed-off-by: Baolin Wang --- drivers/mmc/host/sdhci-sprd.c | 51 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) -- 1.7.9.5 diff --git a/drivers/mmc/host/sdhci-sprd.c b/drivers/mmc/host/sdhci-sprd.c index e6eda13..911a09b 100644 --- a/drivers/mmc/host/sdhci-sprd.c +++ b/drivers/mmc/host/sdhci-sprd.c @@ -29,6 +29,8 @@ #define SDHCI_SPRD_DLL_INIT_COUNT 0xc00 #define SDHCI_SPRD_DLL_PHASE_INTERNAL 0x3 +#define SDHCI_SPRD_REG_32_DLL_DLY 0x204 + #define SDHCI_SPRD_REG_32_DLL_DLY_OFFSET 0x208 #define SDHCIBSPRD_IT_WR_DLY_INV BIT(5) #define SDHCI_SPRD_BIT_CMD_DLY_INV BIT(13) @@ -72,6 +74,24 @@ struct sdhci_sprd_host { struct clk *clk_2x_enable; u32 base_rate; int flags; /* backup of host attribute */ + u32 phy_delay[MMC_TIMING_MMC_HS400 + 2]; +}; + +struct sdhci_sprd_phy_cfg { + const char *property; + u8 timing; +}; + +static const struct sdhci_sprd_phy_cfg sdhci_sprd_phy_cfgs[] = { + { "sprd,phy-delay-legacy", MMC_TIMING_LEGACY, }, + { "sprd,phy-delay-sd-highspeed", MMC_TIMING_MMC_HS, }, + { "sprd,phy-delay-sd-uhs-sdr50", MMC_TIMING_UHS_SDR50, }, + { "sprd,phy-delay-sd-uhs-sdr104", MMC_TIMING_UHS_SDR104, }, + { "sprd,phy-delay-mmc-highspeed", MMC_TIMING_MMC_HS, }, + { "sprd,phy-delay-mmc-ddr52", MMC_TIMING_MMC_DDR52, }, + { "sprd,phy-delay-mmc-hs200", MMC_TIMING_MMC_HS200, }, + { "sprd,phy-delay-mmc-hs400", MMC_TIMING_MMC_HS400, }, + { "sprd,phy-delay-mmc-hs400es", MMC_TIMING_MMC_HS400 + 1, }, }; #define TO_SPRD_HOST(host) sdhci_pltfm_priv(sdhci_priv(host)) @@ -276,6 +296,9 @@ static unsigned int sdhci_sprd_get_min_clock(struct sdhci_host *host) static void sdhci_sprd_set_uhs_signaling(struct sdhci_host *host, unsigned int timing) { + struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); + struct mmc_host *mmc = host->mmc; + u32 *p = sprd_host->phy_delay; u16 ctrl_2; if (timing == host->timing) @@ -314,6 +337,9 @@ static void sdhci_sprd_set_uhs_signaling(struct sdhci_host *host, } sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); + + if (!mmc->ios.enhanced_strobe) + sdhci_writel(host, p[timing], SDHCI_SPRD_REG_32_DLL_DLY); } static void sdhci_sprd_hw_reset(struct sdhci_host *host) @@ -381,6 +407,8 @@ static void sdhci_sprd_hs400_enhanced_strobe(struct mmc_host *mmc, struct mmc_ios *ios) { struct sdhci_host *host = mmc_priv(mmc); + struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); + u32 *p = sprd_host->phy_delay; u16 ctrl_2; if (!ios->enhanced_strobe) @@ -395,6 +423,28 @@ static void sdhci_sprd_hs400_enhanced_strobe(struct mmc_host *mmc, sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); sdhci_sprd_sd_clk_on(host); + + /* Set the PHY DLL delay value for HS400 enhanced strobe mode */ + sdhci_writel(host, p[MMC_TIMING_MMC_HS400 + 1], + SDHCI_SPRD_REG_32_DLL_DLY); +} + +static void sdhci_sprd_phy_param_parse(struct sdhci_sprd_host *sprd_host, + struct device_node *np) +{ + u32 *p = sprd_host->phy_delay; + int ret, i, index; + u32 val[4]; + + for (i = 0; i < ARRAY_SIZE(sdhci_sprd_phy_cfgs); i++) { + ret = of_property_read_u32_array(np, + sdhci_sprd_phy_cfgs[i].property, val, 4); + if (ret) + continue; + + index = sdhci_sprd_phy_cfgs[i].timing; + p[index] = val[0] | (val[1] << 8) | (val[2] << 16) | (val[3] << 24); + } } static const struct sdhci_pltfm_data sdhci_sprd_pdata = { @@ -428,6 +478,7 @@ static int sdhci_sprd_probe(struct platform_device *pdev) goto pltfm_free; sprd_host = TO_SPRD_HOST(host); + sdhci_sprd_phy_param_parse(sprd_host, pdev->dev.of_node); clk = devm_clk_get(&pdev->dev, "sdio"); if (IS_ERR(clk)) { From patchwork Mon May 20 10:12:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "\(Exiting\) Baolin Wang" X-Patchwork-Id: 164587 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp94290ili; Mon, 20 May 2019 03:13:08 -0700 (PDT) X-Google-Smtp-Source: APXvYqwTsuLOB0K+Z+lNFlyhm9XyQECAO4T6VL94Po7YiZpbdIkhoz/BTXwrbURl+ju+w7+rX3kL X-Received: by 2002:a65:420a:: with SMTP id c10mr6925886pgq.376.1558347188039; Mon, 20 May 2019 03:13:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1558347188; cv=none; d=google.com; s=arc-20160816; b=O4kiObVa4j7yh4ukXD/+wamgaZQtLVOS3cFClRgp2bilLjBpXoFEC+sOMr7BU4D2gR 12OyW9/EioBZIVAJkki/pYbPM4gfI/FPc5YBxh/X48eas/3/ikV1RdFqj4sMFecoth5W DCXtQutWplsVnOQdST/k28TpxmPlCvIVc1R37m0q1nvFTZRZEyIm/6jDh9RyXrWbGSU3 Pf4ics3+1aER1wtWDcMAHszK6IIHxIner2lbOf8T2a9lAjZll0oguyCv0mDToJf/lQ16 hFk3jWAs/lhV/kFdP1WGan0qscRqoexD3tNq39nWc8v2seztUG4peGnWkZv/wHvi6v+m WEIw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:references :in-reply-to:message-id:date:subject:cc:to:from:dkim-signature; bh=ap6Go4OzNxJ532m09L3XvGYt1ETDxtVIslcDJHxqhh8=; b=ZKTLL7ZLrHJYBMF6PdazeW+TJOYZVdRFi229nphJRquQ4kEkt2cIRX8+QTgvOG5By7 RF8CjlTCl+QMMylrIYQ1DNNiwaquHk75kObEx0Wt/v21RRU16rUk4vdgx2YdbgsHY9nx iFp10ozAgSfbr9wYIpgFVs16okc68wZw4nfUyz1Gj9IwX8dyVHrup+UWEgGsCAk7+wdA JFHidDswllcbLnIzL+9Ig3Zy30HNahh2WTo5w8zK/AUDk0wvSQU4bxa8bXiig+IaOWoq 365gALcLx9mAaCkjsne5og0MJtBt4k//pvplwh80/7ZeZQxnawHN3XqwNE/4zIHlbu/g 7+ew== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dg9voSlk; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 25si17722110pgs.239.2019.05.20.03.13.07; Mon, 20 May 2019 03:13:08 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dg9voSlk; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732546AbfETKNG (ORCPT + 30 others); Mon, 20 May 2019 06:13:06 -0400 Received: from mail-pl1-f195.google.com ([209.85.214.195]:33174 "EHLO mail-pl1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732535AbfETKND (ORCPT ); Mon, 20 May 2019 06:13:03 -0400 Received: by mail-pl1-f195.google.com with SMTP id y3so6528094plp.0 for ; Mon, 20 May 2019 03:13:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=ap6Go4OzNxJ532m09L3XvGYt1ETDxtVIslcDJHxqhh8=; b=dg9voSlkL9Tcl87q88SNV55S8GA0JmQ0duHA+37dyzDY6OcpNFosrqe5mS3YzRmQOK KPzF/tT9V0EzWBhy2zsLMNsoshKCx2xZyxd4iwz9E9Z+2nn92gIHu5ZHF9a2rvSKpInj ca0v4q6NwLwD/s3f1bL/W4RAqzlQCYCkHWlRExJXrGi1L4hv02Om0lUPuSKo3CmzH1mz d34F0kjxLbephXWC09QvmFZSnEu6Ekd6KSVve5DHXWh8KKISDCiIzD1Vjtqw0xlrah4s Fmbp7jB3XlkVoe7T9o5bHTcpAiwbDpZHyq8FlWAt8RUnDgGdDJmKqnmM8+kdwtqJT8jL 8bLw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=ap6Go4OzNxJ532m09L3XvGYt1ETDxtVIslcDJHxqhh8=; b=J1X3lpCVx6DAZfXV63jTqvYn1l7xd3Jqttefo4IS1Kw1rGvQMAeTUBbJltkuTnOTZP +/RBPK2fsxEroPl1BHBH4ly4Hny3jG5sHTDvjd/5ne5v3JZG8GaKK3O/pVhIBV/Q8uTj FDfjm5/e46BicDS/KOCnr1s1U2D4i1lqAeBS0J7ocfXDgZJ9NZ5AfHmlamE6g49Z/bzn Oazc+iErowCsR+O+Gm0L31D1J6EWuwtcD5d9oBGJEYHYSVF+oWYR8E2i1ye+evn7dZ8g OAM5NOybYC8BJYKZ4eqRIHbzkOzCnrvFkN+zdC3XHfnKC+fZ6n3+TgIKnzkIXzDPBYtU yUag== X-Gm-Message-State: APjAAAWMnebOEUMKq+XNfS6MJPNbLSm1XOQt6SpXj41f584w6zDEHZp1 +tzMNRh47LfUXatJbW+AJ1FKkw== X-Received: by 2002:a17:902:bb06:: with SMTP id l6mr16803820pls.78.1558347182324; Mon, 20 May 2019 03:13:02 -0700 (PDT) Received: from baolinwangubtpc.spreadtrum.com ([117.18.48.102]) by smtp.gmail.com with ESMTPSA id b3sm30098127pfr.146.2019.05.20.03.12.58 (version=TLS1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 20 May 2019 03:13:01 -0700 (PDT) From: Baolin Wang To: adrian.hunter@intel.com, ulf.hansson@linaro.org, zhang.lyra@gmail.com, orsonzhai@gmail.com, robh+dt@kernel.org, mark.rutland@arm.com, arnd@arndb.de, olof@lixom.net Cc: baolin.wang@linaro.org, vincent.guittot@linaro.org, arm@kernel.org, linux-arm-kernel@lists.infradead.org, linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 9/9] arm64: dts: sprd: Add Spreadtrum SD host controller support Date: Mon, 20 May 2019 18:12:02 +0800 Message-Id: <7fc6cd63966bda900b07ac9b2156e313a6f2ac17.1558346019.git.baolin.wang@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: References: In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add one Spreadtrum SD host controller to support eMMC card for Spreadtrum SC9860 platform. Signed-off-by: Baolin Wang --- arch/arm64/boot/dts/sprd/whale2.dtsi | 35 ++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) -- 1.7.9.5 diff --git a/arch/arm64/boot/dts/sprd/whale2.dtsi b/arch/arm64/boot/dts/sprd/whale2.dtsi index b5c5dce..86ec2b0 100644 --- a/arch/arm64/boot/dts/sprd/whale2.dtsi +++ b/arch/arm64/boot/dts/sprd/whale2.dtsi @@ -168,6 +168,34 @@ vdd-supply = <&vddusb33>; sprd,vdd-voltage = <3300000>; }; + + sdio3: sdio@50430000 { + compatible = "sprd,sdhci-r11"; + reg = <0 0x50430000 0 0x1000>; + interrupts = ; + + clock-names = "sdio", "enable", "2x_enable"; + clocks = <&aon_prediv CLK_EMMC_2X>, + <&apahb_gate CLK_EMMC_EB>, + <&aon_gate CLK_EMMC_2X_EN>; + assigned-clocks = <&aon_prediv CLK_EMMC_2X>; + assigned-clock-parents = <&clk_l0_409m6>; + + sprd,phy-delay-mmc-hs400 = <0x44 0x7f 0x2e 0x2e>; + sprd,phy-delay-mmc-hs200 = <0x0 0x8c 0x8c 0x8c>; + sprd,phy-delay-mmc-ddr52 = <0x3f 0x75 0x14 0x14>; + sprd,phy-delay-mmc-hs400es = <0x3f 0x3f 0x2e 0x2e>; + vmmc-supply = <&vddemmccore>; + bus-width = <8>; + non-removable; + no-sdio; + no-sd; + cap-mmc-hw-reset; + mmc-hs400-enhanced-strobe; + mmc-hs400-1_8v; + mmc-hs200-1_8v; + mmc-ddr-1_8v; + }; }; aon { @@ -310,4 +338,11 @@ clock-frequency = <100000000>; clock-output-names = "ext-rco-100m"; }; + + clk_l0_409m6: clk_l0_409m6 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <409600000>; + clock-output-names = "ext-409m6"; + }; };