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[209.51.188.17]) by mx.google.com with ESMTPS id c64-20020ae9ed43000000b007463cdd2a59si1768884qkg.675.2023.03.20.03.11.13 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 20 Mar 2023 03:11:13 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=J1FYxKVV; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1peCTY-0003lv-WC; Mon, 20 Mar 2023 06:10:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1peCTQ-0003kc-MU for qemu-devel@nongnu.org; Mon, 20 Mar 2023 06:10:42 -0400 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1peCTP-0000CI-1u for qemu-devel@nongnu.org; Mon, 20 Mar 2023 06:10:40 -0400 Received: by mail-wm1-x32b.google.com with SMTP id o32so690058wms.1 for ; Mon, 20 Mar 2023 03:10:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1679307036; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=H7w228qMV522vrZs8kcDs+ryF/z3Qx23mEIba2VleiM=; b=J1FYxKVVugjFuJuf+X3ZiP3R9eiR3UOQiMW0huLiK70p0rhYEXs6XUECflTGFM4BBp BaacGM7TebtC/ksSciddGBJBi3/dypyja7sZJP2MhxIaQB4SgMuewzWTczac20cG6Cpx vqlM5M1u0IkM8rzj81nPU2p7/DcMv7WqQIsuEQkZEy++X/LmitpnRtEUGBVHUotXHAsO /WIm2ES4Gq76pcwLM6vL1OzcolRBjyIAYi/98oaXN+gOhTLOTLFB+Xd58ggyDcd1sRwR UxgK5zUk6MSQm9jQTrhydo6peY6dCmFz01ZRuGdobThQew2f2WFhCoQ8esTG7LbxGSgS /xWQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679307036; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=H7w228qMV522vrZs8kcDs+ryF/z3Qx23mEIba2VleiM=; b=2mmRonhVSHvxjVrzn6PLmbuKfnMJsU5j415Z4WiMCK7jwi6kPpZkugMpiZ2OQUDUuK yfFDwKGyGaQ604vlFpv4igO779TV3ZZ2RnEgIuvRyUef3fNg29IBJD5yV6EB5d1hqilx YtG6xQ9AZ8ZEQNfdX31ibRPjnNETtxOxlWbTF0ApEszvc+od2LHOG6hAp/HNX6ysCeX0 kbffduL1/Fo7TRceXBfBww+dWCmuHg7ywyXABLuriktPj9OFWpdCtt9GrHAoBO+PhYPM jiLkJj8cFAs1x2VChcZoBVm5wSUqa2EkS6yROS7zm+VTOWVVlNu0uWNtxQxjqVrb2yyL N1Fg== X-Gm-Message-State: AO0yUKW9dU35kyjsYjU5RWUyrTUJcYlFGSp/3Y954iTLH9G27l6loF6L a46In524fAJpGITscfVKh3zanQ== X-Received: by 2002:a7b:ce99:0:b0:3ee:126b:4a11 with SMTP id q25-20020a7bce99000000b003ee126b4a11mr623974wmj.6.1679307036739; Mon, 20 Mar 2023 03:10:36 -0700 (PDT) Received: from zen.linaroharston ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id k10-20020a5d6e8a000000b002d1daafea30sm8480224wrz.34.2023.03.20.03.10.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Mar 2023 03:10:36 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id E4E9E1FFB8; Mon, 20 Mar 2023 10:10:35 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: Alessandro Di Federico , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , qemu-devel@nongnu.org Cc: Richard Henderson , Paolo Bonzini , Eduardo Habkost , =?utf-8?q?Alex_Benn=C3=A9e?= Subject: [PATCH 01/10] metadata: add .git-blame-ignore-revs Date: Mon, 20 Mar 2023 10:10:26 +0000 Message-Id: <20230320101035.2214196-2-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230320101035.2214196-1-alex.bennee@linaro.org> References: <20230320101035.2214196-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Someone mentioned this on IRC so I thought I would try it out with a few commits that are pure code style fixes. Signed-off-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé --- .git-blame-ignore-revs | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100644 .git-blame-ignore-revs diff --git a/.git-blame-ignore-revs b/.git-blame-ignore-revs new file mode 100644 index 0000000000..24208ece8c --- /dev/null +++ b/.git-blame-ignore-revs @@ -0,0 +1,18 @@ +# +# List of code-formatting clean ups the git blame can ignore +# +# git blame --ignore-revs-file .git-blame-ignore-revs +# +# or +# +# git config blame.ignoreRevsFile .git-blame-ignore-revs +# + +# gdbstub: clean-up indents +ad9e4585b3c7425759d3eea697afbca71d2c2082 + +# e1000e: fix code style +0eadd56bf53ab196a16d492d7dd31c62e1c24c32 + +# target/riscv: coding style fixes +8c7feddddd9218b407792120bcfda0347ed16205 From patchwork Mon Mar 20 10:10:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 665187 Delivered-To: patch@linaro.org Received: by 2002:a5d:5602:0:0:0:0:0 with SMTP id l2csp1036895wrv; Mon, 20 Mar 2023 03:12:10 -0700 (PDT) X-Google-Smtp-Source: AK7set/3ym6Al9sIb7meFJQjEUS7ZLczyS6AhO82UCvAm8sdYvcYwDeNGdAkJoA0pYYo06a3vRjm X-Received: by 2002:ac8:5793:0:b0:3e3:5ac8:c17f with SMTP id v19-20020ac85793000000b003e35ac8c17fmr842360qta.4.1679307130588; Mon, 20 Mar 2023 03:12:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1679307130; cv=none; d=google.com; s=arc-20160816; b=tX66gzb0W/suSbe0uwplo5XCZMEK4NmtP0EbcaDQtPQN8CGQPtySDvYBTQZkaExKh6 oEF2DIrcSredzHdXV6QvPKlKzk/yxTS0IU37NeQSh3jK0Hw/Dse0x8jLCKAvxuWQbeu0 gYP6elzQc5SLcl6+iPfbNy0Wg8+qHMktDElJCtOH2Af5svIz4aTc+7dyJeiKILi1KIsx vcANHN28fBjI31lw+xsI3r+NB9udjy5Vdf00b6EUzM2jkQLJsRh1e/6eWeI+wLt1ONDy guXReMS7o1vDf5QDD+VNq9rmcefgCYhyCE/XJhBMqJLXT01eMSnTnBYp3OE3ml8R5UJT HITw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=lkGhHF/Bbg/xrVEDUpY4Rq5VsWgFg/qhGJTCVRi4OCI=; b=bmg9tE1dlR+TLqxUnX3D5kfxr1RYWHbVPh2ndfu4FJxam6d779a+m5HNvScv+WbIAs svABMM0JNLed0Pr0V3CWiThtvuyjB2HBGY3f8ZAAVHVyYzE5ta1MQfWYnxVOLbMaqmyK musgmgi7XeMcTE4lWI2iQ1YC79KNnb9fElDM/2jZE6GzN9R1Rut+x//YBQMSfohn3EHq smtuz40uH7fswTDSIXiW+Wpy/2PXEmxwzvw6ZNs1P6W3Aq4IhdTUYGYhBMxV9pjEbzjF Xrj9634iV1C4aft3jamH/2XHx+OH8RdahbBo/VXmgM05yLWaXAvBFeVuzjIfvc8H/bDv sRuA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="B/qIpmA+"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id br32-20020a05620a462000b007460166a3f7si1660789qkb.380.2023.03.20.03.12.10 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 20 Mar 2023 03:12:10 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="B/qIpmA+"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1peCTb-0003mT-GB; Mon, 20 Mar 2023 06:10:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1peCTR-0003ke-94 for qemu-devel@nongnu.org; Mon, 20 Mar 2023 06:10:42 -0400 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1peCTP-0000CO-94 for qemu-devel@nongnu.org; Mon, 20 Mar 2023 06:10:41 -0400 Received: by mail-wr1-x42d.google.com with SMTP id y14so9756927wrq.4 for ; Mon, 20 Mar 2023 03:10:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1679307037; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lkGhHF/Bbg/xrVEDUpY4Rq5VsWgFg/qhGJTCVRi4OCI=; b=B/qIpmA+PwpepOvsnR7yA/h9x7ITqpE2H8ciuXD6XjIoWk2PHhlZU/72Y7cr/UzN43 Xtg9SRiKnMZ38REdxOd181X9Yx1ehkiHqoqzzaba9ZRZsjyijzvslwd7wJQkqMeYJAom D2UX/h8V5/Nss/MZFL6dLD8uIYaG+hS9ZPGPwrfxd7Ikqibasn5df/h0SXlFlKe14/Xa ETLDlY1UGxRbE3D8EHtjlkPivfV/FJbFX9vZ8qsvw0Y1lgqQGXdAUwBfDkQXAVN092pz GkBHPdKaIiEJJXuQOT96VHFf0xHbrldejHdcYSuX9qlNnbomkRLqSYV+rrmxDuGnvsIg qwhA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679307037; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lkGhHF/Bbg/xrVEDUpY4Rq5VsWgFg/qhGJTCVRi4OCI=; b=5c3b8hmp1F1rXPe7+pO89gkDVj2KpVMlLuQevPVooBcF8odmPlfAF+vuQXneMJMFuF 9/Fyv81PdKOickIBrcgbV3qoCRYmHUa0OPOGTlQhbMST7kiKY7uayCADEW8JJuf5lZOF tOTMgEx4bKhh9vNylir6NgPh2q+Ba8z8PKFIRf2G12fq0wnqI+aKkcGD/a7hfXWfbpgC 7PZ42+X2PCDRfJPu+YgecsR2b0gvBjMNYeSIORADZmHt2wwWbDjcY6mmVrhnpfwcv1p/ d9Aa7uId9dqlaZlr6fL/+UUYj1/oyOnpAddGgAx7LhGYr8DsibRdGUfL6Ok/VEVAMUQU C3HQ== X-Gm-Message-State: AO0yUKWd7nd2c34C/LT2xBaJI+MRq7X2AaW2SP4+INvxp0Datnr9cxF2 PZJVMfKe1Pwttkje1eSq1gjCIbODmya5MTsF/iA= X-Received: by 2002:a5d:4090:0:b0:2cf:aa6e:3ade with SMTP id o16-20020a5d4090000000b002cfaa6e3ademr13175365wrp.15.1679307037009; Mon, 20 Mar 2023 03:10:37 -0700 (PDT) Received: from zen.linaroharston ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id b9-20020a05600010c900b002c7163660a9sm8495893wrx.105.2023.03.20.03.10.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Mar 2023 03:10:36 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 0BB361FFBA; Mon, 20 Mar 2023 10:10:36 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: Alessandro Di Federico , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , qemu-devel@nongnu.org Cc: Richard Henderson , Paolo Bonzini , Eduardo Habkost , =?utf-8?q?Alex_Benn=C3=A9e?= Subject: [PATCH 02/10] accel/tcg: move cpu_reloading_memory_map into cpu-exec-softmmu Date: Mon, 20 Mar 2023 10:10:27 +0000 Message-Id: <20230320101035.2214196-3-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230320101035.2214196-1-alex.bennee@linaro.org> References: <20230320101035.2214196-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This doesn't save much as cpu-exec-common still needs to be built per-target for its knowledge of CPUState but this helps with keeping things organised. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson Reviewed-by: Alessandro Di Federico --- accel/tcg/cpu-exec-common.c | 30 ---------------------- accel/tcg/cpu-exec-softmmu.c | 50 ++++++++++++++++++++++++++++++++++++ accel/tcg/meson.build | 10 ++++++++ 3 files changed, 60 insertions(+), 30 deletions(-) create mode 100644 accel/tcg/cpu-exec-softmmu.c diff --git a/accel/tcg/cpu-exec-common.c b/accel/tcg/cpu-exec-common.c index e7962c9348..c6b0ad303e 100644 --- a/accel/tcg/cpu-exec-common.c +++ b/accel/tcg/cpu-exec-common.c @@ -32,36 +32,6 @@ void cpu_loop_exit_noexc(CPUState *cpu) cpu_loop_exit(cpu); } -#if defined(CONFIG_SOFTMMU) -void cpu_reloading_memory_map(void) -{ - if (qemu_in_vcpu_thread() && current_cpu->running) { - /* The guest can in theory prolong the RCU critical section as long - * as it feels like. The major problem with this is that because it - * can do multiple reconfigurations of the memory map within the - * critical section, we could potentially accumulate an unbounded - * collection of memory data structures awaiting reclamation. - * - * Because the only thing we're currently protecting with RCU is the - * memory data structures, it's sufficient to break the critical section - * in this callback, which we know will get called every time the - * memory map is rearranged. - * - * (If we add anything else in the system that uses RCU to protect - * its data structures, we will need to implement some other mechanism - * to force TCG CPUs to exit the critical section, at which point this - * part of this callback might become unnecessary.) - * - * This pair matches cpu_exec's rcu_read_lock()/rcu_read_unlock(), which - * only protects cpu->as->dispatch. Since we know our caller is about - * to reload it, it's safe to split the critical section. - */ - rcu_read_unlock(); - rcu_read_lock(); - } -} -#endif - void cpu_loop_exit(CPUState *cpu) { /* Undo the setting in cpu_tb_exec. */ diff --git a/accel/tcg/cpu-exec-softmmu.c b/accel/tcg/cpu-exec-softmmu.c new file mode 100644 index 0000000000..2318dd8c7d --- /dev/null +++ b/accel/tcg/cpu-exec-softmmu.c @@ -0,0 +1,50 @@ +/* + * Emulator main CPU execution loop, softmmu bits + * + * Copyright (c) 2003-2005 Fabrice Bellard + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "hw/core/cpu.h" +#include "sysemu/cpus.h" + +void cpu_reloading_memory_map(void) +{ + if (qemu_in_vcpu_thread() && current_cpu->running) { + /* The guest can in theory prolong the RCU critical section as long + * as it feels like. The major problem with this is that because it + * can do multiple reconfigurations of the memory map within the + * critical section, we could potentially accumulate an unbounded + * collection of memory data structures awaiting reclamation. + * + * Because the only thing we're currently protecting with RCU is the + * memory data structures, it's sufficient to break the critical section + * in this callback, which we know will get called every time the + * memory map is rearranged. + * + * (If we add anything else in the system that uses RCU to protect + * its data structures, we will need to implement some other mechanism + * to force TCG CPUs to exit the critical section, at which point this + * part of this callback might become unnecessary.) + * + * This pair matches cpu_exec's rcu_read_lock()/rcu_read_unlock(), which + * only protects cpu->as->dispatch. Since we know our caller is about + * to reload it, it's safe to split the critical section. + */ + rcu_read_unlock(); + rcu_read_lock(); + } +} diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build index aeb20a6ef0..bdc086b90d 100644 --- a/accel/tcg/meson.build +++ b/accel/tcg/meson.build @@ -1,3 +1,9 @@ +# +# Currently most things here end up in specific_ss eventually because +# they need knowledge of CPUState. Stuff that that doesn't can live in +# common user, softmmu or overall code +# + tcg_ss = ss.source_set() tcg_ss.add(files( 'tcg-all.c', @@ -9,6 +15,7 @@ tcg_ss.add(files( 'translate-all.c', 'translator.c', )) + tcg_ss.add(when: 'CONFIG_USER_ONLY', if_true: files('user-exec.c')) tcg_ss.add(when: 'CONFIG_SOFTMMU', if_false: files('user-exec-stub.c')) tcg_ss.add(when: 'CONFIG_PLUGIN', if_true: [files('plugin-gen.c')]) @@ -27,3 +34,6 @@ tcg_module_ss.add(when: ['CONFIG_SOFTMMU', 'CONFIG_TCG'], if_true: files( 'tcg-accel-ops-icount.c', 'tcg-accel-ops-rr.c', )) + +# Common softmmu code +softmmu_ss.add(files('cpu-exec-softmmu.c')) From patchwork Mon Mar 20 10:10:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 665185 Delivered-To: patch@linaro.org Received: by 2002:a5d:5602:0:0:0:0:0 with SMTP id l2csp1036777wrv; Mon, 20 Mar 2023 03:11:45 -0700 (PDT) X-Google-Smtp-Source: AK7set+rysdL0bzTe3Vmeb1ZgWXWeyQkZ0ss3QxBUrsYPxjY+DQU/uh34VbTSzYynr5Fz8Y0Px2r X-Received: by 2002:a05:622a:1792:b0:3c0:3d68:540c with SMTP id s18-20020a05622a179200b003c03d68540cmr22756271qtk.65.1679307105070; Mon, 20 Mar 2023 03:11:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1679307105; cv=none; d=google.com; s=arc-20160816; b=spbN3kMTgvvr1TeTK5l//sEPycHfl8Hj++mD3ujNf/4u/Vxk/B/wDchIFZ87I7vfQ9 bTPSPzneZ9duj9GJEIPElZcsvIrB2VZyE+qDnDq4vnccBPiEq7yXPPpwSc12j4jJ4SXc OnEXu9MfG7q8yLbivQhlPuz/5cy8c7ANjdByCksXsWOPLEp4yzIqp9QktC+Go8VDUtgu T3oJkC4t/LdFx0rC7gi15/2iNik+1brnGdKOKxcGY0f3bhuOhKSF9IG9Xmf9hFMJMQKF A6dJoJz85TQArWeYZV65Ua1Rd8ajslhPwfxA0WEofsL+w03W5Tb4Omlc5XJFoWTcomtz dD5w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=NlG2WYAuWf1MF90p6NWRpZT5faSFXPhuXyYZFUB3mGE=; b=EY41V7vYYP6KbqBvi8gETpe39awj8ye9tc+dy51O7JzbFkmWYjVa9DNWKl0HOGVwcL 06AWTuPLodEPOhmCxI3EgSfDPrt5axDSAfMdx94I2Qageenhamnxa7iiVrQMrHw0zEV/ YW1CyP9dVZHstSWvddPmLs6r5wCwGPGJfXpW3rHJ+XywryCqZrhE8LO5uKd+BxgUaRRw Nr160t3ZLJjelXkDrtwm8OdtoW009b+jQgztORCOjC93TQ7xGR9jmNVFsqgrEHHZNVyN z4dLbHxb482DzDIH474icrYNqdyKt/ao5rYJ0qNnBnBWUwvsn4PByFw09i+xoQKV39a5 uj0w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ffefsSjP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé --- include/hw/core/sysemu-cpu-ops.h | 5 +++++ target/i386/cpu-internal.h | 1 + accel/tcg/cpu-exec.c | 14 +++----------- target/i386/cpu-sysemu.c | 12 ++++++++++++ target/i386/cpu.c | 1 + 5 files changed, 22 insertions(+), 11 deletions(-) diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h index ee169b872c..c9d30172c4 100644 --- a/include/hw/core/sysemu-cpu-ops.h +++ b/include/hw/core/sysemu-cpu-ops.h @@ -48,6 +48,11 @@ typedef struct SysemuCPUOps { * GUEST_PANICKED events. */ GuestPanicInformation* (*get_crash_info)(CPUState *cpu); + /** + * @handle_cpu_halt: Callback for special handling during cpu_handle_halt() + * @cs: The CPUState + */ + void (*handle_cpu_halt)(CPUState *cpu); /** * @write_elf32_note: Callback for writing a CPU-specific ELF note to a * 32-bit VM coredump. diff --git a/target/i386/cpu-internal.h b/target/i386/cpu-internal.h index 9baac5c0b4..75b302fb33 100644 --- a/target/i386/cpu-internal.h +++ b/target/i386/cpu-internal.h @@ -65,6 +65,7 @@ void x86_cpu_get_crash_info_qom(Object *obj, Visitor *v, void x86_cpu_apic_create(X86CPU *cpu, Error **errp); void x86_cpu_apic_realize(X86CPU *cpu, Error **errp); void x86_cpu_machine_reset_cb(void *opaque); +void x86_cpu_handle_halt(CPUState *cs); #endif /* !CONFIG_USER_ONLY */ #endif /* I386_CPU_INTERNAL_H */ diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index c815f2dbfd..5e5906e199 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -22,6 +22,7 @@ #include "qapi/error.h" #include "qapi/type-helpers.h" #include "hw/core/tcg-cpu-ops.h" +#include "hw/core/sysemu-cpu-ops.h" #include "trace.h" #include "disas/disas.h" #include "exec/exec-all.h" @@ -30,9 +31,6 @@ #include "qemu/rcu.h" #include "exec/log.h" #include "qemu/main-loop.h" -#if defined(TARGET_I386) && !defined(CONFIG_USER_ONLY) -#include "hw/i386/apic.h" -#endif #include "sysemu/cpus.h" #include "exec/cpu-all.h" #include "sysemu/cpu-timers.h" @@ -650,15 +648,9 @@ static inline bool cpu_handle_halt(CPUState *cpu) { #ifndef CONFIG_USER_ONLY if (cpu->halted) { -#if defined(TARGET_I386) - if (cpu->interrupt_request & CPU_INTERRUPT_POLL) { - X86CPU *x86_cpu = X86_CPU(cpu); - qemu_mutex_lock_iothread(); - apic_poll_irq(x86_cpu->apic_state); - cpu_reset_interrupt(cpu, CPU_INTERRUPT_POLL); - qemu_mutex_unlock_iothread(); + if (cpu->cc->sysemu_ops->handle_cpu_halt) { + cpu->cc->sysemu_ops->handle_cpu_halt(cpu); } -#endif /* TARGET_I386 */ if (!cpu_has_work(cpu)) { return true; } diff --git a/target/i386/cpu-sysemu.c b/target/i386/cpu-sysemu.c index 28115edf44..e545bf7590 100644 --- a/target/i386/cpu-sysemu.c +++ b/target/i386/cpu-sysemu.c @@ -18,6 +18,7 @@ */ #include "qemu/osdep.h" +#include "qemu/main-loop.h" #include "cpu.h" #include "sysemu/xen.h" #include "sysemu/whpx.h" @@ -310,6 +311,17 @@ void x86_cpu_apic_realize(X86CPU *cpu, Error **errp) } } +void x86_cpu_handle_halt(CPUState *cpu) +{ + if (cpu->interrupt_request & CPU_INTERRUPT_POLL) { + X86CPU *x86_cpu = X86_CPU(cpu); + qemu_mutex_lock_iothread(); + apic_poll_irq(x86_cpu->apic_state); + cpu_reset_interrupt(cpu, CPU_INTERRUPT_POLL); + qemu_mutex_unlock_iothread(); + } +} + GuestPanicInformation *x86_cpu_get_crash_info(CPUState *cs) { X86CPU *cpu = X86_CPU(cs); diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 6576287e5b..67027d28b0 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7241,6 +7241,7 @@ static const struct SysemuCPUOps i386_sysemu_ops = { .get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug, .asidx_from_attrs = x86_asidx_from_attrs, .get_crash_info = x86_cpu_get_crash_info, + .handle_cpu_halt = x86_cpu_handle_halt, .write_elf32_note = x86_cpu_write_elf32_note, .write_elf64_note = x86_cpu_write_elf64_note, .write_elf32_qemunote = x86_cpu_write_elf32_qemunote, From patchwork Mon Mar 20 10:10:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 665190 Delivered-To: patch@linaro.org Received: by 2002:a5d:5602:0:0:0:0:0 with SMTP id l2csp1037135wrv; Mon, 20 Mar 2023 03:12:51 -0700 (PDT) X-Google-Smtp-Source: AK7set+QUk6QRMkSfMrJhaztKKmoEJRZbGpFfmS73tEcSalKifebyr8KBjYKbqXJZ2H6gMhxR3XG X-Received: by 2002:a05:6214:258e:b0:5ad:13a6:b45b with SMTP id fq14-20020a056214258e00b005ad13a6b45bmr32846613qvb.11.1679307171329; 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Front ends that don't understand the flag will ignore it anyway. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- accel/tcg/cpu-exec.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 5e5906e199..f883be197f 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -309,14 +309,11 @@ static void log_cpu_exec(target_ulong pc, CPUState *cpu, if (qemu_loglevel_mask(CPU_LOG_TB_CPU)) { FILE *logfile = qemu_log_trylock(); if (logfile) { - int flags = 0; + int flags = CPU_DUMP_CCOP;; if (qemu_loglevel_mask(CPU_LOG_TB_FPU)) { flags |= CPU_DUMP_FPU; } -#if defined(TARGET_I386) - flags |= CPU_DUMP_CCOP; -#endif cpu_dump_state(cpu, logfile, flags); qemu_log_unlock(logfile); } From patchwork Mon Mar 20 10:10:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 665188 Delivered-To: patch@linaro.org Received: by 2002:a5d:5602:0:0:0:0:0 with SMTP id l2csp1037028wrv; Mon, 20 Mar 2023 03:12:35 -0700 (PDT) X-Google-Smtp-Source: AK7set+2GUjjQU4yhqcPa5VPyaBpoNh5Sn7s1urQj/IqcQDci8S2s3FF9DeYGhNrzw1n1fCCv9G9 X-Received: by 2002:a05:6214:2584:b0:5ac:c5a1:7ced with SMTP id fq4-20020a056214258400b005acc5a17cedmr41556734qvb.0.1679307155535; Mon, 20 Mar 2023 03:12:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1679307155; cv=none; d=google.com; s=arc-20160816; b=a/EXrL5HCW+K8yqSYdwbXHKwioHqLemIrOK/mu4telcxkI8oE5LwMbNYsybAcO7K07 X3ziuE8Lg3GoYaZPnne2dTsxRr5hmPdMpmKaJw5XbttDTcvYJqq6fSrKiK7Shxbtjbbw m4nHk+5Jdkj4xPlrMa4q6AhIxC5tpE39iMyGnoB1FuRAKVGn26rpsRX5olOfqGs5ajG5 gepL0qiDpqzauj7ACusxQ6f5mGlxCjvF4pm0HjPpdnPNJAPPPWopFetX4eXBy4wAgkZI OliRCQfMxInrDmVB7Le9PbCzUNB+yGVLaSHV9fzwS1u58Dips95Kap3ZOLwmslmxLqQF PKAg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=zAnVh7k03xLE58mG3oLOMO1waepQbpwXIySIk1v3C+8=; b=rBpwGe7f1ZvqT0o/X+bOrPxxCz9ro2QoOiq8jRHpWWxSoeGv2X5kWNcVpXW+DUOvdd XfEI7JuBFDcn60SvAUjRRjJ3RLrO5yGKieHbF10PuW60IHNUs7YkAAFKF09E8gw39vfu gXwOyxZBtXJRsU+TrzgVYoXD/9NQZCQ7RmN1K8QkQTtlYFee2KcH6BghKySOWDIT9MT0 Q8tpqSp/hIdgSgwjCk7+L1XJhf37Tyu1175pecaCi4GvmI3Nvo4xLOcHy6eBQy2Ner5A 2mzEFw+t62RiY1oEVJLw8epeoW3Ghu4XaUz/cj9DVY3NC5O0C+uWCcD8Uj6H/MWJu/oq DLlA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XsM+Jvwx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Mon, 20 Mar 2023 03:10:38 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 592A51FFBD; Mon, 20 Mar 2023 10:10:36 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: Alessandro Di Federico , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , qemu-devel@nongnu.org Cc: Richard Henderson , Paolo Bonzini , Eduardo Habkost , =?utf-8?q?Alex_Benn=C3=A9e?= Subject: [PATCH 05/10] accel/tcg: remove the fake_user_interrupt guards Date: Mon, 20 Mar 2023 10:10:30 +0000 Message-Id: <20230320101035.2214196-6-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230320101035.2214196-1-alex.bennee@linaro.org> References: <20230320101035.2214196-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org At the cost of an empty tcg_ops field for most targets we can avoid target specific hacks in cpu-exec.c Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- include/hw/core/tcg-cpu-ops.h | 2 +- accel/tcg/cpu-exec.c | 14 +++++++------- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index 20e3c0ffbb..66c0cecdde 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -50,7 +50,7 @@ struct TCGCPUOps { void (*debug_excp_handler)(CPUState *cpu); #ifdef NEED_CPU_H -#if defined(CONFIG_USER_ONLY) && defined(TARGET_I386) +#if defined(CONFIG_USER_ONLY) /** * @fake_user_interrupt: Callback for 'fake exception' handling. * diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index f883be197f..ea2e7004fe 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -698,13 +698,13 @@ static inline bool cpu_handle_exception(CPUState *cpu, int *ret) return true; } else { #if defined(CONFIG_USER_ONLY) - /* if user mode only, we simulate a fake exception - which will be handled outside the cpu execution - loop */ -#if defined(TARGET_I386) - CPUClass *cc = CPU_GET_CLASS(cpu); - cc->tcg_ops->fake_user_interrupt(cpu); -#endif /* TARGET_I386 */ + /* + * For some user mode handling we simulate a fake exception + * which will be handled outside the cpu execution loop + */ + if (cpu->cc->tcg_ops->fake_user_interrupt) { + cpu->cc->tcg_ops->fake_user_interrupt(cpu); + } *ret = cpu->exception_index; cpu->exception_index = -1; return true; From patchwork Mon Mar 20 10:10:31 2023 Content-Type: text/plain; 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Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson Reviewed-by: Alessandro Di Federico --- include/exec/cpu-all.h | 52 +------------------------- include/exec/cpu-irq.h | 83 ++++++++++++++++++++++++++++++++++++++++++ include/exec/poison.h | 13 ------- 3 files changed, 84 insertions(+), 64 deletions(-) create mode 100644 include/exec/cpu-irq.h diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 2eb1176538..6b8085cf19 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -297,57 +297,7 @@ void *page_get_target_data(target_ulong address) CPUArchState *cpu_copy(CPUArchState *env); -/* Flags for use in ENV->INTERRUPT_PENDING. - - The numbers assigned here are non-sequential in order to preserve - binary compatibility with the vmstate dump. Bit 0 (0x0001) was - previously used for CPU_INTERRUPT_EXIT, and is cleared when loading - the vmstate dump. */ - -/* External hardware interrupt pending. This is typically used for - interrupts from devices. */ -#define CPU_INTERRUPT_HARD 0x0002 - -/* Exit the current TB. This is typically used when some system-level device - makes some change to the memory mapping. E.g. the a20 line change. */ -#define CPU_INTERRUPT_EXITTB 0x0004 - -/* Halt the CPU. */ -#define CPU_INTERRUPT_HALT 0x0020 - -/* Debug event pending. */ -#define CPU_INTERRUPT_DEBUG 0x0080 - -/* Reset signal. */ -#define CPU_INTERRUPT_RESET 0x0400 - -/* Several target-specific external hardware interrupts. Each target/cpu.h - should define proper names based on these defines. */ -#define CPU_INTERRUPT_TGT_EXT_0 0x0008 -#define CPU_INTERRUPT_TGT_EXT_1 0x0010 -#define CPU_INTERRUPT_TGT_EXT_2 0x0040 -#define CPU_INTERRUPT_TGT_EXT_3 0x0200 -#define CPU_INTERRUPT_TGT_EXT_4 0x1000 - -/* Several target-specific internal interrupts. These differ from the - preceding target-specific interrupts in that they are intended to - originate from within the cpu itself, typically in response to some - instruction being executed. These, therefore, are not masked while - single-stepping within the debugger. */ -#define CPU_INTERRUPT_TGT_INT_0 0x0100 -#define CPU_INTERRUPT_TGT_INT_1 0x0800 -#define CPU_INTERRUPT_TGT_INT_2 0x2000 - -/* First unused bit: 0x4000. */ - -/* The set of all bits that should be masked when single-stepping. */ -#define CPU_INTERRUPT_SSTEP_MASK \ - (CPU_INTERRUPT_HARD \ - | CPU_INTERRUPT_TGT_EXT_0 \ - | CPU_INTERRUPT_TGT_EXT_1 \ - | CPU_INTERRUPT_TGT_EXT_2 \ - | CPU_INTERRUPT_TGT_EXT_3 \ - | CPU_INTERRUPT_TGT_EXT_4) +#include "exec/cpu-irq.h" #ifdef CONFIG_USER_ONLY diff --git a/include/exec/cpu-irq.h b/include/exec/cpu-irq.h new file mode 100644 index 0000000000..58bd98d812 --- /dev/null +++ b/include/exec/cpu-irq.h @@ -0,0 +1,83 @@ +/* + * Internal execution defines for qemu irqs + * + * Copyright (c) 2003 Fabrice Bellard + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#ifndef EXEC_CPU_IRQ_H +#define EXEC_CPU_IRQ_H + +/* + * Flags for use in ENV->INTERRUPT_PENDING. + * + * The numbers assigned here are non-sequential in order to preserve + * binary compatibility with the vmstate dump. Bit 0 (0x0001) was + * previously used for CPU_INTERRUPT_EXIT, and is cleared when loading + * the vmstate dump. + */ + +/* + * External hardware interrupt pending. This is typically used for + * interrupts from devices. + */ +#define CPU_INTERRUPT_HARD 0x0002 + +/* + * Exit the current TB. This is typically used when some system-level device + * makes some change to the memory mapping. E.g. the a20 line change. + */ +#define CPU_INTERRUPT_EXITTB 0x0004 + +/* Halt the CPU. */ +#define CPU_INTERRUPT_HALT 0x0020 + +/* Debug event pending. */ +#define CPU_INTERRUPT_DEBUG 0x0080 + +/* Reset signal. */ +#define CPU_INTERRUPT_RESET 0x0400 + +/* Several target-specific external hardware interrupts. Each target/cpu.h + should define proper names based on these defines. */ +#define CPU_INTERRUPT_TGT_EXT_0 0x0008 +#define CPU_INTERRUPT_TGT_EXT_1 0x0010 +#define CPU_INTERRUPT_TGT_EXT_2 0x0040 +#define CPU_INTERRUPT_TGT_EXT_3 0x0200 +#define CPU_INTERRUPT_TGT_EXT_4 0x1000 + +/* + * Several target-specific internal interrupts. These differ from the + * preceding target-specific interrupts in that they are intended to + * originate from within the cpu itself, typically in response to some + * instruction being executed. These, therefore, are not masked while + * single-stepping within the debugger. + */ +#define CPU_INTERRUPT_TGT_INT_0 0x0100 +#define CPU_INTERRUPT_TGT_INT_1 0x0800 +#define CPU_INTERRUPT_TGT_INT_2 0x2000 + +/* First unused bit: 0x4000. */ + +/* The set of all bits that should be masked when single-stepping. */ +#define CPU_INTERRUPT_SSTEP_MASK \ + (CPU_INTERRUPT_HARD \ + | CPU_INTERRUPT_TGT_EXT_0 \ + | CPU_INTERRUPT_TGT_EXT_1 \ + | CPU_INTERRUPT_TGT_EXT_2 \ + | CPU_INTERRUPT_TGT_EXT_3 \ + | CPU_INTERRUPT_TGT_EXT_4) + +#endif /* EXEC_CPU_IRQ_H */ diff --git a/include/exec/poison.h b/include/exec/poison.h index 140daa4a85..a0ab1d7d46 100644 --- a/include/exec/poison.h +++ b/include/exec/poison.h @@ -52,19 +52,6 @@ #pragma GCC poison TARGET_PAGE_BITS #pragma GCC poison TARGET_PAGE_ALIGN -#pragma GCC poison CPU_INTERRUPT_HARD -#pragma GCC poison CPU_INTERRUPT_EXITTB -#pragma GCC poison CPU_INTERRUPT_HALT -#pragma GCC poison CPU_INTERRUPT_DEBUG -#pragma GCC poison CPU_INTERRUPT_TGT_EXT_0 -#pragma GCC poison CPU_INTERRUPT_TGT_EXT_1 -#pragma GCC poison CPU_INTERRUPT_TGT_EXT_2 -#pragma GCC poison CPU_INTERRUPT_TGT_EXT_3 -#pragma GCC poison CPU_INTERRUPT_TGT_EXT_4 -#pragma GCC poison CPU_INTERRUPT_TGT_INT_0 -#pragma GCC poison CPU_INTERRUPT_TGT_INT_1 -#pragma GCC poison CPU_INTERRUPT_TGT_INT_2 - #pragma GCC poison CONFIG_ALPHA_DIS #pragma GCC poison CONFIG_CRIS_DIS #pragma GCC poison CONFIG_HPPA_DIS From patchwork Mon Mar 20 10:10:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 665186 Delivered-To: patch@linaro.org Received: by 2002:a5d:5602:0:0:0:0:0 with SMTP id l2csp1036795wrv; Mon, 20 Mar 2023 03:11:48 -0700 (PDT) X-Google-Smtp-Source: AK7set/Qc8I5duhLHJsDA2nCvWIWdmkhlU2Rg+s1K35Q9ul7uQoRG78ZDJn17/D67T3gnZ9zSLVN X-Received: by 2002:a05:6214:d07:b0:5c2:b08a:3b9e with SMTP id 7-20020a0562140d0700b005c2b08a3b9emr11359290qvh.29.1679307108784; Mon, 20 Mar 2023 03:11:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1679307108; cv=none; d=google.com; s=arc-20160816; b=ubkrmSrhn0lcRle43qtkHdXOT6ctwVubalc3+VE5kxy0ZCOQrQWnGWC4UcibtCajum oNtGRmxcvAzi2fuuM6HeacOH4luiCaV7EWjkyXVOWAPmYIeOJZ2PbZ2lJxi3W1w8Qp0n 9ux3Gbe5A0jvzOWUZtRBKpL8SoLvMFJg5hZcGv5/+1g48FSdFk2cNse4MQSbxhWvftKW KvWs8/pmxVBdvVWZMiAAEpV0s3Yui1b2qFsdOiZboQ2j44xTth/b9zbXCJmqlnWLiTOG wmFQy+FHdvCYHtzderCT6eo01tO8/3/nFQDbpS9/BOJ3iMsgjSKsUKstkSy+jk1mzZUc jd4g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=4kskGeJQrf9Cxcn5vNzrmuB/lHaeNa1KLZhaRS/P5FA=; b=KmtoqF7ut6kEgKDDwg9zY3eyPGmqoICNaFfm97maviBhWmlcPREWfaQ+5YiIn4vlWx GnznSsXFZxoAI9VE+sfipF89i4TEB8ulO4qLLWmizfSpjPO8kef1IwPYFGEAR8tLNeqe 7IoTTPTxfL0w/qYmur6XIctCh7YgLvpLML2tvj8OTrvhYwIm9wNRzLUdXmxd7QUfcMYa 65jPsCZ9yUtZwc6U8x0pxwhRLRn6vI1Z9Y+rTU2QhLLKg0l252CW+eRKvq/geLqbxW7P tvMEcxRk1hh63YplVBHgsphkv0SQsSgQs55l/QH9hTellwJsfi7L+okGJ/a0lDBgKjF2 P1MQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tVTfBFQe; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- accel/tcg/cpu-exec.c | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index ea2e7004fe..daa6e24daf 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -774,7 +774,9 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, if (unlikely(qatomic_read(&cpu->interrupt_request))) { int interrupt_request; - qemu_mutex_lock_iothread(); + /* If we exit via cpu_loop_exit/longjmp it is reset in cpu_exec */ + QEMU_IOTHREAD_LOCK_GUARD(); + interrupt_request = cpu->interrupt_request; if (unlikely(cpu->singlestep_enabled & SSTEP_NOIRQ)) { /* Mask out external interrupts for this step. */ @@ -783,7 +785,6 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, if (interrupt_request & CPU_INTERRUPT_DEBUG) { cpu->interrupt_request &= ~CPU_INTERRUPT_DEBUG; cpu->exception_index = EXCP_DEBUG; - qemu_mutex_unlock_iothread(); return true; } #if !defined(CONFIG_USER_ONLY) @@ -794,7 +795,6 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, cpu->interrupt_request &= ~CPU_INTERRUPT_HALT; cpu->halted = 1; cpu->exception_index = EXCP_HLT; - qemu_mutex_unlock_iothread(); return true; } #if defined(TARGET_I386) @@ -805,14 +805,12 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, cpu_svm_check_intercept_param(env, SVM_EXIT_INIT, 0, 0); do_cpu_init(x86_cpu); cpu->exception_index = EXCP_HALTED; - qemu_mutex_unlock_iothread(); return true; } #else else if (interrupt_request & CPU_INTERRUPT_RESET) { replay_interrupt(); cpu_reset(cpu); - qemu_mutex_unlock_iothread(); return true; } #endif /* !TARGET_I386 */ @@ -835,7 +833,6 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, */ if (unlikely(cpu->singlestep_enabled)) { cpu->exception_index = EXCP_DEBUG; - qemu_mutex_unlock_iothread(); return true; } cpu->exception_index = -1; @@ -852,9 +849,6 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, the program flow was changed */ *last_tb = NULL; } - - /* If we exit via cpu_loop_exit/longjmp it is reset in cpu_exec */ - qemu_mutex_unlock_iothread(); } /* Finally, check if we need to exit to the main loop. */ From patchwork Mon Mar 20 10:10:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 665181 Delivered-To: patch@linaro.org Received: by 2002:a5d:5602:0:0:0:0:0 with SMTP id l2csp1036559wrv; Mon, 20 Mar 2023 03:11:15 -0700 (PDT) X-Google-Smtp-Source: AK7set+Y+0YOH0nXGJzgoZ1e+RgD8bbbix7Mt+VDWL07NSaihC9P88LSVFMk0uioFhoO14ivC2J0 X-Received: by 2002:ac8:7fc2:0:b0:3e3:3941:d167 with SMTP id b2-20020ac87fc2000000b003e33941d167mr1371503qtk.34.1679307075187; Mon, 20 Mar 2023 03:11:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1679307075; cv=none; d=google.com; s=arc-20160816; b=kaOis17VVLPqgizpH7oSF0gCrioWrHao/2lVxD+SvluvMB7SE0vQbmriml2kmVkfIy 8OXQPVMXtpaT9y+FSp1wNW2GKR2Y8l2FaRATrrE0Cip4WBUq/7l3KVBbPTclz7LG/H/a ShzXm7n4u81uNau5lmKqGwGtM8VTMxy35jfvcLVg/saKN7L3e4PrPUhVV1afQRdnl55N opVZxkF7D+oBbmqNeQQyZMuLiYYvX8doMCSTToUveSfBNITjM1oRCvuI2gFxu5ISR4pW BB/nyrDYtRa8jBGPqzzVNPaFLE/U1/hy6E7GYRv/RZ+OoKl809vz8xzFza2zxWai/sR3 K5CQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=DLYB3843FF7GnXqw2uZL62dMpE0zmO1Pq0/V+yySmyc=; b=C6+D60+aQFo7SjrTCcWUGZX/C5/yD4p3Nv3FCQiZtY/291vi+n67vXN62kbmHEfujB v84o1yCVQsYvjBqw98aRKDdu0jcYwdMYsPwUxkBn2VLh04SGe+mKlEHCPENFyo4/uGuS sMEXF9l0sJLLyA8eiUuVGgoGyBx0xWTMHW/rc+G+mw4ebl1k8Sq4Jtem6eYBZLTJaUzb 76jpZ8GsRSlsA5XSaLqFZX/D8AKQ8TzsajoJ4H/8m9GWs02ZmUSxrEZs2uV7RplKUhTM oXncm1Hw6IrZ/36+RvWKw5eFNLuty4kImsSJwuQk41RE+IyAJby3HjgHgPiEQrcELkdA J6Iw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tsGUSQCe; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Mon, 20 Mar 2023 03:10:38 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id AD1611FFB7; Mon, 20 Mar 2023 10:10:36 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: Alessandro Di Federico , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , qemu-devel@nongnu.org Cc: Richard Henderson , Paolo Bonzini , Eduardo Habkost , =?utf-8?q?Alex_Benn=C3=A9e?= Subject: [PATCH 08/10] accel/tcg: push i386 specific hacks into handle_cpu_interrupt callback Date: Mon, 20 Mar 2023 10:10:33 +0000 Message-Id: <20230320101035.2214196-9-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230320101035.2214196-1-alex.bennee@linaro.org> References: <20230320101035.2214196-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Alex Bennée --- include/hw/core/sysemu-cpu-ops.h | 11 +++++++++++ target/i386/cpu-internal.h | 1 + accel/tcg/cpu-exec-softmmu.c | 16 ++++++++++++++++ accel/tcg/cpu-exec.c | 31 ++++++++++--------------------- target/i386/cpu-sysemu.c | 17 +++++++++++++++++ target/i386/cpu.c | 1 + 6 files changed, 56 insertions(+), 21 deletions(-) diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h index c9d30172c4..d53907b517 100644 --- a/include/hw/core/sysemu-cpu-ops.h +++ b/include/hw/core/sysemu-cpu-ops.h @@ -53,6 +53,15 @@ typedef struct SysemuCPUOps { * @cs: The CPUState */ void (*handle_cpu_halt)(CPUState *cpu); + /** + * @handle_cpu_interrupt: handle init/reset interrupts + * @cs: The CPUState + * @irq_request: the interrupt request + * + * Most architectures share a common handler. Returns true if the + * handler did indeed handle and interrupt. + */ + bool (*handle_cpu_interrupt)(CPUState *cpu, int irq_request); /** * @write_elf32_note: Callback for writing a CPU-specific ELF note to a * 32-bit VM coredump. @@ -94,4 +103,6 @@ typedef struct SysemuCPUOps { } SysemuCPUOps; +bool common_cpu_handle_interrupt(CPUState *cpu, int irq_request); + #endif /* SYSEMU_CPU_OPS_H */ diff --git a/target/i386/cpu-internal.h b/target/i386/cpu-internal.h index 75b302fb33..4fee4e125e 100644 --- a/target/i386/cpu-internal.h +++ b/target/i386/cpu-internal.h @@ -66,6 +66,7 @@ void x86_cpu_apic_create(X86CPU *cpu, Error **errp); void x86_cpu_apic_realize(X86CPU *cpu, Error **errp); void x86_cpu_machine_reset_cb(void *opaque); void x86_cpu_handle_halt(CPUState *cs); +bool x86_cpu_handle_interrupt(CPUState *cpu, int irq_request); #endif /* !CONFIG_USER_ONLY */ #endif /* I386_CPU_INTERNAL_H */ diff --git a/accel/tcg/cpu-exec-softmmu.c b/accel/tcg/cpu-exec-softmmu.c index 2318dd8c7d..89e6cb2e3a 100644 --- a/accel/tcg/cpu-exec-softmmu.c +++ b/accel/tcg/cpu-exec-softmmu.c @@ -18,7 +18,11 @@ */ #include "qemu/osdep.h" +#include "qemu/main-loop.h" +#include "exec/replay-core.h" +#include "exec/cpu-irq.h" #include "hw/core/cpu.h" +#include "hw/core/sysemu-cpu-ops.h" #include "sysemu/cpus.h" void cpu_reloading_memory_map(void) @@ -48,3 +52,15 @@ void cpu_reloading_memory_map(void) rcu_read_lock(); } } + +/* Called with BQL held */ +bool common_cpu_handle_interrupt(CPUState *cpu, int interrupt_request) +{ + if (interrupt_request & CPU_INTERRUPT_RESET) { + replay_interrupt(); + cpu_reset(cpu); + return true; + } else { + return false; + } +} diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index daa6e24daf..8fa19b7222 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -797,28 +797,17 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, cpu->exception_index = EXCP_HLT; return true; } -#if defined(TARGET_I386) - else if (interrupt_request & CPU_INTERRUPT_INIT) { - X86CPU *x86_cpu = X86_CPU(cpu); - CPUArchState *env = &x86_cpu->env; - replay_interrupt(); - cpu_svm_check_intercept_param(env, SVM_EXIT_INIT, 0, 0); - do_cpu_init(x86_cpu); - cpu->exception_index = EXCP_HALTED; - return true; - } -#else - else if (interrupt_request & CPU_INTERRUPT_RESET) { - replay_interrupt(); - cpu_reset(cpu); + else if (cpu->cc->sysemu_ops->handle_cpu_interrupt && + cpu->cc->sysemu_ops->handle_cpu_interrupt(cpu, interrupt_request)) { + return true; + } else if (common_cpu_handle_interrupt(cpu, interrupt_request)) { return true; - } -#endif /* !TARGET_I386 */ - /* The target hook has 3 exit conditions: - False when the interrupt isn't processed, - True when it is, and we should restart on a new TB, - and via longjmp via cpu_loop_exit. */ - else { + } else { + /* + * The target hook has 3 exit conditions: False when the + * interrupt isn't processed, True when it is, and we should + * restart on a new TB, and via longjmp via cpu_loop_exit. + */ CPUClass *cc = CPU_GET_CLASS(cpu); if (cc->tcg_ops->cpu_exec_interrupt && diff --git a/target/i386/cpu-sysemu.c b/target/i386/cpu-sysemu.c index e545bf7590..5638ed4aa4 100644 --- a/target/i386/cpu-sysemu.c +++ b/target/i386/cpu-sysemu.c @@ -31,6 +31,7 @@ #include "hw/qdev-properties.h" #include "exec/address-spaces.h" +#include "exec/replay-core.h" #include "hw/i386/apic_internal.h" #include "cpu-internal.h" @@ -322,6 +323,22 @@ void x86_cpu_handle_halt(CPUState *cpu) } } +/* Called with BQL held */ +bool x86_cpu_handle_interrupt(CPUState *cpu, int interrupt_request) +{ + if (interrupt_request & CPU_INTERRUPT_INIT) { + X86CPU *x86_cpu = X86_CPU(cpu); + CPUArchState *env = &x86_cpu->env; + replay_interrupt(); + cpu_svm_check_intercept_param(env, SVM_EXIT_INIT, 0, 0); + do_cpu_init(x86_cpu); + cpu->exception_index = EXCP_HALTED; + return true; + } else { + return false; + } +} + GuestPanicInformation *x86_cpu_get_crash_info(CPUState *cs) { X86CPU *cpu = X86_CPU(cs); diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 67027d28b0..1b66583987 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7242,6 +7242,7 @@ static const struct SysemuCPUOps i386_sysemu_ops = { .asidx_from_attrs = x86_asidx_from_attrs, .get_crash_info = x86_cpu_get_crash_info, .handle_cpu_halt = x86_cpu_handle_halt, + .handle_cpu_interrupt = x86_cpu_handle_interrupt, .write_elf32_note = x86_cpu_write_elf32_note, .write_elf64_note = x86_cpu_write_elf64_note, .write_elf32_qemunote = x86_cpu_write_elf32_qemunote, From patchwork Mon Mar 20 10:10:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 665189 Delivered-To: patch@linaro.org Received: by 2002:a5d:5602:0:0:0:0:0 with SMTP id l2csp1037112wrv; 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Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- include/hw/core/tcg-cpu-ops.h | 5 +++++ accel/tcg/cpu-exec.c | 29 +++++++++-------------------- target/i386/tcg/tcg-cpu.c | 1 + 3 files changed, 15 insertions(+), 20 deletions(-) diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index 66c0cecdde..8e8df8c330 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -121,6 +121,11 @@ struct TCGCPUOps { */ bool (*io_recompile_replay_branch)(CPUState *cpu, const TranslationBlock *tb); + /** + * @virtual_interrupts: IRQs that can be ignored for replay purposes + */ + int virtual_interrupts; + #else /** * record_sigsegv: diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 8fa19b7222..56be7956e7 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -737,22 +737,6 @@ static inline bool cpu_handle_exception(CPUState *cpu, int *ret) return false; } -#ifndef CONFIG_USER_ONLY -/* - * CPU_INTERRUPT_POLL is a virtual event which gets converted into a - * "real" interrupt event later. It does not need to be recorded for - * replay purposes. - */ -static inline bool need_replay_interrupt(int interrupt_request) -{ -#if defined(TARGET_I386) - return !(interrupt_request & CPU_INTERRUPT_POLL); -#else - return true; -#endif -} -#endif /* !CONFIG_USER_ONLY */ - static inline bool cpu_handle_interrupt(CPUState *cpu, TranslationBlock **last_tb) { @@ -808,11 +792,16 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, * interrupt isn't processed, True when it is, and we should * restart on a new TB, and via longjmp via cpu_loop_exit. */ - CPUClass *cc = CPU_GET_CLASS(cpu); + struct TCGCPUOps const *tcg_ops = cpu->cc->tcg_ops; - if (cc->tcg_ops->cpu_exec_interrupt && - cc->tcg_ops->cpu_exec_interrupt(cpu, interrupt_request)) { - if (need_replay_interrupt(interrupt_request)) { + if (tcg_ops->cpu_exec_interrupt && + tcg_ops->cpu_exec_interrupt(cpu, interrupt_request)) { + /* + * Virtual events gets converted into a "real" + * interrupt event later. They do not need to be + * recorded for replay purposes. + */ + if (!(interrupt_request & tcg_ops->virtual_interrupts)) { replay_interrupt(); } /* diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index b942c306d6..750ae0f945 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -104,6 +104,7 @@ static const struct TCGCPUOps x86_tcg_ops = { .do_unaligned_access = x86_cpu_do_unaligned_access, .debug_excp_handler = breakpoint_handler, .debug_check_breakpoint = x86_debug_check_breakpoint, + .virtual_interrupts = CPU_INTERRUPT_POLL, #endif /* !CONFIG_USER_ONLY */ }; From patchwork Mon Mar 20 10:10:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 665184 Delivered-To: patch@linaro.org Received: by 2002:a5d:5602:0:0:0:0:0 with SMTP id l2csp1036776wrv; Mon, 20 Mar 2023 03:11:45 -0700 (PDT) X-Google-Smtp-Source: AK7set/w2bzusGAxvGiciS0SdHcV0X8jH1xJy6aH+gjUDJg9EkMnFm1qY4zyg2+1bFtxVEoCb7PF X-Received: by 2002:a05:622a:1315:b0:3da:a657:db78 with SMTP id v21-20020a05622a131500b003daa657db78mr15449274qtk.9.1679307105110; Mon, 20 Mar 2023 03:11:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1679307105; cv=none; d=google.com; s=arc-20160816; b=hs6ajQ9Ptp4bNpeS3tI8u/ZV1pDGpprDgLb2rn97GvLU00+jUoESfU2RgA66Xg9gJA 14DPhu7CatYE4ibtbjdUePv07QySPbYhfFhlf5ryXrYn9u3tMvQ5uPdr9q0PUamSXNsY xPPCWzw+6EMZy+sT0wrrMocCy5puXcNilnFO+LztOkjAR/+FHnywv7GltjlvFoA70M6h 5o0fter1nofK1853gaSjb/wP3LH7jvsxUj96Kh7qLQCSgUDmjpRMi0vlIFww9U9XDonc +bFGmnCabJ9Bsaw8pnGPAk1GYp0LOD0gm4kGeN+L+ovz7kuS4+MB/Qie8qvjIOMV5SAl CeXg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=FnmBMm+SXTgqFEy4wlEqxWB8R7Mqnlhesphm0Wpbwgg=; b=Q+1Wbbp1Owa9L79bgsFF14jfcJsNMh61Q7bf6E7etJSYkar1/xedg38DryDgNTiL2/ WdP/igkKIG0DffljXFjTpd51fZ4sjoUDHYoXH4rYsZQ55D+toe6pNfda4CylHi7DUz1s g6zred23zLoiTGLuB334IbA4MtTV4oWNvDh6F9+NV4ZHAzdUcHUOXPdi4tSD6LPL/J4w YoE4YlVR0aanvtjObXVlT9FvQWzjOClrRT1iyIcAO9nS5yKOtMvjOVaHw2ir3bwrTGqW YBKeDNNMI4L4W/RDHv8MOVjBJDU+ARmdvGeyq4U2tHP/I+2QR5ggo3AB0sFQHm73nNzB 5D1A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=oyBmGFF+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Mon, 20 Mar 2023 03:10:38 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id DD5641FFB8; Mon, 20 Mar 2023 10:10:36 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: Alessandro Di Federico , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , qemu-devel@nongnu.org Cc: Richard Henderson , Paolo Bonzini , Eduardo Habkost , =?utf-8?q?Alex_Benn=C3=A9e?= Subject: [PATCH 10/10] accel/tcg: remove unused includes Date: Mon, 20 Mar 2023 10:10:35 +0000 Message-Id: <20230320101035.2214196-11-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230320101035.2214196-1-alex.bennee@linaro.org> References: <20230320101035.2214196-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson Reviewed-by: Alessandro Di Federico --- accel/tcg/cpu-exec.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 56be7956e7..90e327c3bb 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -19,20 +19,16 @@ #include "qemu/osdep.h" #include "qemu/qemu-print.h" -#include "qapi/error.h" -#include "qapi/type-helpers.h" #include "hw/core/tcg-cpu-ops.h" #include "hw/core/sysemu-cpu-ops.h" #include "trace.h" #include "disas/disas.h" -#include "exec/exec-all.h" #include "tcg/tcg.h" #include "qemu/atomic.h" #include "qemu/rcu.h" #include "exec/log.h" #include "qemu/main-loop.h" #include "sysemu/cpus.h" -#include "exec/cpu-all.h" #include "sysemu/cpu-timers.h" #include "exec/replay-core.h" #include "sysemu/tcg.h"