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This makes it really efficient to perform CMOs by VA as we only need to look at dirty pages. Signed-off-by: Marc Zyngier [ Paul: pick from the Android tree. Rebase to the upstream ] Signed-off-by: Ying-Chun Liu (PaulLiu) Cc: Tom Rini Link: https://android.googlesource.com/platform/external/u-boot/+/3c433724e6f830a6b2edd5ec3d4a504794887263 --- arch/arm/cpu/armv8/cache_v8.c | 16 +++++++++++++++- arch/arm/include/asm/armv8/mmu.h | 14 ++++++++++---- arch/arm/include/asm/global_data.h | 1 + 3 files changed, 26 insertions(+), 5 deletions(-) diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index 697334086f..4760064ee1 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -93,6 +93,8 @@ u64 get_tcr(u64 *pips, u64 *pva_bits) if (el == 1) { tcr = TCR_EL1_RSVD | (ips << 32) | TCR_EPD1_DISABLE; + if (gd->arch.has_hafdbs) + tcr |= TCR_HA | TCR_HD; } else if (el == 2) { tcr = TCR_EL2_RSVD | (ips << 16); } else { @@ -200,6 +202,9 @@ static void __cmo_on_leaves(void (*cmo_fn)(unsigned long, unsigned long), attrs != PTE_BLOCK_MEMTYPE(MT_NORMAL_NC)) continue; + if (gd->arch.has_hafdbs && (pte & (PTE_RDONLY | PTE_DBM)) != PTE_DBM) + continue; + end = va + BIT(level2shift(level)) - 1; /* No intersection with RAM? */ @@ -348,6 +353,9 @@ static void add_map(struct mm_region *map) if (va_bits < 39) level = 1; + if (gd->arch.has_hafdbs) + attrs |= PTE_DBM | PTE_RDONLY; + map_range(map->virt, map->phys, map->size, level, (u64 *)gd->arch.tlb_addr, attrs); } @@ -399,7 +407,13 @@ static int count_ranges(void) __weak u64 get_page_table_size(void) { u64 one_pt = MAX_PTE_ENTRIES * sizeof(u64); - u64 size; + u64 size, mmfr1; + + asm volatile("mrs %0, id_aa64mmfr1_el1" : "=r" (mmfr1)); + if ((mmfr1 & 0xf) == 2) + gd->arch.has_hafdbs = true; + else + gd->arch.has_hafdbs = false; /* Account for all page tables we would need to cover our memory map */ size = one_pt * count_ranges(); diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h index 9f58cedb65..98a27db316 100644 --- a/arch/arm/include/asm/armv8/mmu.h +++ b/arch/arm/include/asm/armv8/mmu.h @@ -49,10 +49,13 @@ #define PTE_TYPE_BLOCK (1 << 0) #define PTE_TYPE_VALID (1 << 0) -#define PTE_TABLE_PXN (1UL << 59) -#define PTE_TABLE_XN (1UL << 60) -#define PTE_TABLE_AP (1UL << 61) -#define PTE_TABLE_NS (1UL << 63) +#define PTE_RDONLY BIT(7) +#define PTE_DBM BIT(51) + +#define PTE_TABLE_PXN BIT(59) +#define PTE_TABLE_XN BIT(60) +#define PTE_TABLE_AP BIT(61) +#define PTE_TABLE_NS BIT(63) /* * Block @@ -99,6 +102,9 @@ #define TCR_TG0_16K (2 << 14) #define TCR_EPD1_DISABLE (1 << 23) +#define TCR_HA BIT(39) +#define TCR_HD BIT(40) + #define TCR_EL1_RSVD (1U << 31) #define TCR_EL2_RSVD (1U << 31 | 1 << 23) #define TCR_EL3_RSVD (1U << 31 | 1 << 23) diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h index 9e746e380a..eda99b5b41 100644 --- a/arch/arm/include/asm/global_data.h +++ b/arch/arm/include/asm/global_data.h @@ -52,6 +52,7 @@ struct arch_global_data { #if defined(CONFIG_ARM64) unsigned long tlb_fillptr; unsigned long tlb_emerg; + bool has_hafdbs; #endif #endif #ifdef CFG_SYS_MEM_RESERVE_SECURE From patchwork Fri Mar 17 16:22:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Liu X-Patchwork-Id: 664557 Delivered-To: patch@linaro.org Received: by 2002:a5d:5602:0:0:0:0:0 with SMTP id l2csp491499wrv; Fri, 17 Mar 2023 09:23:38 -0700 (PDT) X-Google-Smtp-Source: AK7set+Nd5mPAihZev6lz9K/K9pvM+pM53vIRwsTlLvGrk08G9n77LxA4zltcuOVZcNHF6wz9iK4 X-Received: by 2002:a05:6214:cc3:b0:56e:b5a1:b521 with SMTP id 3-20020a0562140cc300b0056eb5a1b521mr47625851qvx.51.1679070217972; Fri, 17 Mar 2023 09:23:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1679070217; cv=none; d=google.com; s=arc-20160816; b=fv3ukcKW3pRhYFmFnC8Ma+gc6ij74uHSxKblRExlZ124J1xN2gGn3pXiOEOzLeEPzV UYztgoXxoJSgodb550GhqUstOVu7tUEYfqZsMLSwz7zntc1Nkt8z3KFc8HFYsvHdT3js em0ooufAbMipuMC/+cszXnRfKZQcIfY6SHXBdO01yB7kLucWw8qNFeg9lEArORzfLJt5 Fq4FXaVoKfNfsaSZdzJuV2OkujriMQDSXQKIEOJ6LDbOmgl4BAgpayqA14X9qQLIa9Gw K+wbTuzSGBFBDe3Tu5W6Yqm+4vA+kt1f1zY+g3fE+iCU8Rp3ezx90VBlKqX46NMoQObl dIKA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=f/yZdXq0tXoVn+UnXN86SQR2lNQJiQzEBQB393JaLjk=; b=T3qxQWCMh4gg8TZSleRPbBAFaNCUS3ZwvkFXTGDzwnM3MidzziGdusisL5x32AgWKC URQ/p1EN6QvX0+kEOQ2dA74inoxmTT7ezZltyP6DESD66ewg1z5xtQ9LYi/VLB26FC8f F+RjJWEfD7nlscPDmh0UD+Nb5r0lL9j3Rlw+gpF/byfvbz8PSVHR8Btxv2MdC5EOgBXc U3gIfxzUH7xYTGzQHj7+Q1KTAKcdAM/CFwsGOD7sBOMl3f4DyrywZTa6QL/fXJl7ST85 HrTOGqLhYDq/1S7kSKeEEnCiQ+J8La6nYm7d7t6xo9/S+xGGzAUcpAD/N8zXgCXqyKh/ MtEQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tLf0a7r5; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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This has no material impact on u-boot's runtime performance, and allows a huge speedup when cleaning the cache. Signed-off-by: Marc Zyngier [ Paul: pick from the Android tree. Rebase to the upstream ] Signed-off-by: Ying-Chun Liu (PaulLiu) Cc: Tom Rini Link: https://android.googlesource.com/platform/external/u-boot/+/417a73581a72ff6d6ee4b0938117b8a23e32f7e8 --- arch/arm/cpu/armv8/cache_v8.c | 14 ++++++++++---- arch/arm/include/asm/global_data.h | 1 + 2 files changed, 11 insertions(+), 4 deletions(-) diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index 4760064ee1..4c6a1b1d6c 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -314,7 +314,7 @@ static void map_range(u64 virt, u64 phys, u64 size, int level, for (i = idx; size; i++) { u64 next_size, *next_table; - if (level >= 1 && + if (level >= gd->arch.first_block_level && size >= map_size && !(virt & (map_size - 1))) { if (level == 3) table[i] = phys | attrs | PTE_TYPE_PAGE; @@ -353,6 +353,9 @@ static void add_map(struct mm_region *map) if (va_bits < 39) level = 1; + if (!gd->arch.first_block_level) + gd->arch.first_block_level = 1; + if (gd->arch.has_hafdbs) attrs |= PTE_DBM | PTE_RDONLY; @@ -369,7 +372,7 @@ static void count_range(u64 virt, u64 size, int level, int *cntp) for (i = idx; size; i++) { u64 next_size; - if (level >= 1 && + if (level >= gd->arch.first_block_level && size >= map_size && !(virt & (map_size - 1))) { virt += map_size; size -= map_size; @@ -410,10 +413,13 @@ __weak u64 get_page_table_size(void) u64 size, mmfr1; asm volatile("mrs %0, id_aa64mmfr1_el1" : "=r" (mmfr1)); - if ((mmfr1 & 0xf) == 2) + if ((mmfr1 & 0xf) == 2) { gd->arch.has_hafdbs = true; - else + gd->arch.first_block_level = 2; + } else { gd->arch.has_hafdbs = false; + gd->arch.first_block_level = 1; + } /* Account for all page tables we would need to cover our memory map */ size = one_pt * count_ranges(); diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h index eda99b5b41..9d94cbe665 100644 --- a/arch/arm/include/asm/global_data.h +++ b/arch/arm/include/asm/global_data.h @@ -52,6 +52,7 @@ struct arch_global_data { #if defined(CONFIG_ARM64) unsigned long tlb_fillptr; unsigned long tlb_emerg; + unsigned int first_block_level; bool has_hafdbs; #endif #endif From patchwork Fri Mar 17 16:22:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Liu X-Patchwork-Id: 664558 Delivered-To: patch@linaro.org Received: by 2002:a5d:5602:0:0:0:0:0 with SMTP id l2csp491608wrv; Fri, 17 Mar 2023 09:23:50 -0700 (PDT) X-Google-Smtp-Source: AK7set9zDOSaMe6l/SOmZD5YdArw9m9ZCiOGRothC2tmC3pjAlasoMkuzgkgLt/5C19Cnlf11FNj X-Received: by 2002:a05:6122:1479:b0:401:bb89:1b0a with SMTP id r25-20020a056122147900b00401bb891b0amr320459vkp.5.1679070230384; Fri, 17 Mar 2023 09:23:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1679070230; cv=none; d=google.com; s=arc-20160816; b=kmLQoES2mT3kpUOTO18Of0foWeMXp/oFiWyLIAumv8502/vYRP8aL1OSnW1zaJTAwK 0LhAWuYW3ZR//m4JRWVsRqW29uRX5JFMyt33rorjfxQZ1UM62ybiZ9E+bRHMrazAbm4O xYKLpsFmK1r1Hq9vEc6DeOxv9et6X5iSC1C/2hNk49YVNA2n3BQIy72l3DPDvFTvjw4k WAtONMvtXkaqZeTgTZpwq/7aWOOm1rbuN2EJELMnTg87qle6ys6MKJ5Fv5vV49MjSfhg x5iOvtb2Cxasdj/ur+AJs8HPd8pPHX15OlgVJtF7fS9oIw5hROdGTvdf+UBBk+Wz59LC vmOg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=p4+MQ0SCCaSYjeoxRqub4df33kCvVYqWnwAZqQEA/OU=; b=kiHc8Z+n+GvP4vwCA4X/BHUBS351nMD0w9WmorcwQGRjK0ZSAflH2rH9Lgvsve1mNR kqYG2eQvsBBDXRuiNiOdSen7XwfH7DbL80kDR+gPOA05qlpfIQJwwmPTklr+mgFY36F0 LwKhuKHCcjbs36b1FVt6T/C5W0dj5YVQ8STP7/UHPywNQHVsagM9RbvzICzDpJhFFefb 8MfqrTNfCUV+PIpLRltoNAzAOgpTJZBiJVEbIlH9ETynYbi0pGtyOCE79g6Jau2i0xq4 PZLKY9zQpBMUBTEHr7UvrhoIQmQlqTVzbgvkRFajyC8xpGYLUPNraDdlYu8jseJnFgB3 fF4Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NuFnyGhF; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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Signed-off-by: meitao [ Paul: pick from the Android tree. Rebase to the upstream ] Signed-off-by: Ying-Chun Liu (PaulLiu) Cc: Tom Rini Link: https://android.googlesource.com/platform/external/u-boot/+/3bf38943aeab4700c2319bff2a1477d99c6afd2f --- arch/arm/cpu/armv8/cache_v8.c | 6 +++++- arch/arm/include/asm/armv8/mmu.h | 10 ++++++++-- 2 files changed, 13 insertions(+), 3 deletions(-) diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index 4c6a1b1d6c..cb1131a048 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -94,11 +94,15 @@ u64 get_tcr(u64 *pips, u64 *pva_bits) if (el == 1) { tcr = TCR_EL1_RSVD | (ips << 32) | TCR_EPD1_DISABLE; if (gd->arch.has_hafdbs) - tcr |= TCR_HA | TCR_HD; + tcr |= TCR_EL1_HA | TCR_EL1_HD; } else if (el == 2) { tcr = TCR_EL2_RSVD | (ips << 16); + if (gd->arch.has_hafdbs) + tcr |= TCR_EL2_HA | TCR_EL2_HD; } else { tcr = TCR_EL3_RSVD | (ips << 16); + if (gd->arch.has_hafdbs) + tcr |= TCR_EL3_HA | TCR_EL3_HD; } /* PTWs cacheable, inner/outer WBWA and inner shareable */ diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h index 98a27db316..19a9e112a4 100644 --- a/arch/arm/include/asm/armv8/mmu.h +++ b/arch/arm/include/asm/armv8/mmu.h @@ -102,8 +102,14 @@ #define TCR_TG0_16K (2 << 14) #define TCR_EPD1_DISABLE (1 << 23) -#define TCR_HA BIT(39) -#define TCR_HD BIT(40) +#define TCR_EL1_HA BIT(39) +#define TCR_EL1_HD BIT(40) + +#define TCR_EL2_HA BIT(21) +#define TCR_EL2_HD BIT(22) + +#define TCR_EL3_HA BIT(21) +#define TCR_EL3_HD BIT(22) #define TCR_EL1_RSVD (1U << 31) #define TCR_EL2_RSVD (1U << 31 | 1 << 23)