From patchwork Wed Mar 15 07:28:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jacky Huang X-Patchwork-Id: 663976 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E2455C7618E for ; Wed, 15 Mar 2023 07:30:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231669AbjCOHa3 (ORCPT ); Wed, 15 Mar 2023 03:30:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38432 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231772AbjCOH36 (ORCPT ); Wed, 15 Mar 2023 03:29:58 -0400 Received: from mail-pj1-x102b.google.com (mail-pj1-x102b.google.com [IPv6:2607:f8b0:4864:20::102b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B39E76C690; Wed, 15 Mar 2023 00:29:11 -0700 (PDT) Received: by mail-pj1-x102b.google.com with SMTP id nn12so17846624pjb.5; Wed, 15 Mar 2023 00:29:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1678865351; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Ed17VsKqIYY1EHY3aBloZZET84zjPJ3dZSJioIcN9l0=; b=jCejio4JOFaEEdujj2UtxzkEnwWmbwdk4jb7/APQfQbPL7rfxOy4DfJrcSAHA4gSuw Ux7tgN+9bErK7Pe2KwoqNcZhxLHx6MG7MS97cnHTuIV5UZO3csvYS1aaPaGzntKQn3jL 40M0KAMMYQNOk1VZkNwUXNy6EF4gTgAQJsfurqyMxrN9SU3YaoTJXO6/TkY4GekXXrVH W0oluaacMemPG4fiEfsDvdv6pCpaKhYuq2OpP9/lN5VhTOWvXFPt7xAby8uu80Wv8Vpl GdWHojEfPr9CBIuy5CuXmZn0+2awb9Mq1meIV8IqrrNtFWDUu5HxmSswFRfmyGPKrQ4I sZ7g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678865351; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Ed17VsKqIYY1EHY3aBloZZET84zjPJ3dZSJioIcN9l0=; b=sdMT2DRDj794tAUfuXRRwWOsyebI0r4zlXI4Ep4Y6Ff+fW2iSErN2eJWXYikopCU6t JkRo8AApNs4yToFAUn2SjZSy/jiUR1os60Fgy8Ot6Ci1ZZ009LRJQs3lkByXa/+YRa9j THiUiIpDUZncn8j/IqP9OCXmv1Uzeza5/4bGcfIMRzDf5sGCxurfSs8lLpAUGR+HRfyu 8YaU0n+GunkqWz0hcsUZhGYqe2gHw9ae7oPIaKGTustycBFd6Q1zqrRRnUG67sUDLjc7 YudLJPZ+wVZ29RR/DnLRSbLxybVEE+Whl/rDDSkuU73qRWAoH3jFSBKoL8JeMMWIqa+X QQrg== X-Gm-Message-State: AO0yUKX9aRQktQPBo9fr8UHSzII29EfWC3urexifMHhW02g7kGo49hpA vw/Qe9dJcmY4wlXc2wH0uvA= X-Google-Smtp-Source: AK7set9KTk8ds9IJJR2XfY2NSP8RNVnPplOwDXkJJflpiW1QbzAegPBDrWjapjJZ8dsePZeKiNH6iQ== X-Received: by 2002:a17:902:d2d1:b0:19a:a520:b203 with SMTP id n17-20020a170902d2d100b0019aa520b203mr1677475plc.25.1678865351189; Wed, 15 Mar 2023 00:29:11 -0700 (PDT) Received: from a28aa0606c51.. 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[60.250.192.107]) by smtp.gmail.com with ESMTPSA id kz11-20020a170902f9cb00b001a0667822c8sm2740003plb.94.2023.03.15.00.29.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Mar 2023 00:29:10 -0700 (PDT) From: Jacky Huang To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, gregkh@linuxfoundation.org, jirislaby@kernel.org Cc: devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, schung@nuvoton.com, Jacky Huang Subject: [PATCH 01/15] arm64: Kconfig.platforms: Add config for Nuvoton MA35 platform Date: Wed, 15 Mar 2023 07:28:48 +0000 Message-Id: <20230315072902.9298-2-ychuang570808@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230315072902.9298-1-ychuang570808@gmail.com> References: <20230315072902.9298-1-ychuang570808@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org From: Jacky Huang Add ARCH_NUVOTON configuration option for Nuvoton MA35 family SoCs. Signed-off-by: Jacky Huang --- arch/arm64/Kconfig.platforms | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 89a0b13b058d..c1f277c05569 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -236,6 +236,15 @@ config ARCH_NPCM General support for NPCM8xx BMC (Arbel). Nuvoton NPCM8xx BMC based on the Cortex A35. +config ARCH_NUVOTON + bool "Nuvoton MA35 Platforms" + select GPIOLIB + select PINCTRL + select RESET_CONTROLLER + help + This enables support for the ARMv8 based Nuvoton SoCs such + as MA35D1. + config ARCH_QCOM bool "Qualcomm Platforms" select GPIOLIB From patchwork Wed Mar 15 07:28:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jacky Huang X-Patchwork-Id: 663975 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CB91BC7618B for ; Wed, 15 Mar 2023 07:30:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231715AbjCOHan (ORCPT ); Wed, 15 Mar 2023 03:30:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39790 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231788AbjCOHaB (ORCPT ); Wed, 15 Mar 2023 03:30:01 -0400 Received: from mail-pl1-x634.google.com (mail-pl1-x634.google.com [IPv6:2607:f8b0:4864:20::634]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3A0BA6C19D; Wed, 15 Mar 2023 00:29:14 -0700 (PDT) Received: by mail-pl1-x634.google.com with SMTP id v21so8986333ple.9; Wed, 15 Mar 2023 00:29:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1678865353; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=skDrdHHxY4/PRNsG0BtA3PR+oADTeYv6w75S5aIGD+k=; b=ncX2cNjBBArloPVBvUzdqBSEYyE6q/RBxhKEBvLcOGoyzywiNysSunaU/OKu8S+zVG WJHnZNjf/npJfFzyniqVTE0/a1I5oVzxyTbHfzPBbihQrPqpmj6BkzoEmfQnFp1DIb4L ECR6fWzulpN+k1wQRBcvsx9Zh9RlS7q0vzi7jE3P5rOStskcjh/b1hSpeMRJUu/aQFi6 Kn+2HGlQglBJzN9Znoi0SI208RUeNBkZ3zTo/e2DH93ow7HirepCuW01sebh/NXx1cVq miTThLyV969evfDME579tdtogEZhgMpAgSD6wyWhfREWjf9YSgCw2GQ+aDk8ndRcST3D lTrw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678865353; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=skDrdHHxY4/PRNsG0BtA3PR+oADTeYv6w75S5aIGD+k=; b=agyfEPVS8wvmjES0I5jjGsUSIv+JPrOKd5xQ9qvKQ5zaL8yLYb0plr3jVlqzfsHJfQ 42BBLbobwH+UOF3z3rHPlP8cPPl7/UOyn3sPZlJ9gVLiWLeq8Xe22zJcsPv28iYOIkA7 IenaGJXnhIYeyLW0M7QwQ+AMXiHlyHvOJy9rPFJlx5sPVCFMYBp08wexV4HhQMVu9cM1 9fNGZlSRz/bJs0rUr4duAGa2fLuIcHlPOjcT1nVY7UvJeuV64TaI79glE9Q2GUD1o4wB OK3QZt4In4rNoGmmfm6CWYayh/VKHl4eoGKsM1nZPtDYCn8No+z/VwnS8zPS6pEYtDuI 8YEw== X-Gm-Message-State: AO0yUKXib2l+8Tp+RSIDXiawp6kioxK+3Uzvv5VeQYxZ+anO/NiSrmmb nDSeBRbrfx9lDf5rOt5BiVg= X-Google-Smtp-Source: AK7set9hHttrvRDC5H+g6AdgKuIgXIrQQYDTQpVx8MLNrRRywrLCA11rZ7KFHpOen4NeVzub6jLetw== X-Received: by 2002:a17:903:2846:b0:19c:e05a:ea6 with SMTP id kq6-20020a170903284600b0019ce05a0ea6mr1270462plb.56.1678865353712; Wed, 15 Mar 2023 00:29:13 -0700 (PDT) Received: from a28aa0606c51.. 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[60.250.192.107]) by smtp.gmail.com with ESMTPSA id kz11-20020a170902f9cb00b001a0667822c8sm2740003plb.94.2023.03.15.00.29.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Mar 2023 00:29:13 -0700 (PDT) From: Jacky Huang To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, gregkh@linuxfoundation.org, jirislaby@kernel.org Cc: devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, schung@nuvoton.com, Jacky Huang Subject: [PATCH 02/15] arm64: defconfig: Add Nuvoton MA35 family support Date: Wed, 15 Mar 2023 07:28:49 +0000 Message-Id: <20230315072902.9298-3-ychuang570808@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230315072902.9298-1-ychuang570808@gmail.com> References: <20230315072902.9298-1-ychuang570808@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org From: Jacky Huang Enable basic drivers for ma35d1 booting up support: architecture, device tree, clock, reset, and uart. Signed-off-by: Jacky Huang --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 7790ee42c68a..c96189acb02c 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -53,6 +53,7 @@ CONFIG_ARCH_LAYERSCAPE=y CONFIG_ARCH_MXC=y CONFIG_ARCH_S32=y CONFIG_ARCH_NPCM=y +CONFIG_ARCH_NUVOTON=y CONFIG_ARCH_QCOM=y CONFIG_ARCH_RENESAS=y CONFIG_ARCH_ROCKCHIP=y From patchwork Wed Mar 15 07:28:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jacky Huang X-Patchwork-Id: 663974 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 267A9C76196 for ; Wed, 15 Mar 2023 07:31:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231732AbjCOHa6 (ORCPT ); Wed, 15 Mar 2023 03:30:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38228 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229720AbjCOHaN (ORCPT ); Wed, 15 Mar 2023 03:30:13 -0400 Received: from mail-pj1-x1035.google.com (mail-pj1-x1035.google.com [IPv6:2607:f8b0:4864:20::1035]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 52E836C8A6; Wed, 15 Mar 2023 00:29:20 -0700 (PDT) Received: by mail-pj1-x1035.google.com with SMTP id y15-20020a17090aa40f00b00237ad8ee3a0so962443pjp.2; Wed, 15 Mar 2023 00:29:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1678865359; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/CCS2m1zwfhk2LpGnKN9zFtTOJStf1pjMwr3+kooI4Q=; b=i8ke9dh7ot3FcVuE4JDjr62PnXVzB1rFhkl5zAXL5j1Btoh7AGc5QfQJYkYjxHjdfN rwevcN+w7hna6YGmaNqA68UguMYRBILBIztPcLussivetje8jYSOFicfvJLDuCC6UL/a o4fz65L3Nj6GjCUgcOlYYGeGSrJXQNDQTqAfncHylHQ0IWwHTMVvjM9UNzYTV12jQw0G CgB6jAbp6F+jtVDHNfmMbGVGxKzwLx6BUR7T7aRkdPHmZyDRYCpEUeS6ATXzyG140Wga egW7d4MPQxFuPoV0aRWUp5QdjtES/jmXubqu2q8BN3XumKJGw/sRLXFwG6Fi3h6UUev6 jfKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678865359; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/CCS2m1zwfhk2LpGnKN9zFtTOJStf1pjMwr3+kooI4Q=; b=bakspIl+Ide68t7oH01v/l4avvRRtqCxfo3zZy5SygAIuahGmCohC9bu1PpETz/e5a +W0zpLNEYM1Uyki1AEPBoE2kps3gmi8IVcao/ykKpLsNeW5sBgJ/wWouL5sRoLn7bFOZ b0D5jvat63U5oaYgmmrC3vhVZtxEBaPIGeZFvW5FM2+OO4JrNlsZNHnQxN+bzgB/kiar 5ur3+Vm1mkC9uCqlkKyFyOirplMidVdZCCiFmpng1v4LF+Cyu0yLiosEWgHVbCMv0Uf8 6XBrFBtQYdy1BEQsXlzzJlPcRlSV7iMU4mPi3tKoYlIO21TMkno3b/+SNTBp532XH6bz 2E+w== X-Gm-Message-State: AO0yUKXtbltZJM2WaPXcq0PyOVqVvICxoRTlV3s9NGCfTH6Bs11jvfjG xV8Jx7v8c4RE2rLLOHeE6Rg= X-Google-Smtp-Source: AK7set/tqDCIbfu/J3LwhrzyLJlcCafSWuorRyokq3BHRo/hpnfoP5PHXZtFkfrMk453U/chmkiwLA== X-Received: by 2002:a17:902:e311:b0:19c:dc31:954e with SMTP id q17-20020a170902e31100b0019cdc31954emr1510316plc.8.1678865358818; Wed, 15 Mar 2023 00:29:18 -0700 (PDT) Received: from a28aa0606c51.. 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[60.250.192.107]) by smtp.gmail.com with ESMTPSA id kz11-20020a170902f9cb00b001a0667822c8sm2740003plb.94.2023.03.15.00.29.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Mar 2023 00:29:18 -0700 (PDT) From: Jacky Huang To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, gregkh@linuxfoundation.org, jirislaby@kernel.org Cc: devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, schung@nuvoton.com, Jacky Huang Subject: [PATCH 04/15] dt-bindings: clock: nuvoton: add binding for ma35d1 clock controller Date: Wed, 15 Mar 2023 07:28:51 +0000 Message-Id: <20230315072902.9298-5-ychuang570808@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230315072902.9298-1-ychuang570808@gmail.com> References: <20230315072902.9298-1-ychuang570808@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org From: Jacky Huang Add the dt-bindings header for Nuvoton ma35d1, that gets shared between the clock controller and clock references in the dts. Signed-off-by: Jacky Huang --- .../dt-bindings/clock/nuvoton,ma35d1-clk.h | 253 ++++++++++++++++++ 1 file changed, 253 insertions(+) create mode 100644 include/dt-bindings/clock/nuvoton,ma35d1-clk.h diff --git a/include/dt-bindings/clock/nuvoton,ma35d1-clk.h b/include/dt-bindings/clock/nuvoton,ma35d1-clk.h new file mode 100644 index 000000000000..6c569fdd6e06 --- /dev/null +++ b/include/dt-bindings/clock/nuvoton,ma35d1-clk.h @@ -0,0 +1,253 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Nuvoton Technologies. + */ + +#ifndef __DT_BINDINGS_CLOCK_NUVOTON_MA35D1_CLK_H +#define __DT_BINDINGS_CLOCK_NUVOTON_MA35D1_CLK_H + +/* external and internal oscillator clocks */ +#define HXT 0 +#define HXT_GATE 1 +#define LXT 2 +#define LXT_GATE 3 +#define HIRC 4 +#define HIRC_GATE 5 +#define LIRC 6 +#define LIRC_GATE 7 +/* PLLs */ +#define CAPLL 8 +#define SYSPLL 9 +#define DDRPLL 10 +#define APLL 11 +#define EPLL 12 +#define VPLL 13 +/* EPLL divider */ +#define EPLL_DIV2 14 +#define EPLL_DIV4 15 +#define EPLL_DIV8 16 +/* CPU clock, system clock, AXI, HCLK and PCLK */ +#define CA35CLK_MUX 17 +#define AXICLK_DIV2 18 +#define AXICLK_DIV4 19 +#define AXICLK_MUX 20 +#define SYSCLK0_MUX 21 +#define SYSCLK1_MUX 22 +#define SYSCLK1_DIV2 23 +#define HCLK0 24 +#define HCLK1 25 +#define HCLK2 26 +#define PCLK0 27 +#define PCLK1 28 +#define PCLK2 29 +#define HCLK3 30 +#define PCLK3 31 +#define PCLK4 32 +/* AXI and AHB peripheral clocks */ +#define USBPHY0 33 +#define USBPHY1 34 +#define DDR0_GATE 35 +#define DDR6_GATE 36 +#define CAN0_MUX 37 +#define CAN0_DIV 38 +#define CAN0_GATE 39 +#define CAN1_MUX 40 +#define CAN1_DIV 41 +#define CAN1_GATE 42 +#define CAN2_MUX 43 +#define CAN2_DIV 44 +#define CAN2_GATE 45 +#define CAN3_MUX 46 +#define CAN3_DIV 47 +#define CAN3_GATE 48 +#define SDH0_MUX 49 +#define SDH0_GATE 50 +#define SDH1_MUX 51 +#define SDH1_GATE 52 +#define NAND_GATE 53 +#define USBD_GATE 54 +#define USBH_GATE 55 +#define HUSBH0_GATE 56 +#define HUSBH1_GATE 57 +#define GFX_MUX 58 +#define GFX_GATE 59 +#define VC8K_GATE 60 +#define DCU_MUX 61 +#define DCU_GATE 62 +#define DCUP_DIV 63 +#define EMAC0_GATE 64 +#define EMAC1_GATE 65 +#define CCAP0_MUX 66 +#define CCAP0_DIV 67 +#define CCAP0_GATE 68 +#define CCAP1_MUX 69 +#define CCAP1_DIV 70 +#define CCAP1_GATE 71 +#define PDMA0_GATE 72 +#define PDMA1_GATE 73 +#define PDMA2_GATE 74 +#define PDMA3_GATE 75 +#define WH0_GATE 76 +#define WH1_GATE 77 +#define HWS_GATE 78 +#define EBI_GATE 79 +#define SRAM0_GATE 80 +#define SRAM1_GATE 81 +#define ROM_GATE 82 +#define TRA_GATE 83 +#define DBG_MUX 84 +#define DBG_GATE 85 +#define CKO_MUX 86 +#define CKO_DIV 87 +#define CKO_GATE 88 +#define GTMR_GATE 89 +#define GPA_GATE 90 +#define GPB_GATE 91 +#define GPC_GATE 92 +#define GPD_GATE 93 +#define GPE_GATE 94 +#define GPF_GATE 95 +#define GPG_GATE 96 +#define GPH_GATE 97 +#define GPI_GATE 98 +#define GPJ_GATE 99 +#define GPK_GATE 100 +#define GPL_GATE 101 +#define GPM_GATE 102 +#define GPN_GATE 103 +/* APB peripheral clocks */ +#define TMR0_MUX 104 +#define TMR0_GATE 105 +#define TMR1_MUX 106 +#define TMR1_GATE 107 +#define TMR2_MUX 108 +#define TMR2_GATE 109 +#define TMR3_MUX 110 +#define TMR3_GATE 111 +#define TMR4_MUX 112 +#define TMR4_GATE 113 +#define TMR5_MUX 114 +#define TMR5_GATE 115 +#define TMR6_MUX 116 +#define TMR6_GATE 117 +#define TMR7_MUX 118 +#define TMR7_GATE 119 +#define TMR8_MUX 120 +#define TMR8_GATE 121 +#define TMR9_MUX 122 +#define TMR9_GATE 123 +#define TMR10_MUX 124 +#define TMR10_GATE 125 +#define TMR11_MUX 126 +#define TMR11_GATE 127 +#define UART0_MUX 128 +#define UART0_DIV 129 +#define UART0_GATE 130 +#define UART1_MUX 131 +#define UART1_DIV 132 +#define UART1_GATE 133 +#define UART2_MUX 134 +#define UART2_DIV 135 +#define UART2_GATE 136 +#define UART3_MUX 137 +#define UART3_DIV 138 +#define UART3_GATE 139 +#define UART4_MUX 140 +#define UART4_DIV 141 +#define UART4_GATE 142 +#define UART5_MUX 143 +#define UART5_DIV 144 +#define UART5_GATE 145 +#define UART6_MUX 146 +#define UART6_DIV 147 +#define UART6_GATE 148 +#define UART7_MUX 149 +#define UART7_DIV 150 +#define UART7_GATE 151 +#define UART8_MUX 152 +#define UART8_DIV 153 +#define UART8_GATE 154 +#define UART9_MUX 155 +#define UART9_DIV 156 +#define UART9_GATE 157 +#define UART10_MUX 158 +#define UART10_DIV 159 +#define UART10_GATE 160 +#define UART11_MUX 161 +#define UART11_DIV 162 +#define UART11_GATE 163 +#define UART12_MUX 164 +#define UART12_DIV 165 +#define UART12_GATE 166 +#define UART13_MUX 167 +#define UART13_DIV 168 +#define UART13_GATE 169 +#define UART14_MUX 170 +#define UART14_DIV 171 +#define UART14_GATE 172 +#define UART15_MUX 173 +#define UART15_DIV 174 +#define UART15_GATE 175 +#define UART16_MUX 176 +#define UART16_DIV 177 +#define UART16_GATE 178 +#define RTC_GATE 179 +#define DDR_GATE 180 +#define KPI_MUX 181 +#define KPI_DIV 182 +#define KPI_GATE 183 +#define I2C0_GATE 184 +#define I2C1_GATE 185 +#define I2C2_GATE 186 +#define I2C3_GATE 187 +#define I2C4_GATE 188 +#define I2C5_GATE 189 +#define QSPI0_MUX 190 +#define QSPI0_GATE 191 +#define QSPI1_MUX 192 +#define QSPI1_GATE 193 +#define SMC0_MUX 194 +#define SMC0_DIV 195 +#define SMC0_GATE 196 +#define SMC1_MUX 197 +#define SMC1_DIV 198 +#define SMC1_GATE 199 +#define WDT0_MUX 200 +#define WDT0_GATE 201 +#define WDT1_MUX 202 +#define WDT1_GATE 203 +#define WDT2_MUX 204 +#define WDT2_GATE 205 +#define WWDT0_MUX 206 +#define WWDT1_MUX 207 +#define WWDT2_MUX 208 +#define EPWM0_GATE 209 +#define EPWM1_GATE 210 +#define EPWM2_GATE 211 +#define I2S0_MUX 212 +#define I2S0_GATE 213 +#define I2S1_MUX 214 +#define I2S1_GATE 215 +#define SSMCC_GATE 216 +#define SSPCC_GATE 217 +#define SPI0_MUX 218 +#define SPI0_GATE 219 +#define SPI1_MUX 220 +#define SPI1_GATE 221 +#define SPI2_MUX 222 +#define SPI2_GATE 223 +#define SPI3_MUX 224 +#define SPI3_GATE 225 +#define ECAP0_GATE 226 +#define ECAP1_GATE 227 +#define ECAP2_GATE 228 +#define QEI0_GATE 229 +#define QEI1_GATE 230 +#define QEI2_GATE 231 +#define ADC_DIV 232 +#define ADC_GATE 233 +#define EADC_DIV 234 +#define EADC_GATE 235 +#define CLK_MAX_IDX 236 + +#endif /* __DT_BINDINGS_CLOCK_NUVOTON_MA35D1_CLK_H */ From patchwork Wed Mar 15 07:28:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jacky Huang X-Patchwork-Id: 663973 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B8CE8C76195 for ; Wed, 15 Mar 2023 07:31:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231628AbjCOHbW (ORCPT ); Wed, 15 Mar 2023 03:31:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38810 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231517AbjCOHaV (ORCPT ); Wed, 15 Mar 2023 03:30:21 -0400 Received: from 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[60.250.192.107]) by smtp.gmail.com with ESMTPSA id kz11-20020a170902f9cb00b001a0667822c8sm2740003plb.94.2023.03.15.00.29.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Mar 2023 00:29:23 -0700 (PDT) From: Jacky Huang To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, gregkh@linuxfoundation.org, jirislaby@kernel.org Cc: devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, schung@nuvoton.com, Jacky Huang Subject: [PATCH 06/15] dt-bindings: mfd: syscon: Add nuvoton,ma35d1-sys compatible Date: Wed, 15 Mar 2023 07:28:53 +0000 Message-Id: <20230315072902.9298-7-ychuang570808@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230315072902.9298-1-ychuang570808@gmail.com> References: <20230315072902.9298-1-ychuang570808@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org From: Jacky Huang Add Nuvoton ma35d1 system registers compatible Signed-off-by: Jacky Huang --- Documentation/devicetree/bindings/mfd/syscon.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml index c828c4f5e4a7..e7a3c6e1e77f 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -57,6 +57,7 @@ properties: - microchip,sparx5-cpu-syscon - mstar,msc313-pmsleep - nuvoton,wpcm450-shm + - nuvoton,ma35d1-sys - rockchip,px30-qos - rockchip,rk3036-qos - rockchip,rk3066-qos From patchwork Wed Mar 15 07:28:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jacky Huang X-Patchwork-Id: 663972 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2F8FBC61DA4 for ; Wed, 15 Mar 2023 07:31:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231771AbjCOHbh (ORCPT ); Wed, 15 Mar 2023 03:31:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39530 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231664AbjCOHa2 (ORCPT ); Wed, 15 Mar 2023 03:30:28 -0400 Received: from mail-pl1-x635.google.com (mail-pl1-x635.google.com [IPv6:2607:f8b0:4864:20::635]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9EBD0222E2; Wed, 15 Mar 2023 00:29:35 -0700 (PDT) Received: by mail-pl1-x635.google.com with SMTP id v21so8986843ple.9; Wed, 15 Mar 2023 00:29:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1678865369; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FPFgK3X39dXISj3hHbLpDm92COtr7gUeJ96GRH4aaGI=; b=dqmoNOyoISBXej1LzyLk9c0SV7voNOz6xI5VYdwXghfpDb+7NY7367qwlzCD8T5DnK pRJAjbGHPsnoPCyUWw5ud/p+X6MT3PNO74Bo+dkX14sywhikAGVeh7KT6TQkY+HfwRaA ODnoQs087B5BDuXRk/0xVHv5zXmZrGlo2yWaacweoc+Ns7jHJ24VshckqbBr1xYrRUcp pqo9/JGuej454709jck82NMtsalxfQ9f1oVVsL6RbAhxY+sWiEpImfLokFqHRB6gx9sH 5cmcFOuZh0Fo4ET9jI7tuIa84REuwnw4IglHhdyKfMVaJIz5pvIuzaJg1Xr31PKovObC ZcFQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678865369; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FPFgK3X39dXISj3hHbLpDm92COtr7gUeJ96GRH4aaGI=; b=LUxy89qZE/FXNwYSFwrZnoNfY4pJc4BY3rf5IXoAAdVLjq73itNkOEbCUoLawu4Rkf MwhR5A/AGRWTiShXDrVaRgu1M/fngcfQ2g5zJAYSGRxuT+AQW4Q0GH1FughsQyqDXhG8 1McUwYplmYnJL1pKMV/vPS1D5nqBLOmcdT/udLW6BzxjNPuvV0XlpROGKPTWskv6X6SS bcH4ibaJ94cXGBH91qmmtgCfvmG+mMI4pEwFPTPDflN5htu8/QoDErrWA2sqMyZDIS7G jIoAaqIHJOLsywiETL+sbwsBv2jkkW8B4cXXFblR+NRClrb5sVE5oR4B2WEBGYz+4lSW f9QA== X-Gm-Message-State: AO0yUKVO9cUyjfVdBVvzg319LJR1ew2M+GTOU/XyWN4L8gP1mklCcRM7 7MISga8Yfbqfgq0pLIvK/3X+kiK/xearaQ== X-Google-Smtp-Source: AK7set/NEiW1gw0LNrWPpFDF68I/JNL/D6y70q7WPUviYQItpE0Io/gzbliw1Zt0QigRdAbwjY7tQg== X-Received: by 2002:a17:903:2310:b0:19a:b588:6fe2 with SMTP id d16-20020a170903231000b0019ab5886fe2mr1453175plh.13.1678865368810; Wed, 15 Mar 2023 00:29:28 -0700 (PDT) Received: from a28aa0606c51.. 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[60.250.192.107]) by smtp.gmail.com with ESMTPSA id kz11-20020a170902f9cb00b001a0667822c8sm2740003plb.94.2023.03.15.00.29.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Mar 2023 00:29:28 -0700 (PDT) From: Jacky Huang To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, gregkh@linuxfoundation.org, jirislaby@kernel.org Cc: devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, schung@nuvoton.com, Jacky Huang Subject: [PATCH 08/15] dt-bindings: clock: Document ma35d1 clock controller bindings Date: Wed, 15 Mar 2023 07:28:55 +0000 Message-Id: <20230315072902.9298-9-ychuang570808@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230315072902.9298-1-ychuang570808@gmail.com> References: <20230315072902.9298-1-ychuang570808@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org From: Jacky Huang Add documentation to describe nuvoton ma35d1 clock driver bindings. Signed-off-by: Jacky Huang --- .../bindings/clock/nuvoton,ma35d1-clk.yaml | 83 +++++++++++++++++++ 1 file changed, 83 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/nuvoton,ma35d1-clk.yaml diff --git a/Documentation/devicetree/bindings/clock/nuvoton,ma35d1-clk.yaml b/Documentation/devicetree/bindings/clock/nuvoton,ma35d1-clk.yaml new file mode 100644 index 000000000000..5c2dea071b38 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/nuvoton,ma35d1-clk.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/nuvoton,ma35d1-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton MA35D1 Clock Controller Module Binding + +maintainers: + - Chi-Fang Li + - Jacky Huang + +description: | + The MA35D1 clock controller generates clocks for the whole chip, + including system clocks and all peripheral clocks. + + See also: + include/dt-bindings/clock/ma35d1-clk.h + +properties: + compatible: + items: + - const: nuvoton,ma35d1-clk + - const: syscon + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + clocks: + maxItems: 1 + + clock-names: + const: clk_hxt + + assigned-clocks: + maxItems: 5 + + assigned-clock-rates: + maxItems: 5 + + nuvoton,pll-mode: + description: + A list of PLL operation mode corresponding to CAPLL, DDRPLL, APLL, + EPLL, and VPLL in sequential. The operation mode value 0 is for + integer mode, 1 is for fractional mode, and 2 is for spread + spectrum mode. + $ref: /schemas/types.yaml#/definitions/uint32-array + maxItems: 5 + items: + minimum: 0 + maximum: 2 + + nuvoton,sys: + description: + Phandle to the system management controller. + $ref: "/schemas/types.yaml#/definitions/phandle-array" + +required: + - compatible + - reg + - "#clock-cells" + - clocks + - clock-names + - nuvoton,sys + +additionalProperties: false + +examples: + - | + #include + + clk: clock-controller@40460200 { + compatible = "nuvoton,ma35d1-clk", "syscon"; + reg = <0x40460200 0x100>; + #clock-cells = <1>; + clocks = <&clk_hxt>; + clock-names = "clk_hxt"; + nuvoton,sys = <&sys>; + }; +... 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[60.250.192.107]) by smtp.gmail.com with ESMTPSA id kz11-20020a170902f9cb00b001a0667822c8sm2740003plb.94.2023.03.15.00.29.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Mar 2023 00:29:33 -0700 (PDT) From: Jacky Huang To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, gregkh@linuxfoundation.org, jirislaby@kernel.org Cc: devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, schung@nuvoton.com, Jacky Huang Subject: [PATCH 10/15] dt-bindings: serial: Document ma35d1 uart controller bindings Date: Wed, 15 Mar 2023 07:28:57 +0000 Message-Id: <20230315072902.9298-11-ychuang570808@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230315072902.9298-1-ychuang570808@gmail.com> References: <20230315072902.9298-1-ychuang570808@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org From: Jacky Huang Add documentation to describe nuvoton ma35d1 uart driver bindings. Signed-off-by: Jacky Huang --- .../serial/nuvoton,ma35d1-serial.yaml | 52 +++++++++++++++++++ 1 file changed, 52 insertions(+) create mode 100644 Documentation/devicetree/bindings/serial/nuvoton,ma35d1-serial.yaml diff --git a/Documentation/devicetree/bindings/serial/nuvoton,ma35d1-serial.yaml b/Documentation/devicetree/bindings/serial/nuvoton,ma35d1-serial.yaml new file mode 100644 index 000000000000..9daa2efd4734 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/nuvoton,ma35d1-serial.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/nuvoton,ma35d1-serial.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton MA35D1 Universal Asynchronous Receiver/Transmitter (UART) + +maintainers: + - Min-Jen Chen + - Jacky Huang + +allOf: + - $ref: "serial.yaml" + +properties: + compatible: + const: nuvoton,ma35d1-uart + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + +unevaluatedProperties: false + +examples: + - | + #include + #include + + aliases { + serial0 = &uart0; + }; + + uart0:serial@40700000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x40700000 0x100>; + interrupts = ; + clocks = <&clk UART0_GATE>; + }; +... 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[60.250.192.107]) by smtp.gmail.com with ESMTPSA id kz11-20020a170902f9cb00b001a0667822c8sm2740003plb.94.2023.03.15.00.29.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Mar 2023 00:29:41 -0700 (PDT) From: Jacky Huang To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, gregkh@linuxfoundation.org, jirislaby@kernel.org Cc: devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, schung@nuvoton.com, Jacky Huang Subject: [PATCH 13/15] reset: Add Nuvoton ma35d1 reset driver support Date: Wed, 15 Mar 2023 07:29:00 +0000 Message-Id: <20230315072902.9298-14-ychuang570808@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230315072902.9298-1-ychuang570808@gmail.com> References: <20230315072902.9298-1-ychuang570808@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org From: Jacky Huang This driver supports individual IP reset for ma35d1. The reset control registers is a subset of system control registers. Signed-off-by: Jacky Huang --- drivers/reset/Kconfig | 6 ++ drivers/reset/Makefile | 1 + drivers/reset/reset-ma35d1.c | 152 +++++++++++++++++++++++++++++++++++ 3 files changed, 159 insertions(+) create mode 100644 drivers/reset/reset-ma35d1.c diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 2a52c990d4fe..47671060d259 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -143,6 +143,12 @@ config RESET_NPCM This enables the reset controller driver for Nuvoton NPCM BMC SoCs. +config RESET_NUVOTON_MA35D1 + bool "Nuvton MA35D1 Reset Driver" + default ARCH_NUVOTON + help + This enables the reset controller driver for Nuvoton MA35D1 SoC. + config RESET_OXNAS bool diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 3e7e5fd633a8..fd52dcf66a99 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -20,6 +20,7 @@ obj-$(CONFIG_RESET_MCHP_SPARX5) += reset-microchip-sparx5.o obj-$(CONFIG_RESET_MESON) += reset-meson.o obj-$(CONFIG_RESET_MESON_AUDIO_ARB) += reset-meson-audio-arb.o obj-$(CONFIG_RESET_NPCM) += reset-npcm.o +obj-$(CONFIG_RESET_NUVOTON_MA35D1) += reset-ma35d1.o obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o obj-$(CONFIG_RESET_POLARFIRE_SOC) += reset-mpfs.o diff --git a/drivers/reset/reset-ma35d1.c b/drivers/reset/reset-ma35d1.c new file mode 100644 index 000000000000..bdd39483ca4e --- /dev/null +++ b/drivers/reset/reset-ma35d1.c @@ -0,0 +1,152 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023 Nuvoton Technology Corp. + * Author: Chi-Fang Li + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define RST_PRE_REG 32 + +struct ma35d1_reset_data { + struct reset_controller_dev rcdev; + struct regmap *regmap; +}; + +struct ma35d1_reboot_data { + struct notifier_block restart_handler; + struct regmap *regmap; +}; + +static int ma35d1_restart_handler(struct notifier_block *this, + unsigned long mode, void *cmd) +{ + struct ma35d1_reboot_data *data = + container_of(this, struct ma35d1_reboot_data, + restart_handler); + regmap_write(data->regmap, REG_SYS_IPRST0, 1 << MA35D1_RESET_CHIP); + return -EAGAIN; +} + +static int ma35d1_reset_update(struct reset_controller_dev *rcdev, + unsigned long id, bool assert) +{ + int reg; + int offset = (id / RST_PRE_REG) * 4; + struct ma35d1_reset_data *data = + container_of(rcdev, struct ma35d1_reset_data, rcdev); + + regmap_read(data->regmap, REG_SYS_IPRST0 + offset, ®); + if (assert) + reg |= 1 << (id % RST_PRE_REG); + else + reg &= ~(1 << (id % RST_PRE_REG)); + + regmap_write(data->regmap, REG_SYS_IPRST0 + offset, reg); + return 0; +} + +static int ma35d1_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return ma35d1_reset_update(rcdev, id, true); +} + +static int ma35d1_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return ma35d1_reset_update(rcdev, id, false); +} + +static int ma35d1_reset_status(struct reset_controller_dev *rcdev, + unsigned long id) +{ + int reg; + int offset = id / RST_PRE_REG; + struct ma35d1_reset_data *data = + container_of(rcdev, struct ma35d1_reset_data, rcdev); + + regmap_read(data->regmap, REG_SYS_IPRST0 + offset, ®); + return !!(reg & BIT(id % RST_PRE_REG)); +} + +static const struct reset_control_ops ma35d1_reset_ops = { + .assert = ma35d1_reset_assert, + .deassert = ma35d1_reset_deassert, + .status = ma35d1_reset_status, +}; + +static const struct of_device_id ma35d1_reset_dt_ids[] = { + { .compatible = "nuvoton,ma35d1-reset" }, + { }, +}; + +static int ma35d1_reset_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct ma35d1_reset_data *reset_data; + struct ma35d1_reboot_data *reboot_data; + int err; + + if (!pdev->dev.of_node) { + dev_err(&pdev->dev, "Device tree node not found\n"); + return -EINVAL; + } + + reset_data = devm_kzalloc(dev, sizeof(*reset_data), GFP_KERNEL); + if (!reset_data) + return -ENOMEM; + + reboot_data = devm_kzalloc(dev, sizeof(*reboot_data), GFP_KERNEL); + if (!reboot_data) { + devm_kfree(dev, reset_data); + return -ENOMEM; + } + + reset_data->regmap = syscon_regmap_lookup_by_phandle( + pdev->dev.of_node, "regmap"); + if (IS_ERR(reset_data->regmap)) { + dev_err(&pdev->dev, "Failed to get SYS register base\n"); + err = PTR_ERR(reset_data->regmap); + goto err_out; + } + reset_data->rcdev.owner = THIS_MODULE; + reset_data->rcdev.nr_resets = MA35D1_RESET_COUNT; + reset_data->rcdev.ops = &ma35d1_reset_ops; + reset_data->rcdev.of_node = dev->of_node; + + reboot_data->regmap = reset_data->regmap; + reboot_data->restart_handler.notifier_call = ma35d1_restart_handler; + reboot_data->restart_handler.priority = 192; + + err = register_restart_handler(&reboot_data->restart_handler); + if (err) + dev_warn(&pdev->dev, "failed to register restart handler\n"); + + return devm_reset_controller_register(dev, &reset_data->rcdev); + +err_out: + devm_kfree(dev, reset_data); + devm_kfree(dev, reboot_data); + return err; +} + +static struct platform_driver ma35d1_reset_driver = { + .probe = ma35d1_reset_probe, + .driver = { + .name = "ma35d1-reset", + .of_match_table = ma35d1_reset_dt_ids, + }, +}; + +builtin_platform_driver(ma35d1_reset_driver); From patchwork Wed Mar 15 07:29:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jacky Huang X-Patchwork-Id: 663969 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B5421C61DA4 for ; Wed, 15 Mar 2023 07:32:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231730AbjCOHcm (ORCPT ); Wed, 15 Mar 2023 03:32:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38814 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230018AbjCOHa7 (ORCPT ); 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[60.250.192.107]) by smtp.gmail.com with ESMTPSA id kz11-20020a170902f9cb00b001a0667822c8sm2740003plb.94.2023.03.15.00.29.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Mar 2023 00:29:43 -0700 (PDT) From: Jacky Huang To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, gregkh@linuxfoundation.org, jirislaby@kernel.org Cc: devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, schung@nuvoton.com, Jacky Huang Subject: [PATCH 14/15] tty: serial: Add Nuvoton ma35d1 serial driver support Date: Wed, 15 Mar 2023 07:29:01 +0000 Message-Id: <20230315072902.9298-15-ychuang570808@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230315072902.9298-1-ychuang570808@gmail.com> References: <20230315072902.9298-1-ychuang570808@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org From: Jacky Huang This adds UART and console driver for Nuvoton ma35d1 Soc. MA35D1 SoC provides up to 17 UART controllers, each with one uart port. The ma35d1 uart controller is not compatible with 8250. The uart controller supports: - Full-duplex asynchronous communications - Separates tx and tx 32/32 bytes entry FIFO for data payloads - Hardware auto-flow control - Programmable rx buffer trigger level (1/4/8/14/30 bytes) - Individual programmable baud rate generator for each channel - Supports nCTS, incoming data, rx FIFO reached threshold and RS-485 Address Match (AAD mode) wake-up function - Supports 8-bit rx buffer time-out detection function - Programmable tx data delay time - Supports Auto-Baud Rate measurement and baud rate compensation - Supports break error, frame error, parity error and rx/tx buffer overflow detection function – Programmable number of data bit, 5-, 6-, 7-, 8- bit character – Programmable parity bit, even, odd, no parity or stick parity bit generation and detection – Programmable stop bit, 1, 1.5, or 2 stop bit generation - Supports IrDA SIR function mode - Supports RS-485 function mode – Supports RS-485 9-bit mode – Supports hardware or software enables to program nRTS pin to control RS-485 transmission direction - Supports PDMA transfer function - Support Single-wire function mode. Signed-off-by: Jacky Huang --- drivers/tty/serial/Kconfig | 18 + drivers/tty/serial/Makefile | 1 + drivers/tty/serial/ma35d1_serial.c | 842 +++++++++++++++++++++++++++++ drivers/tty/serial/ma35d1_serial.h | 93 ++++ include/uapi/linux/serial_core.h | 3 + 5 files changed, 957 insertions(+) create mode 100644 drivers/tty/serial/ma35d1_serial.c create mode 100644 drivers/tty/serial/ma35d1_serial.h diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig index 625358f44419..cb47fe804595 100644 --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig @@ -1562,6 +1562,24 @@ config SERIAL_SUNPLUS_CONSOLE you can alter that using a kernel command line option such as "console=ttySUPx". +config SERIAL_NUVOTON_MA35D1 + tristate "Nuvoton MA35D1 family UART support" + depends on ARCH_NUVOTON || COMPILE_TEST + select SERIAL_CORE + help + This driver supports Nuvoton MA35D1 family UART ports. If you would + like to use them, you must answer Y or M to this option. Note that + for use as console, it must be included in kernel and not as a + module + +config SERIAL_NUVOTON_MA35D1_CONSOLE + bool "Console on a Nuvotn MA35D1 family UART port" + depends on SERIAL_NUVOTON_MA35D1=y + select SERIAL_CORE_CONSOLE + help + Select this options if you'd like to use the UART port0 of the + Nuvoton MA35D1 family as a console. + endmenu config SERIAL_MCTRL_GPIO diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile index cd9afd9e3018..71ebeba06ff2 100644 --- a/drivers/tty/serial/Makefile +++ b/drivers/tty/serial/Makefile @@ -93,3 +93,4 @@ obj-$(CONFIG_SERIAL_MCTRL_GPIO) += serial_mctrl_gpio.o obj-$(CONFIG_SERIAL_KGDB_NMI) += kgdb_nmi.o obj-$(CONFIG_KGDB_SERIAL_CONSOLE) += kgdboc.o +obj-$(CONFIG_SERIAL_NUVOTON_MA35D1) += ma35d1_serial.o diff --git a/drivers/tty/serial/ma35d1_serial.c b/drivers/tty/serial/ma35d1_serial.c new file mode 100644 index 000000000000..8940d07c3777 --- /dev/null +++ b/drivers/tty/serial/ma35d1_serial.c @@ -0,0 +1,842 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * MA35D1 serial driver + * Copyright (C) 2023 Nuvoton Technology Corp. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "ma35d1_serial.h" + +#define UART_NR 17 + +static struct uart_driver ma35d1serial_reg; +struct clk *clk; + +struct uart_ma35d1_port { + struct uart_port port; + u16 capabilities; /* port capabilities */ + u8 ier; + u8 lcr; + u8 mcr; + u8 mcr_mask; /* mask of user bits */ + u8 mcr_force; /* mask of forced bits */ + struct serial_rs485 rs485; /* rs485 settings */ + u32 baud_rate; + int rx_count; + u32 console_baud_rate; + u32 console_line; + u32 console_int; +}; + +static struct device_node *ma35d1serial_uart_nodes[UART_NR]; +static struct uart_ma35d1_port ma35d1serial_ports[UART_NR] = { 0 }; +static void __stop_tx(struct uart_ma35d1_port *p); +static void transmit_chars(struct uart_ma35d1_port *up); + +static struct uart_ma35d1_port *to_ma35d1_uart_port(struct uart_port *uart) +{ + return container_of(uart, struct uart_ma35d1_port, port); +} + +static u32 serial_in(struct uart_ma35d1_port *p, int offset) +{ + return __raw_readl(p->port.membase + offset); +} + +static void serial_out(struct uart_ma35d1_port *p, int offset, int value) +{ + __raw_writel(value, p->port.membase + offset); +} + +static void __stop_tx(struct uart_ma35d1_port *p) +{ + u32 ier; + + ier = serial_in(p, UART_REG_IER); + if (ier & THRE_IEN) + serial_out(p, UART_REG_IER, ier & ~THRE_IEN); +} + +static void ma35d1serial_stop_tx(struct uart_port *port) +{ + struct uart_ma35d1_port *up = (struct uart_ma35d1_port *)port; + + __stop_tx(up); +} + +static void ma35d1serial_start_tx(struct uart_port *port) +{ + struct uart_ma35d1_port *up = (struct uart_ma35d1_port *)port; + u32 ier; + struct circ_buf *xmit = &up->port.state->xmit; + + ier = serial_in(up, UART_REG_IER); + serial_out(up, UART_REG_IER, ier & ~THRE_IEN); + if (uart_circ_chars_pending(xmit) < + (16 - ((serial_in(up, UART_REG_FSR) >> 16) & 0x3F))) + transmit_chars(up); + serial_out(up, UART_REG_IER, ier | THRE_IEN); +} + +static void ma35d1serial_stop_rx(struct uart_port *port) +{ + struct uart_ma35d1_port *up = (struct uart_ma35d1_port *)port; + + serial_out(up, UART_REG_IER, serial_in(up, UART_REG_IER) & ~RDA_IEN); +} + +static void +receive_chars(struct uart_ma35d1_port *up) +{ + u8 ch; + u32 fsr; + u32 isr; + u32 dcnt; + char flag; + + isr = serial_in(up, UART_REG_ISR); + fsr = serial_in(up, UART_REG_FSR); + + while (!(fsr & RX_EMPTY)) { + flag = TTY_NORMAL; + up->port.icount.rx++; + + if (unlikely(fsr & (BIF | FEF | PEF | RX_OVER_IF))) { + if (fsr & BIF) { + serial_out(up, UART_REG_FSR, BIF); + up->port.icount.brk++; + if (uart_handle_break(&up->port)) + continue; + } + if (fsr & FEF) { + serial_out(up, UART_REG_FSR, FEF); + up->port.icount.frame++; + } + if (fsr & PEF) { + serial_out(up, UART_REG_FSR, PEF); + up->port.icount.parity++; + } + if (fsr & RX_OVER_IF) { + serial_out(up, UART_REG_FSR, RX_OVER_IF); + up->port.icount.overrun++; + } + if (fsr & BIF) + flag = TTY_BREAK; + if (fsr & PEF) + flag = TTY_PARITY; + if (fsr & FEF) + flag = TTY_FRAME; + } + ch = (u8)serial_in(up, UART_REG_RBR); + if (uart_handle_sysrq_char(&up->port, ch)) + continue; + + uart_insert_char(&up->port, fsr, RX_OVER_IF, ch, flag); + up->rx_count++; + dcnt = (serial_in(up, UART_REG_FSR) >> 8) & 0x3f; + if (up->rx_count > 1023) { + spin_lock(&up->port.lock); + tty_flip_buffer_push(&up->port.state->port); + spin_unlock(&up->port.lock); + up->rx_count = 0; + if ((isr & RXTO_IF) && (dcnt == 0)) + goto tout_end; + } + if (isr & RDA_IF) { + if (dcnt == 1) + return; + } + fsr = serial_in(up, UART_REG_FSR); + } + spin_lock(&up->port.lock); + tty_flip_buffer_push(&up->port.state->port); + spin_unlock(&up->port.lock); +tout_end: + up->rx_count = 0; +} + +static void transmit_chars(struct uart_ma35d1_port *up) +{ + struct circ_buf *xmit = &up->port.state->xmit; + int count = 16 - ((serial_in(up, UART_REG_FSR) >> 16) & 0xF); + + if (serial_in(up, UART_REG_FSR) & TX_FULL) + count = 0; + if (up->port.x_char) { + serial_out(up, UART_REG_THR, up->port.x_char); + up->port.icount.tx++; + up->port.x_char = 0; + return; + } + if (uart_tx_stopped(&up->port)) { + ma35d1serial_stop_tx(&up->port); + return; + } + if (uart_circ_empty(xmit)) { + __stop_tx(up); + return; + } + while (count > 0) { + serial_out(up, UART_REG_THR, xmit->buf[xmit->tail]); + xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); + up->port.icount.tx++; + count--; + if (uart_circ_empty(xmit)) + break; + } + if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) + uart_write_wakeup(&up->port); + if (uart_circ_empty(xmit)) + __stop_tx(up); +} + +static irqreturn_t ma35d1serial_interrupt(int irq, void *dev_id) +{ + struct uart_ma35d1_port *up = (struct uart_ma35d1_port *)dev_id; + u32 isr, fsr; + + isr = serial_in(up, UART_REG_ISR); + fsr = serial_in(up, UART_REG_FSR); + if (isr & (RDA_IF | RXTO_IF)) + receive_chars(up); + if (isr & THRE_INT) + transmit_chars(up); + if (fsr & (BIF | FEF | PEF | RX_OVER_IF | TX_OVER_IF)) + serial_out(up, UART_REG_FSR, + (BIF | FEF | PEF | RX_OVER_IF | TX_OVER_IF)); + + return IRQ_HANDLED; +} + +static u32 ma35d1serial_tx_empty(struct uart_port *port) +{ + struct uart_ma35d1_port *up = (struct uart_ma35d1_port *)port; + u32 fsr; + + fsr = serial_in(up, UART_REG_FSR); + return (fsr & (TE_FLAG | TX_EMPTY)) == (TE_FLAG | TX_EMPTY) ? + TIOCSER_TEMT : 0; +} + +static u32 ma35d1serial_get_mctrl(struct uart_port *port) +{ + struct uart_ma35d1_port *up = (struct uart_ma35d1_port *)port; + u32 status; + u32 ret = 0; + + status = serial_in(up, UART_REG_MSR); + if (!(status & 0x10)) + ret |= TIOCM_CTS; + return ret; +} + +static void ma35d1serial_set_mctrl(struct uart_port *port, u32 mctrl) +{ + struct uart_ma35d1_port *up = (struct uart_ma35d1_port *)port; + u32 mcr = 0; + u32 ier = 0; + + if (mctrl & TIOCM_RTS) { + /* set RTS high level trigger */ + mcr = serial_in(up, UART_REG_MCR); + mcr |= 0x200; + mcr &= ~(0x2); + } + if (up->mcr & UART_MCR_AFE) { + /* set RTS high level trigger */ + mcr = serial_in(up, UART_REG_MCR); + mcr |= 0x200; + mcr &= ~(0x2); + + /* enable CTS/RTS auto-flow control */ + serial_out(up, UART_REG_IER, + (serial_in(up, UART_REG_IER) | (0x3000))); + + /* Set hardware flow control */ + up->port.flags |= UPF_HARD_FLOW; + } else { + /* disable CTS/RTS auto-flow control */ + ier = serial_in(up, UART_REG_IER); + ier &= ~(0x3000); + serial_out(up, UART_REG_IER, ier); + + /* un-set hardware flow control */ + up->port.flags &= ~UPF_HARD_FLOW; + } + + /* set CTS high level trigger */ + serial_out(up, UART_REG_MSR, (serial_in(up, UART_REG_MSR) | (0x100))); + serial_out(up, UART_REG_MCR, mcr); +} + +static void ma35d1serial_break_ctl(struct uart_port *port, int break_state) +{ + struct uart_ma35d1_port *up = (struct uart_ma35d1_port *)port; + unsigned long flags; + u32 lcr; + + spin_lock_irqsave(&up->port.lock, flags); + lcr = serial_in(up, UART_REG_LCR); + if (break_state != 0) + lcr |= BCB; /* set break */ + else + lcr &= ~BCB; /* clr break */ + serial_out(up, UART_REG_LCR, lcr); + spin_unlock_irqrestore(&up->port.lock, flags); +} + +static int ma35d1serial_startup(struct uart_port *port) +{ + struct uart_ma35d1_port *up = (struct uart_ma35d1_port *)port; + struct tty_struct *tty = port->state->port.tty; + int retval; + + /* Reset FIFO */ + serial_out(up, UART_REG_FCR, TFR | RFR /* | RX_DIS */); + + /* Clear pending interrupts */ + serial_out(up, UART_REG_ISR, 0xFFFFFFFF); + + retval = request_irq(port->irq, ma35d1serial_interrupt, 0, + tty ? tty->name : "ma35d1_serial", port); + if (retval) { + dev_err(up->port.dev, "request irq failed.\n"); + return retval; + } + + /* Now, initialize the UART */ + /* FIFO trigger level 4 byte */ + /* RTS trigger level 8 bytes */ + serial_out(up, UART_REG_FCR, + serial_in(up, UART_REG_FCR) | 0x10 | 0x20000); + serial_out(up, UART_REG_LCR, 0x7); /* 8 bit */ + serial_out(up, UART_REG_TOR, 0x40); + serial_out(up, UART_REG_IER, + RTO_IEN | RDA_IEN | TIME_OUT_EN | BUFERR_IEN); + return 0; +} + +static void ma35d1serial_shutdown(struct uart_port *port) +{ + struct uart_ma35d1_port *up = (struct uart_ma35d1_port *)port; + + free_irq(port->irq, port); + + /* Disable interrupts from this port */ + serial_out(up, UART_REG_IER, 0); +} + +static u32 ma35d1serial_get_divisor(struct uart_port *port, u32 baud) +{ + u32 quot; + + quot = (port->uartclk / baud) - 2; + return quot; +} + +static void ma35d1serial_set_termios(struct uart_port *port, + struct ktermios *termios, + const struct ktermios *old) +{ + struct uart_ma35d1_port *up = (struct uart_ma35d1_port *)port; + u32 lcr = 0; + unsigned long flags; + u32 baud, quot; + + switch (termios->c_cflag & CSIZE) { + case CS5: + lcr = 0; + break; + case CS6: + lcr |= 1; + break; + case CS7: + lcr |= 2; + break; + case CS8: + default: + lcr |= 3; + break; + } + + if (termios->c_cflag & CSTOPB) + lcr |= NSB; + if (termios->c_cflag & PARENB) + lcr |= PBE; + if (!(termios->c_cflag & PARODD)) + lcr |= EPE; + if (termios->c_cflag & CMSPAR) + lcr |= SPE; + + baud = uart_get_baud_rate(port, termios, old, port->uartclk / 0xffff, + port->uartclk / 11); + + quot = ma35d1serial_get_divisor(port, baud); + + /* + * Ok, we're now changing the port state. Do it with + * interrupts disabled. + */ + spin_lock_irqsave(&up->port.lock, flags); + + up->port.read_status_mask = RX_OVER_IF; + if (termios->c_iflag & INPCK) + up->port.read_status_mask |= FEF | PEF; + if (termios->c_iflag & (BRKINT | PARMRK)) + up->port.read_status_mask |= BIF; + + /* + * Characteres to ignore + */ + up->port.ignore_status_mask = 0; + if (termios->c_iflag & IGNPAR) + up->port.ignore_status_mask |= FEF | PEF; + if (termios->c_iflag & IGNBRK) { + up->port.ignore_status_mask |= BIF; + /* + * If we're ignoring parity and break indicators, + * ignore overruns too (for real raw support). + */ + if (termios->c_iflag & IGNPAR) + up->port.ignore_status_mask |= RX_OVER_IF; + } + if (termios->c_cflag & CRTSCTS) + up->mcr |= UART_MCR_AFE; + else + up->mcr &= ~UART_MCR_AFE; + + ma35d1serial_set_mctrl(&up->port, up->port.mctrl); + serial_out(up, UART_REG_BAUD, quot | 0x30000000); + serial_out(up, UART_REG_LCR, lcr); + spin_unlock_irqrestore(&up->port.lock, flags); +} + +static void ma35d1serial_release_port(struct uart_port *port) +{ + iounmap(port->membase); + port->membase = NULL; +} + +static int ma35d1serial_request_port(struct uart_port *port) +{ + return 0; +} + +static void ma35d1serial_config_port(struct uart_port *port, int flags) +{ + int ret; + + /* + * Find the region that we can probe for. This in turn + * tells us whether we can probe for the type of port. + */ + ret = ma35d1serial_request_port(port); + if (ret < 0) + return; + port->type = PORT_MA35D1; +} + +static int ma35d1serial_verify_port(struct uart_port *port, + struct serial_struct *ser) +{ + if (ser->type != PORT_UNKNOWN && ser->type != PORT_MA35D1) + return -EINVAL; + return 0; +} + +static const char *ma35d1serial_type(struct uart_port *port) +{ + return (port->type == PORT_MA35D1) ? "MA35D1" : NULL; +} + +/* Enable or disable the rs485 support */ +static int ma35d1serial_config_rs485(struct uart_port *port, + struct ktermios *termios, + struct serial_rs485 *rs485conf) +{ + struct uart_ma35d1_port *p = to_ma35d1_uart_port(port); + + p->rs485 = *rs485conf; + + if (p->rs485.delay_rts_before_send >= 1000) + p->rs485.delay_rts_before_send = 1000; + + serial_out(p, UART_FUN_SEL, + (serial_in(p, UART_FUN_SEL) & ~FUN_SEL_MASK)); + + if (rs485conf->flags & SER_RS485_ENABLED) { + serial_out(p, UART_FUN_SEL, + (serial_in(p, UART_FUN_SEL) | FUN_SEL_RS485)); + + if (rs485conf->flags & SER_RS485_RTS_ON_SEND) + serial_out(p, UART_REG_MCR, + (serial_in(p, UART_REG_MCR) & ~0x200)); + else + serial_out(p, UART_REG_MCR, + (serial_in(p, UART_REG_MCR) | 0x200)); + + /* set auto direction mode */ + serial_out(p, UART_REG_ALT_CSR, + (serial_in(p, UART_REG_ALT_CSR) | (1 << 10))); + } + return 0; +} + +static int ma35d1serial_ioctl(struct uart_port *port, u32 cmd, unsigned long arg) +{ + switch (cmd) { + default: + return -ENOIOCTLCMD; + } + return 0; +} + +static const struct uart_ops ma35d1serial_ops = { + .tx_empty = ma35d1serial_tx_empty, + .set_mctrl = ma35d1serial_set_mctrl, + .get_mctrl = ma35d1serial_get_mctrl, + .stop_tx = ma35d1serial_stop_tx, + .start_tx = ma35d1serial_start_tx, + .stop_rx = ma35d1serial_stop_rx, + .break_ctl = ma35d1serial_break_ctl, + .startup = ma35d1serial_startup, + .shutdown = ma35d1serial_shutdown, + .set_termios = ma35d1serial_set_termios, + .type = ma35d1serial_type, + .release_port = ma35d1serial_release_port, + .request_port = ma35d1serial_request_port, + .config_port = ma35d1serial_config_port, + .verify_port = ma35d1serial_verify_port, + .ioctl = ma35d1serial_ioctl, +}; + +static const struct of_device_id ma35d1_serial_of_match[] = { + { .compatible = "nuvoton,ma35d1-uart" }, + {}, +}; +MODULE_DEVICE_TABLE(of, ma35d1_serial_of_match); + +#ifdef CONFIG_SERIAL_NUVOTON_MA35D1_CONSOLE + +static void ma35d1serial_console_putchar(struct uart_port *port, + unsigned char ch) +{ + struct uart_ma35d1_port *up = (struct uart_ma35d1_port *)port; + + do { + } while ((serial_in(up, UART_REG_FSR) & TX_FULL)); + serial_out(up, UART_REG_THR, ch); +} + +/* + * Print a string to the serial port trying not to disturb + * any possible real use of the port... + * + * The console_lock must be held when we get here. + */ +static void ma35d1serial_console_write(struct console *co, + const char *s, u32 count) +{ + struct uart_ma35d1_port *up = &ma35d1serial_ports[co->index]; + unsigned long flags; + u32 ier; + + local_irq_save(flags); + + /* + * First save the IER then disable the interrupts + */ + ier = serial_in(up, UART_REG_IER); + serial_out(up, UART_REG_IER, 0); + + uart_console_write(&up->port, s, count, ma35d1serial_console_putchar); + + /* + * Finally, wait for transmitter to become empty + * and restore the IER + */ + do { + } while (!(serial_in(up, UART_REG_FSR) & TX_EMPTY)); + serial_out(up, UART_REG_IER, ier); + local_irq_restore(flags); +} + +static int __init ma35d1serial_console_setup(struct console *co, + char *options) +{ + struct device_node *np = ma35d1serial_uart_nodes[co->index]; + struct uart_ma35d1_port *p = &ma35d1serial_ports[co->index]; + u32 val32[4]; + struct uart_port *port; + int baud = 115200; + int bits = 8; + int parity = 'n'; + int flow = 'n'; + + /* + * Check whether an invalid uart number has been specified, and + * if so, search for the first available port that does have + * console support. + */ + if ((co->index < 0) || (co->index >= UART_NR)) { + pr_debug("Console Port%x out of range\n", co->index); + return -EINVAL; + } + + if (of_property_read_u32_array(np, "reg", val32, 4) != 0) + return -EINVAL; + p->port.iobase = val32[1]; + p->port.membase = ioremap(p->port.iobase, 0x10000); + p->port.ops = &ma35d1serial_ops; + p->port.line = 0; + p->port.uartclk = 24000000; + + port = &ma35d1serial_ports[co->index].port; + return uart_set_options(port, co, baud, parity, bits, flow); +} + +static struct console ma35d1serial_console = { + .name = "ttyS", + .write = ma35d1serial_console_write, + .device = uart_console_device, + .setup = ma35d1serial_console_setup, + .flags = CON_PRINTBUFFER | CON_ENABLED, + .index = -1, + .data = &ma35d1serial_reg, +}; + +static void +ma35d1serial_console_init_port(void) +{ + int i = 0; + struct device_node *np; + + for_each_matching_node(np, ma35d1_serial_of_match) { + if (ma35d1serial_uart_nodes[i] == NULL) { + ma35d1serial_uart_nodes[i] = np; + i++; + } + } +} + +static int __init ma35d1serial_console_init(void) +{ + ma35d1serial_console_init_port(); + register_console(&ma35d1serial_console); + return 0; +} +console_initcall(ma35d1serial_console_init); + +#define MA35D1SERIAL_CONSOLE (&ma35d1serial_console) +#else +#define MA35D1SERIAL_CONSOLE NULL +#endif + +static struct uart_driver ma35d1serial_reg = { + .owner = THIS_MODULE, + .driver_name = "serial", + .dev_name = "ttyS", + .major = TTY_MAJOR, + .minor = 64, + .cons = MA35D1SERIAL_CONSOLE, + .nr = UART_NR, +}; + +/** + * Suspend one serial port. + */ +void ma35d1serial_suspend_port(int line) +{ + uart_suspend_port(&ma35d1serial_reg, &ma35d1serial_ports[line].port); +} +EXPORT_SYMBOL(ma35d1serial_suspend_port); + +/** + * Resume one serial port. + */ +void ma35d1serial_resume_port(int line) +{ + struct uart_ma35d1_port *up = &ma35d1serial_ports[line]; + + uart_resume_port(&ma35d1serial_reg, &up->port); +} +EXPORT_SYMBOL(ma35d1serial_resume_port); + +/* + * Register a set of serial devices attached to a platform device. + * The list is terminated with a zero flags entry, which means we expect + * all entries to have at least UPF_BOOT_AUTOCONF set. + */ +static int ma35d1serial_probe(struct platform_device *pdev) +{ + struct resource *res_mem; + struct uart_ma35d1_port *up; + int ret; + struct clk *clk; + int err; + + if (pdev->dev.of_node) { + ret = of_alias_get_id(pdev->dev.of_node, "serial"); + if (ret < 0) { + dev_err(&pdev->dev, + "failed to get alias/pdev id, errno %d\n", + ret); + return ret; + } + } + up = &ma35d1serial_ports[ret]; + up->port.line = ret; + res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res_mem) + return -ENODEV; + + up->port.iobase = res_mem->start; + up->port.membase = ioremap(up->port.iobase, 0x10000); + up->port.ops = &ma35d1serial_ops; + + spin_lock_init(&up->port.lock); + + clk = of_clk_get(pdev->dev.of_node, 0); + if (IS_ERR(clk)) { + err = PTR_ERR(clk); + dev_err(&pdev->dev, "failed to get core clk: %d\n", err); + return -ENOENT; + } + err = clk_prepare_enable(clk); + if (err) + return -ENOENT; + + if (up->port.line != 0) + up->port.uartclk = clk_get_rate(clk); + up->port.irq = platform_get_irq(pdev, 0); + up->port.dev = &pdev->dev; + up->port.flags = UPF_BOOT_AUTOCONF; + up->port.rs485_config = ma35d1serial_config_rs485; + ret = uart_add_one_port(&ma35d1serial_reg, &up->port); + platform_set_drvdata(pdev, up); + return 0; +} + +/* + * Remove serial ports registered against a platform device. + */ +static int ma35d1serial_remove(struct platform_device *dev) +{ + int i; + struct uart_port *port = platform_get_drvdata(dev); + + free_irq(port->irq, port); + for (i = 0; i < UART_NR; i++) { + struct uart_ma35d1_port *up = &ma35d1serial_ports[i]; + + if (up->port.dev == &dev->dev) + uart_remove_one_port(&ma35d1serial_reg, &up->port); + } + return 0; +} + +static int ma35d1serial_suspend(struct platform_device *dev, + pm_message_t state) +{ + int i; + struct uart_ma35d1_port *up; + + if (dev->dev.of_node) + i = of_alias_get_id(dev->dev.of_node, "serial"); + if (i < 0) { + dev_err(&dev->dev, "failed to get alias/pdev id, errno %d\n", + i); + return i; + } + up = &ma35d1serial_ports[i]; + if (i == 0) { + up->console_baud_rate = serial_in(up, UART_REG_BAUD); + up->console_line = serial_in(up, UART_REG_LCR); + up->console_int = serial_in(up, UART_REG_IER); + } + return 0; +} + +static int ma35d1serial_resume(struct platform_device *dev) +{ + int i; + struct uart_ma35d1_port *up; + + if (dev->dev.of_node) + i = of_alias_get_id(dev->dev.of_node, "serial"); + if (i < 0) { + dev_err(&dev->dev, "failed to get alias/pdev id, errno %d\n", + i); + return i; + } + up = &ma35d1serial_ports[i]; + if (i == 0) { + serial_out(up, UART_REG_BAUD, up->console_baud_rate); + serial_out(up, UART_REG_LCR, up->console_line); + serial_out(up, UART_REG_IER, up->console_int); + } + return 0; +} + +static struct platform_driver ma35d1serial_driver = { + .probe = ma35d1serial_probe, + .remove = ma35d1serial_remove, + .suspend = ma35d1serial_suspend, + .resume = ma35d1serial_resume, + .driver = { + .name = "ma35d1-uart", + .owner = THIS_MODULE, + .of_match_table = of_match_ptr(ma35d1_serial_of_match), + }, +}; + +static int __init ma35d1serial_init(void) +{ + int ret; + + ret = uart_register_driver(&ma35d1serial_reg); + if (ret) + return ret; + ret = platform_driver_register(&ma35d1serial_driver); + if (ret) + uart_unregister_driver(&ma35d1serial_reg); + return ret; +} + +static void __exit ma35d1serial_exit(void) +{ + platform_driver_unregister(&ma35d1serial_driver); + uart_unregister_driver(&ma35d1serial_reg); +} + +module_init(ma35d1serial_init); +module_exit(ma35d1serial_exit); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("MA35D1 serial driver"); +MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR); + diff --git a/drivers/tty/serial/ma35d1_serial.h b/drivers/tty/serial/ma35d1_serial.h new file mode 100644 index 000000000000..5fd845c31b29 --- /dev/null +++ b/drivers/tty/serial/ma35d1_serial.h @@ -0,0 +1,93 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * MA35D1 serial driver header file + * Copyright (C) 2023 Nuvoton Technology Corp. + */ +#ifndef __MA35D1_SERIAL_H__ +#define __MA35D1_SERIAL_H__ + +/* UART Receive/Transmit Buffer Register */ +#define UART_REG_RBR 0x00 +#define UART_REG_THR 0x00 + +/* UART Interrupt Enable Register */ +#define UART_REG_IER 0x04 +#define RDA_IEN 0x00000001 /* RBR Available Interrupt Enable */ +#define THRE_IEN 0x00000002 /* THR Empty Interrupt Enable */ +#define RLS_IEN 0x00000004 /* RX Line Status Interrupt Enable */ +#define RTO_IEN 0x00000010 /* RX Time-out Interrupt Enable */ +#define BUFERR_IEN 0x00000020 /* Buffer Error Interrupt Enable */ +#define TIME_OUT_EN 0x00000800 /* RX Buffer Time-out Counter Enable */ + +/* UART FIFO Control Register */ +#define UART_REG_FCR 0x08 +#define RFR 0x00000002 /* RX Field Software Reset */ +#define TFR 0x00000004 /* TX Field Software Reset */ + +/* UART Line Control Register */ +#define UART_REG_LCR 0x0C +#define NSB 0x00000004 /* Number of “STOP Bit” */ +#define PBE 0x00000008 /* Parity Bit Enable */ +#define EPE 0x00000010 /* Even Parity Enable */ +#define SPE 0x00000020 /* Stick Parity Enable */ +#define BCB 0x00000040 /* Break Control */ + +/* UART Modem Control Register */ +#define UART_REG_MCR 0x10 +#define RTS 0x00000020 /* nRTS Signal Control */ +#define RTSACTLV 0x00000200 /* nRTS Pin Active Level */ +#define RTSSTS 0x00002000 /* nRTS Pin Status (Read Only) */ + +/* UART Modem Status Register */ +#define UART_REG_MSR 0x14 +#define CTSDETF 0x00000001 /* Detect nCTS State Change Flag */ +#define CTSSTS 0x00000010 /* nCTS Pin Status (Read Only) */ +#define CTSACTLV 0x00000100 /* nCTS Pin Active Level */ + +/* UART FIFO Status Register */ +#define UART_REG_FSR 0x18 +#define RX_OVER_IF 0x00000001 /* RX Overflow Error Interrupt Flag */ +#define PEF 0x00000010 /* Parity Error Flag*/ +#define FEF 0x00000020 /* Framing Error Flag */ +#define BIF 0x00000040 /* Break Interrupt Flag */ +#define RX_EMPTY 0x00004000 /* Receiver FIFO Empty (Read Only) */ +#define RX_FULL 0x00008000 /* Receiver FIFO Full (Read Only) */ +#define TX_EMPTY 0x00400000 /* Transmitter FIFO Empty (Read Only) */ +#define TX_FULL 0x00800000 /* Transmitter FIFO Full (Read Only) */ +#define TX_OVER_IF 0x01000000 /* TX Overflow Error Interrupt Flag */ +#define TE_FLAG 0x10000000 /* Transmitter Empty Flag (Read Only) */ + +/* UART Interrupt Status Register */ +#define UART_REG_ISR 0x1C +#define RDA_IF 0x00000001 /* RBR Available Interrupt Flag */ +#define THRE_IF 0x00000002 /* THR Empty Interrupt Flag */ +#define RLSIF 0x00000004 /* Receive Line Interrupt Flag */ +#define MODEMIF 0x00000008 /* MODEM Interrupt Flag */ +#define RXTO_IF 0x00000010 /* RX Time-out Interrupt Flag */ +#define BUFEIF 0x00000020 /* Buffer Error Interrupt Flag */ +#define WK_IF 0x00000040 /* UART Wake-up Interrupt Flag */ +#define RDAINT 0x00000100 /* RBR Available Interrupt Indicator */ +#define THRE_INT 0x00000200 /* THR Empty Interrupt Indicator */ + +/* UART Time-out Register */ +#define UART_REG_TOR 0x20 + +/* UART Baud Rate Divider Register */ +#define UART_REG_BAUD 0x24 + +/* UART Alternate Control/Status Register */ +#define UART_REG_ALT_CSR 0x2C + +/* UART Function Select Register */ +#define UART_FUN_SEL 0x30 +#define FUN_SEL_UART 0x00000000 +#define FUN_SEL_RS485 0x00000003 +#define FUN_SEL_MASK 0x00000007 + +/* UART Wake-up Control Register */ +#define UART_REG_WKCTL 0x40 + +/* UART Wake-up Status Register */ +#define UART_REG_WKSTS 0x44 + +#endif /* __MA35D1_SERIAL_H__ */ diff --git a/include/uapi/linux/serial_core.h b/include/uapi/linux/serial_core.h index 281fa286555c..c6d53db17042 100644 --- a/include/uapi/linux/serial_core.h +++ b/include/uapi/linux/serial_core.h @@ -279,4 +279,7 @@ /* Sunplus UART */ #define PORT_SUNPLUS 123 +/* Nuvoton MA35D1 UART */ +#define PORT_MA35D1 124 + #endif /* _UAPILINUX_SERIAL_CORE_H */