From patchwork Tue Mar 14 15:28:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 663702 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4EAFEC7618B for ; Tue, 14 Mar 2023 15:28:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231201AbjCNP2q (ORCPT ); Tue, 14 Mar 2023 11:28:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57518 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230521AbjCNP2o (ORCPT ); Tue, 14 Mar 2023 11:28:44 -0400 Received: from mail-lj1-x22a.google.com (mail-lj1-x22a.google.com [IPv6:2a00:1450:4864:20::22a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B5FED3B3DB for ; Tue, 14 Mar 2023 08:28:41 -0700 (PDT) Received: by mail-lj1-x22a.google.com with SMTP id h3so16399771lja.12 for ; Tue, 14 Mar 2023 08:28:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678807720; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=dDrs6JyeTYzM6UbBJjwqEiLM0mM7HZ/Cu05l6aEARFA=; b=IFE6Gu3pkatgASwbx1ImpERuqNfGoEv4bKaRQZJgSsFYmX9pyq789ui74anr0GCEgf 2xhhKtZyoTkYjXzPauAL1Zp41IK+Vpjlwq+hoO13s91dFAMtE6VgaJnabahi+PpOaeQo 7cDgmExTSrb/GiJspQc4v8qgRrsmpmSSEM7cUYx38aDmKcw+l1lyUJ+yGQkPUySaOkpL 1jT0ETnMz6lohpMpRS3SwQcgxd/g2g4M6hw4mQ2lAJYlCijRKOLW0Y5X40UVcfpE3jPE 885KfrBnSHaQMS1LZzaG2dZVEoQFavz1LBj4jqiCpXSqIda3x3QRT0E1SgBQ7WHVOlY9 cTAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678807720; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dDrs6JyeTYzM6UbBJjwqEiLM0mM7HZ/Cu05l6aEARFA=; b=zygt+QN4qmoVGbHQCYtS0bV6HGLMzw+tPLZEnZwv89iCe8o9HRpdqHHmnwgw7lI02X JO2+xnvetfwZS3ZkPafZds/DOnFVFUYrC9LGSmsd+PtIucD6wb+ZkqTnCUGBpGnRiFOs RdQzLhMM2muNG8/tUWpotIJ+OytA7h4oYmWdtVf9WSC9/DWhx6h42esozwPMlngHmNoA rST+r7tuPWmUFD7bdMhbBXwNMDlTqeYKg9xvJPS2gk2y67OD5p7E09XLYDLsto1fIn41 PX+yZfLyWnbKjFmgTmpzU6HiI9IRui4eVJajHdQY4wEY7CGpmDW8Hj6MB4tSqzLXAc41 HakQ== X-Gm-Message-State: AO0yUKXOPnEivtbK3SxiqMQm5X+kBarboC3Gm8iqMAIP2T9/dvYTc7Qi udcF6AEW/UneulvxBmHIVgurkg== X-Google-Smtp-Source: AK7set+AKW5h3+gpYUWs5M8YeHUiHDyWaDoRGbpKtAv13E6yGkGt34J83LUQNCU+EhNDQZ0o+KzEBA== X-Received: by 2002:a2e:83c6:0:b0:293:5360:162b with SMTP id s6-20020a2e83c6000000b002935360162bmr4084469ljh.11.1678807719958; Tue, 14 Mar 2023 08:28:39 -0700 (PDT) Received: from [192.168.1.101] (abyj16.neoplus.adsl.tpnet.pl. [83.9.29.16]) by smtp.gmail.com with ESMTPSA id 27-20020a2e165b000000b002986a977bf2sm491529ljw.90.2023.03.14.08.28.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Mar 2023 08:28:39 -0700 (PDT) From: Konrad Dybcio Date: Tue, 14 Mar 2023 16:28:32 +0100 Subject: [PATCH v4 01/14] dt-bindings: display/msm: gpu: Document GMU wrapper-equipped A6xx MIME-Version: 1.0 Message-Id: <20230223-topic-gmuwrapper-v4-1-e987eb79d03f@linaro.org> References: <20230223-topic-gmuwrapper-v4-0-e987eb79d03f@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v4-0-e987eb79d03f@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1678807716; l=3204; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=6sAUPUwHP7+WUPx0qnkXu1yRwFCLU2UOzBhHFKkRGTM=; b=mV+9zzv7CDxkMqctTdkZFuDUkQFR5lB3OtJchHXfOYHhrrpWJ/oHSNLECv+KrnMciFrDa+s7/Rx9 dsByIHe1CGn7Aexc8isUndJ0jhglIt6f9uZXVUBWv3VqK6RfeBKH X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The "GMU Wrapper" is Qualcomm's name for "let's treat the GPU blocks we'd normally assign to the GMU as if they were a part of the GMU, even though they are not". It's a (good) software representation of the GMU_CX and GMU_GX register spaces within the GPUSS that helps us programatically treat these de-facto GMU-less parts in a way that's very similar to their GMU-equipped cousins, massively saving up on code duplication. The "wrapper" register space was specifically designed to mimic the layout of a real GMU, though it rather obviously does not have the M3 core et al. GMU wrapper-equipped A6xx GPUs require clocks and clock-names to be specified under the GPU node, just like their older cousins. Account for that. Signed-off-by: Konrad Dybcio --- .../devicetree/bindings/display/msm/gpu.yaml | 57 ++++++++++++++++++---- 1 file changed, 48 insertions(+), 9 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Documentation/devicetree/bindings/display/msm/gpu.yaml index d4191cca71fb..ac1a9bce2042 100644 --- a/Documentation/devicetree/bindings/display/msm/gpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml @@ -36,10 +36,7 @@ properties: reg-names: minItems: 1 - items: - - const: kgsl_3d0_reg_memory - - const: cx_mem - - const: cx_dbgc + maxItems: 3 interrupts: maxItems: 1 @@ -157,16 +154,58 @@ allOf: required: - clocks - clock-names + - if: properties: compatible: contains: - pattern: '^qcom,adreno-6[0-9][0-9]\.[0-9]$' - - then: # Since Adreno 6xx series clocks should be defined in GMU + enum: + - qcom,adreno-610.0 + - qcom,adreno-619.1 + then: properties: - clocks: false - clock-names: false + clock-names: + items: + - const: core + description: GPU Core clock + - const: iface + description: GPU Interface clock + - const: mem_iface + description: GPU Memory Interface clock + - const: alt_mem_iface + description: GPU Alternative Memory Interface clock + - const: gmu + description: CX GMU clock + - const: xo + description: GPUCC clocksource clock + + reg-names: + minItems: 1 + items: + - const: kgsl_3d0_reg_memory + - const: cx_dbgc + + required: + - clocks + - clock-names + else: + if: + properties: + compatible: + contains: + pattern: '^qcom,adreno-6[0-9][0-9]\.[0-9]$' + + then: # Starting with A6xx, the clocks are usually defined in the GMU node + properties: + clocks: false + clock-names: false + + reg-names: + minItems: 1 + items: + - const: kgsl_3d0_reg_memory + - const: cx_mem + - const: cx_dbgc examples: - | From patchwork Tue Mar 14 15:28:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 663701 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 44847C6FD1C for ; Tue, 14 Mar 2023 15:28:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231229AbjCNP2s (ORCPT ); Tue, 14 Mar 2023 11:28:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57910 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229687AbjCNP2r (ORCPT ); Tue, 14 Mar 2023 11:28:47 -0400 Received: from mail-lj1-x230.google.com (mail-lj1-x230.google.com [IPv6:2a00:1450:4864:20::230]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8292352F44 for ; Tue, 14 Mar 2023 08:28:43 -0700 (PDT) Received: by mail-lj1-x230.google.com with SMTP id h3so16399870lja.12 for ; Tue, 14 Mar 2023 08:28:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678807721; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=FfpC0lXYq1ll6nbzoGKkSBMv0WmddnDy3ZKS7f0bm/s=; b=nuXeOgG35nLhpQRRtNMHfnLyZD6r104D193hTDJ6SUD6UTROZX49ztDyCxB5b/yXQL Rqb9pP3md5/C8Pu3IazHspSOZQQVt6W22h0N8rTzTPk8yL945NI0eDpXxvOZh69Nnhfs TRklrmiV3rQZHKy6dGYTuwmTbUntIN6lfgzEuNuJNcgyR/Xieck5pWDmV7+LPzgoZZt4 UDwFts4TWGaGsk6Xz/9N4rVmOXQ9JM27IvkiXSBEjZtHVhlPpIM1T8jxGBF9WQoJz3IU wCS5jes6BWXkCB+bOFcYDWwwKfFxpQGAxDdRge+5gd4JroLTe6+UmvpmXAUOXiD4DVwu vSqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678807721; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FfpC0lXYq1ll6nbzoGKkSBMv0WmddnDy3ZKS7f0bm/s=; b=D/b+9uDhwr+GTjgMOdWwVKalVX8DvRUIZtx7hHka5GRCA6xVJum/ZvnjK8nXEvBY9b 8V5jcrdouY+2C6bxI1npRjt4RaZstn/qto8FUpUzi+LQ0rMKjdMS6AvT9nZNdRcTgmWm IstvkgC8vwaN+TNFyANiXGtiwcRe8Y183JMKvrxogryReUTk9JD5TmBb113yEqTsUBSf Si790MOeraTS8JJhqRfNw2EW+APfiB9AlvZSeuzvianLgm88TPComDiRrU+uGgFct2CM 2A2VOL0kinu16cOKiBreTyJJfdnZqvncz4ZLp7s01MWXijeOa0e87zOlALpvnes2VKKS m6Gw== X-Gm-Message-State: AO0yUKVmrUfhgQkPCiEFVtqqpP9inJFXOxRCc2CQ9sF1tMk6/CKbhyav Sk1wrl/avxrtcHodjhgWO1Hv3w== X-Google-Smtp-Source: AK7set/WntUhZuSNUQTrPjCTj4ukX0xl87beorxjM9H0yP4/SY9PWs7JVDdulaM8wwYD1Se+d2giaQ== X-Received: by 2002:a2e:93c6:0:b0:295:a33f:5349 with SMTP id p6-20020a2e93c6000000b00295a33f5349mr11157007ljh.26.1678807721760; Tue, 14 Mar 2023 08:28:41 -0700 (PDT) Received: from [192.168.1.101] (abyj16.neoplus.adsl.tpnet.pl. [83.9.29.16]) by smtp.gmail.com with ESMTPSA id 27-20020a2e165b000000b002986a977bf2sm491529ljw.90.2023.03.14.08.28.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Mar 2023 08:28:41 -0700 (PDT) From: Konrad Dybcio Date: Tue, 14 Mar 2023 16:28:33 +0100 Subject: [PATCH v4 02/14] dt-bindings: display/msm/gmu: Add GMU wrapper MIME-Version: 1.0 Message-Id: <20230223-topic-gmuwrapper-v4-2-e987eb79d03f@linaro.org> References: <20230223-topic-gmuwrapper-v4-0-e987eb79d03f@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v4-0-e987eb79d03f@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1678807716; l=3283; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=UT3xDmXTHRxoAqg/suyw+w4CBgyq4mbs1kv24/YUgS4=; b=Yj3XYeUYs1m8xSmfDaz+G1H2jht5+3yszWDs4/x/w6AR5a0OpS9HKzKChzuLlKQk2FjWMjVL954/ cJyNHPETCk3lA8OCiyigoRSsoyRRc0ziAMQ3HyyxyrTvcopQdhtW X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The "GMU Wrapper" is Qualcomm's name for "let's treat the GPU blocks we'd normally assign to the GMU as if they were a part of the GMU, even though they are not". It's a (good) software representation of the GMU_CX and GMU_GX register spaces within the GPUSS that helps us programatically treat these de-facto GMU-less parts in a way that's very similar to their GMU-equipped cousins, massively saving up on code duplication. The "wrapper" register space was specifically designed to mimic the layout of a real GMU, though it rather obviously does not have the M3 core et al. To sum it all up, the GMU wrapper is essentially a register space within the GPU, which Linux sees as a dumbed-down regular GMU: there's no clocks, interrupts, multiple reg spaces, iommus and OPP. Document it. Signed-off-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/display/msm/gmu.yaml | 49 ++++++++++++++++------ 1 file changed, 37 insertions(+), 12 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml b/Documentation/devicetree/bindings/display/msm/gmu.yaml index ab14e81cb050..021373e686e1 100644 --- a/Documentation/devicetree/bindings/display/msm/gmu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gmu.yaml @@ -19,16 +19,18 @@ description: | properties: compatible: - items: - - pattern: '^qcom,adreno-gmu-6[0-9][0-9]\.[0-9]$' - - const: qcom,adreno-gmu + oneOf: + - items: + - pattern: '^qcom,adreno-gmu-6[0-9][0-9]\.[0-9]$' + - const: qcom,adreno-gmu + - const: qcom,adreno-gmu-wrapper reg: - minItems: 3 + minItems: 1 maxItems: 4 reg-names: - minItems: 3 + minItems: 1 maxItems: 4 clocks: @@ -44,7 +46,6 @@ properties: - description: GMU HFI interrupt - description: GMU interrupt - interrupt-names: items: - const: hfi @@ -72,14 +73,8 @@ required: - compatible - reg - reg-names - - clocks - - clock-names - - interrupts - - interrupt-names - power-domains - power-domain-names - - iommus - - operating-points-v2 additionalProperties: false @@ -216,6 +211,27 @@ allOf: - const: cxo - const: axi - const: memnoc + - if: + properties: + compatible: + contains: + const: qcom,adreno-gmu-wrapper + then: + properties: + reg: + items: + - description: GMU wrapper register space + reg-names: + items: + - const: gmu + else: + required: + - clocks + - clock-names + - interrupts + - interrupt-names + - iommus + - operating-points-v2 examples: - | @@ -249,3 +265,12 @@ examples: iommus = <&adreno_smmu 5>; operating-points-v2 = <&gmu_opp_table>; }; + + gmu_wrapper: gmu@596a000 { + compatible = "qcom,adreno-gmu-wrapper"; + reg = <0x0596a000 0x30000>; + reg-names = "gmu"; + power-domains = <&gpucc GPU_CX_GDSC>, + <&gpucc GPU_GX_GDSC>; + power-domain-names = "cx", "gx"; + }; From patchwork Tue Mar 14 15:28:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 663700 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0067DC74A4B for ; Tue, 14 Mar 2023 15:28:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231592AbjCNP24 (ORCPT ); Tue, 14 Mar 2023 11:28:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58106 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229571AbjCNP2t (ORCPT ); Tue, 14 Mar 2023 11:28:49 -0400 Received: from mail-lj1-x234.google.com (mail-lj1-x234.google.com [IPv6:2a00:1450:4864:20::234]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A1D3E559C3 for ; Tue, 14 Mar 2023 08:28:45 -0700 (PDT) Received: by mail-lj1-x234.google.com with SMTP id z5so16399500ljc.8 for ; Tue, 14 Mar 2023 08:28:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678807725; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=hsp+OP49dyvTA0hg06hKxLnq+WOs2dGZ48Sal52G9bk=; b=CGXtFAlrCUIohL3loQwAGHDCaABKaw299PVDfZQOpH39MnvHu5Y6d5mR6o5KNPW/RH sbdHMKHhmPBHZOXInm/6RCNkxYyERcbYtFn6fYVtuOotl7+ML6oYAyCC445gHTGsnED8 KmdxxshSquUUC31++k5Mu3svyEVywEpoJq/1IqnEzROsO+31zLxSHqRG5ohDR2uiFbvr q/v+ajfSH9Oa0RRLqX5hVneyoDMXGhqb2Nw02L6wdfplCLcr53IkxkXyhBKmFeEGsTir ODkFSKcOJZYTaxB8Fg5ppXhkTFlHw0IAbg2ORzqi8mV3EjxdqYOBjgpwGrlkuRl30VPc adVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678807725; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hsp+OP49dyvTA0hg06hKxLnq+WOs2dGZ48Sal52G9bk=; b=WQhlPgJofvjKYcLpkxKEDSty1CrExrzJoUq3kB/PNZbgfJ0rzIen1W5MlHg8w2I7ky fiokLpwO/pSJCdxxRPB+8wEZgNbvlEozPqcwcSDtx6sJzYUZO5Q97MZKx8RN752AbJKD 3BdzQV7LI9lznWLjEJcyR5MdVYlAslADpI626W2WKQTTJaCc/uU4XimGP+gMtzh0rcK0 8EVN6/hKP8x5MU25T2KlfXyselSkXXw14pAXacGFB3+AXq9Jcm8Qctp4PaZQ/YW1bqLo Y6QNlCO2h13tMnSZPYyGFafU20LXtnfj4IGq+sBR8gYfZjthxCNZheYZUEcGi3pW57Tk ccww== X-Gm-Message-State: AO0yUKUVpnszIbtHsUMD4R8wBflAg7nsoJCCwQiu40Mm3QM73WuASrCf ntWdlSKA1aIczAvPAXSikTGrDg== X-Google-Smtp-Source: AK7set8UwjTvNY569Dzv+O3Rg1WzvAvqAYQ7+gA21ZsnZjBYnf6lVmfdrWCYg6a7PBog4S+VVa3xPg== X-Received: by 2002:a2e:131a:0:b0:295:93eb:1c01 with SMTP id 26-20020a2e131a000000b0029593eb1c01mr11806514ljt.25.1678807725141; Tue, 14 Mar 2023 08:28:45 -0700 (PDT) Received: from [192.168.1.101] (abyj16.neoplus.adsl.tpnet.pl. [83.9.29.16]) by smtp.gmail.com with ESMTPSA id 27-20020a2e165b000000b002986a977bf2sm491529ljw.90.2023.03.14.08.28.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Mar 2023 08:28:44 -0700 (PDT) From: Konrad Dybcio Date: Tue, 14 Mar 2023 16:28:35 +0100 Subject: [PATCH v4 04/14] drm/msm/a6xx: Extend and explain UBWC config MIME-Version: 1.0 Message-Id: <20230223-topic-gmuwrapper-v4-4-e987eb79d03f@linaro.org> References: <20230223-topic-gmuwrapper-v4-0-e987eb79d03f@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v4-0-e987eb79d03f@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1678807716; l=2979; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=jfJopFwWQyGceVNOEMOJgd5qDKEUsswtNczspv0fE70=; b=GTW6adG8HrXjwT99h/qJn2ktz6+O907jU1DOFTqH811t7emgC9lzJjXGPyflNTe1eTdiM0XxIn/g 1PeE0h08DwJHYz2iaT40X2IGJnlgctdBEFToirOL7OamNhxVZhKl X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Rename lower_bit to hbb_lo and explain what it signifies. Add explanations (wherever possible to other tunables). Port setting min_access_length, ubwc_mode and hbb_hi from downstream. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 39 +++++++++++++++++++++++++++-------- 1 file changed, 30 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index a849db8252f2..2f55dac52833 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -786,10 +786,25 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu) static void a6xx_set_ubwc_config(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); - u32 lower_bit = 2; - u32 amsbc = 0; + /* Unknown, introduced with A650 family, related to UBWC mode/ver 4 */ u32 rgb565_predicator = 0; + /* Unknown, introduced with A650 family */ u32 uavflagprd_inv = 0; + /* Whether the minimum access length is 64 bits */ + u32 min_acc_len = 0; + /* Entirely magic, per-GPU-gen value */ + u32 ubwc_mode = 0; + /* + * The Highest Bank Bit value represents the bit of the highest DDR bank. + * We then subtract 13 from it (13 is the minimum value allowed by hw) and + * write the lowest two bits of the remaining value as hbb_lo and the + * one above it as hbb_hi to the hardware. This should ideally use DRAM + * type detection. + */ + u32 hbb_hi = 0; + u32 hbb_lo = 2; + /* Unknown, introduced with A640/680 */ + u32 amsbc = 0; /* a618 is using the hw default values */ if (adreno_is_a618(adreno_gpu)) @@ -800,25 +815,31 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu)) { /* TODO: get ddr type from bootloader and use 2 for LPDDR4 */ - lower_bit = 3; + hbb_lo = 3; amsbc = 1; rgb565_predicator = 1; uavflagprd_inv = 2; } if (adreno_is_7c3(adreno_gpu)) { - lower_bit = 1; + hbb_lo = 1; amsbc = 1; rgb565_predicator = 1; uavflagprd_inv = 2; } gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL, - rgb565_predicator << 11 | amsbc << 4 | lower_bit << 1); - gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, lower_bit << 1); - gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, - uavflagprd_inv << 4 | lower_bit << 1); - gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, lower_bit << 21); + rgb565_predicator << 11 | hbb_hi << 10 | amsbc << 4 | + min_acc_len << 3 | hbb_lo << 1 | ubwc_mode); + + gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, hbb_hi << 4 | + min_acc_len << 3 | hbb_lo << 1 | ubwc_mode); + + gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, hbb_hi << 10 | + uavflagprd_inv << 4 | min_acc_len << 3 | + hbb_lo << 1 | ubwc_mode); + + gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, min_acc_len << 23 | hbb_lo << 21); } static int a6xx_cp_init(struct msm_gpu *gpu) From patchwork Tue Mar 14 15:28:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 663699 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D2871C6FD1C for ; Tue, 14 Mar 2023 15:29:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231484AbjCNP3I (ORCPT ); Tue, 14 Mar 2023 11:29:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58556 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231553AbjCNP2z (ORCPT ); Tue, 14 Mar 2023 11:28:55 -0400 Received: from mail-lj1-x232.google.com (mail-lj1-x232.google.com [IPv6:2a00:1450:4864:20::232]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E2AEA6EB98 for ; Tue, 14 Mar 2023 08:28:49 -0700 (PDT) Received: by mail-lj1-x232.google.com with SMTP id t14so16423956ljd.5 for ; Tue, 14 Mar 2023 08:28:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678807728; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=159lZK1VC8AnArbTbfywvfz47MuAlqr+e0q9A9rUbAY=; b=ybkS1ks85NwBg0oo4KVc4YOEPbJDHyxaTPYyY5Ix/0wWYBycqMFQxYFzrOVQ6wjypO fQmQycMbmWZvRFv7EduPzK10eesNeyMeiZJvpoHNqbbImGbWHlCu0F/fNvwSaVttOIlN JSbW0fOGV5ZttCFGvf6VYxPo8gUKcGGVxpMglgQDoUl30mV6R4KoNhgzpaQ2j9Glukbz RMENp5oNU5cfRTprvVqD6orxx+uicybh/W3zYauQtLBj6JZRMKQ45UVZCOvhq+SHvDd6 lJWX0KvsUlPjFe6eyjd21Ka+W3Hcqs8eiTJMKR6z32H0p0/HpJqW2tyDrqH1IaokaCXz +56A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678807728; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=159lZK1VC8AnArbTbfywvfz47MuAlqr+e0q9A9rUbAY=; b=DqoJvwyJsNawoux0tX+4q0PxeJg9v25qF9RyrKljXZ7zzeuiVgrZN8pCzwkpkL3J3s hOkKP/p62set0gpiw5gmZYsixXAQdShVUPEWLkk4hf7qFXRV4FNmc6mvAnajvROlJ4rX v1b0cn9TKNAj2Byo3ViWXDEx84mtbshTB00a9bJGAjBo/jl9pl5qgifqqhDcD60WqA/o yJV0G6c4+jtGi3ZT+plcJ5qbh0vC7AFdtQGYv7JHbKcREsHUpZHle53ZrvQeP7UaLrXZ wseZhGb2+PemtnPNYwIIh8xCTJq+q72VjBUKMMsQ0gqU8JdTfux7/1AuOjuj0bA/40AQ duXg== X-Gm-Message-State: AO0yUKWxrSRd7mHio7AUh0zlbbyBHci+87CjDgUVgeKT8iMUfeNECi0f x3eb42S7MYdeXxjPt99vEsN87A== X-Google-Smtp-Source: AK7set95lDIxfeW2sbimzmWl+O6poG1xg+59izmaVd4VGvYk/eNDDUxvFvJ4rN1VRn8SyfcPqBex6Q== X-Received: by 2002:a05:651c:1059:b0:295:b96e:ca99 with SMTP id x25-20020a05651c105900b00295b96eca99mr14017598ljm.50.1678807728292; Tue, 14 Mar 2023 08:28:48 -0700 (PDT) Received: from [192.168.1.101] (abyj16.neoplus.adsl.tpnet.pl. [83.9.29.16]) by smtp.gmail.com with ESMTPSA id 27-20020a2e165b000000b002986a977bf2sm491529ljw.90.2023.03.14.08.28.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Mar 2023 08:28:48 -0700 (PDT) From: Konrad Dybcio Date: Tue, 14 Mar 2023 16:28:37 +0100 Subject: [PATCH v4 06/14] drm/msm/a6xx: Remove both GBIF and RBBM GBIF halt on hw init MIME-Version: 1.0 Message-Id: <20230223-topic-gmuwrapper-v4-6-e987eb79d03f@linaro.org> References: <20230223-topic-gmuwrapper-v4-0-e987eb79d03f@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v4-0-e987eb79d03f@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1678807716; l=1251; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=SQf5xqv6dgkFv8lqaRaSsqR3oatLGI4JEKv+JlvqW4k=; b=j0wqavMQyp9JVzEUb+dyZ3aehx3l+F1HEWpU/j8PV1u7+qyWbwNnPl8Ix1vohsIlZY8QP7XOf0G8 gFxAnV4NCSDkUzx+xsz2mPlEqsuMhpdcxfpQLRfk7YgDSyVTBnNy X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Currently we're only deasserting REG_A6XX_RBBM_GBIF_HALT, but we also need REG_A6XX_GBIF_HALT to be set to 0. For GMU-equipped GPUs this is done in a6xx_bus_clear_pending_transactions(), but for the GMU-less ones we have to do it *somewhere*. Unhalting both side by side sounds like a good plan and it won't cause any issues if it's unnecessary. Also, add a memory barrier to ensure it's gone through. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index a90847a3379a..70e9bd21ba3b 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1015,8 +1015,12 @@ static int hw_init(struct msm_gpu *gpu) } /* Clear GBIF halt in case GX domain was not collapsed */ - if (a6xx_has_gbif(adreno_gpu)) + if (a6xx_has_gbif(adreno_gpu)) { + gpu_write(gpu, REG_A6XX_GBIF_HALT, 0); gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, 0); + /* Let's make extra sure that the GPU can access the memory.. */ + mb(); + } gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_CNTL, 0); From patchwork Tue Mar 14 15:28:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 663698 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 67E7EC74A4B for ; Tue, 14 Mar 2023 15:29:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229866AbjCNP3W (ORCPT ); Tue, 14 Mar 2023 11:29:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58668 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231679AbjCNP25 (ORCPT ); Tue, 14 Mar 2023 11:28:57 -0400 Received: from mail-lj1-x236.google.com (mail-lj1-x236.google.com [IPv6:2a00:1450:4864:20::236]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 095468E3D6 for ; Tue, 14 Mar 2023 08:28:52 -0700 (PDT) Received: by mail-lj1-x236.google.com with SMTP id f16so16402318ljq.10 for ; Tue, 14 Mar 2023 08:28:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678807731; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=0QBfkwBASk6EqehMpj5iBWVthwGOhEMOaMUH5eoHlaw=; b=UepBCxqmyQ8a7htSDlTFI0ShFtEB7diji/pbqGjwg56DIr/pGL1FMQG23Kn4gVFUIH NWU7NEQOg6QEPw+QBNKkfk0e3g7KdwuL54ChUUC95zetLCTFMuNkWeytTRsZmOoAlBPh 6oKBWQ+Zrt2mvYnaj1zpDOe5mfV6hGiVgV8S4nFnuK92cLLCnctMeMoH5uimRkorSjJC hi7HBB16Btn0M0sTQJkP9rlv0qMBsA6gH2fdDc36OWvkMN9RwmYFYtyGhAjMCcaOXdv7 Iu3w3ma+ue36QNvHTEAvVstExQCK4oYWWSW8+plHHOxbDvNQ+AjF0T3Vli78h9Ec6XHk l0BA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678807731; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0QBfkwBASk6EqehMpj5iBWVthwGOhEMOaMUH5eoHlaw=; b=rQPqNCchtIb5cNgJ4YhXTDJKRTDJnGgErXp6Trl24tLi0h2zjU/iQ8r8HJlrChLJ1y 81CPdgIdH1I4+o7Kw2TuzVZ0Qvrs7F7P8ofF1vbkmShG1SPCX4ZQeF8HhG7yQip7DXZJ cCPXWm5xViGHR1XLv+aU8CgKcFxRMA2CWQRa1kxCrYju5OcjOcJvlyqT8B13+uOUy2yl SXfIZKgoG1oWiMR5/UHwL1jOHfBUxOJ9gif4bpaqNFWXVsWvWF9duGCf3zTNxU3QgTqV MJY7vG36gTKRaDonFO7HgKixjkFeUg6Zk7T33QTIpitwf/RPqLEbm+gUtn7GBAE77NxR YNlw== X-Gm-Message-State: AO0yUKV88mwP5xgS15PwU0rkoLgYkGHCsL/nnVuiwLmB+mz2ISOiJC0W pVG2eynuSvOAFnYarZofB7VJxQ== X-Google-Smtp-Source: AK7set9319x6pXFA2ZB5oQB5t6Vlb6uh1fRGtzfQAmcsGR0/P2fXfUFxvI6C2W5JvKGej6l20vdP9Q== X-Received: by 2002:a2e:909a:0:b0:295:a829:1c57 with SMTP id l26-20020a2e909a000000b00295a8291c57mr12082944ljg.20.1678807731546; Tue, 14 Mar 2023 08:28:51 -0700 (PDT) Received: from [192.168.1.101] (abyj16.neoplus.adsl.tpnet.pl. [83.9.29.16]) by smtp.gmail.com with ESMTPSA id 27-20020a2e165b000000b002986a977bf2sm491529ljw.90.2023.03.14.08.28.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Mar 2023 08:28:51 -0700 (PDT) From: Konrad Dybcio Date: Tue, 14 Mar 2023 16:28:39 +0100 Subject: [PATCH v4 08/14] drm/msm/a6xx: Add support for A619_holi MIME-Version: 1.0 Message-Id: <20230223-topic-gmuwrapper-v4-8-e987eb79d03f@linaro.org> References: <20230223-topic-gmuwrapper-v4-0-e987eb79d03f@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v4-0-e987eb79d03f@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1678807716; l=4940; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=RIb1PwuaJxl26QOFy9hE9BbhqyB0PIh+V+WoOWu9KIo=; b=h7jUht1chOrWGuBBXbU8DzuW6yjeui4Q0sDTGbH6GAeYwsfIT23zHYJDwYLDz3LenakP9X/KTBJ5 izASb5SjDlR6KxM03YuJv1h7kgCC7iusu/S20201Ob3fWj/jky89 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org A619_holi is a GMU-less variant of the already-supported A619 GPU. It's present on at least SM4350 (holi) and SM6375 (blair). No mesa changes are required. Add the required kernel-side support for it. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 42 ++++++++++++++++++++++++++------- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 ++++ 2 files changed, 39 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 70e9bd21ba3b..1c0e5e1df89c 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -614,14 +614,16 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state) return; /* Disable SP clock before programming HWCG registers */ - if (!adreno_has_gmu_wrapper(adreno_gpu)) + if (!adreno_has_gmu_wrapper(adreno_gpu) || + adreno_is_a619_holi(adreno_gpu)) gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 1, 0); for (i = 0; (reg = &adreno_gpu->info->hwcg[i], reg->offset); i++) gpu_write(gpu, reg->offset, state ? reg->value : 0); /* Enable SP clock */ - if (!adreno_has_gmu_wrapper(adreno_gpu)) + if (!adreno_has_gmu_wrapper(adreno_gpu) || + adreno_is_a619_holi(adreno_gpu)) gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 0, 1); gpu_write(gpu, REG_A6XX_RBBM_CLOCK_CNTL, state ? clock_cntl_on : 0); @@ -814,6 +816,9 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) if (adreno_is_a618(adreno_gpu)) return; + if (adreno_is_a619_holi(gpu)) + hbb_lo = 0; + if (adreno_is_a640_family(adreno_gpu)) amsbc = 1; @@ -1015,7 +1020,12 @@ static int hw_init(struct msm_gpu *gpu) } /* Clear GBIF halt in case GX domain was not collapsed */ - if (a6xx_has_gbif(adreno_gpu)) { + if (adreno_is_a619_holi(adreno_gpu)) { + gpu_write(gpu, REG_A6XX_GBIF_HALT, 0); + gpu_write(gpu, 0x18, 0); + /* Let's make extra sure that the GPU can access the memory.. */ + mb(); + } else if (a6xx_has_gbif(adreno_gpu)) { gpu_write(gpu, REG_A6XX_GBIF_HALT, 0); gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, 0); /* Let's make extra sure that the GPU can access the memory.. */ @@ -1024,6 +1034,9 @@ static int hw_init(struct msm_gpu *gpu) gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_CNTL, 0); + if (adreno_is_a619_holi(adreno_gpu)) + a6xx_sptprac_enable(gmu); + /* * Disable the trusted memory range - we don't actually supported secure * memory rendering at this point in time and we don't want to block off @@ -1301,7 +1314,8 @@ static void a6xx_dump(struct msm_gpu *gpu) #define GBIF_CLIENT_HALT_MASK BIT(0) #define GBIF_ARB_HALT_MASK BIT(1) #define VBIF_RESET_ACK_TIMEOUT 100 -#define VBIF_RESET_ACK_MASK 0x00f0 +#define VBIF_RESET_ACK_MASK 0xF0 +#define GPR0_GBIF_HALT_REQUEST 0x1E0 static void a6xx_recover(struct msm_gpu *gpu) { @@ -1358,10 +1372,16 @@ static void a6xx_recover(struct msm_gpu *gpu) /* Software-reset the GPU */ if (adreno_has_gmu_wrapper(adreno_gpu)) { - /* Halt the GX side of GBIF */ - gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, GBIF_GX_HALT_MASK); - spin_until(gpu_read(gpu, REG_A6XX_RBBM_GBIF_HALT_ACK) & - GBIF_GX_HALT_MASK); + if (adreno_is_a619_holi(adreno_gpu)) { + gpu_write(gpu, 0x18, GPR0_GBIF_HALT_REQUEST); + spin_until((gpu_read(gpu, REG_A6XX_RBBM_VBIF_GX_RESET_STATUS) & + (VBIF_RESET_ACK_MASK)) == VBIF_RESET_ACK_MASK); + } else { + /* Halt the GX side of GBIF */ + gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, GBIF_GX_HALT_MASK); + spin_until(gpu_read(gpu, REG_A6XX_RBBM_GBIF_HALT_ACK) & + GBIF_GX_HALT_MASK); + } /* Halt new client requests on GBIF */ gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_CLIENT_HALT_MASK); @@ -1783,6 +1803,9 @@ static int a6xx_pm_resume(struct msm_gpu *gpu) if (ret) goto err; + if (adreno_is_a619_holi(adreno_gpu)) + a6xx_sptprac_enable(gmu); + err: mutex_unlock(&a6xx_gpu->gmu.lock); @@ -1837,6 +1860,9 @@ static int a6xx_pm_suspend(struct msm_gpu *gpu) mutex_lock(&a6xx_gpu->gmu.lock); + if (adreno_is_a619_holi(adreno_gpu)) + a6xx_sptprac_disable(gmu); + clk_disable_unprepare(gpu->ebi1_clk); clk_bulk_disable_unprepare(gpu->nr_clocks, gpu->grp_clks); diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 2c0f0ef094cb..92ece15ec7d8 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -252,6 +252,11 @@ static inline int adreno_is_a619(struct adreno_gpu *gpu) return gpu->revn == 619; } +static inline int adreno_is_a619_holi(struct adreno_gpu *gpu) +{ + return adreno_is_a619(gpu) && adreno_has_gmu_wrapper(gpu); +} + static inline int adreno_is_a630(struct adreno_gpu *gpu) { return gpu->revn == 630; From patchwork Tue Mar 14 15:28:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 663697 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A73A7C6FD1D for ; Tue, 14 Mar 2023 15:29:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231530AbjCNP31 (ORCPT ); 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[83.9.29.16]) by smtp.gmail.com with ESMTPSA id 27-20020a2e165b000000b002986a977bf2sm491529ljw.90.2023.03.14.08.28.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Mar 2023 08:28:54 -0700 (PDT) From: Konrad Dybcio Date: Tue, 14 Mar 2023 16:28:41 +0100 Subject: [PATCH v4 10/14] drm/msm/a6xx: Fix some A619 tunables MIME-Version: 1.0 Message-Id: <20230223-topic-gmuwrapper-v4-10-e987eb79d03f@linaro.org> References: <20230223-topic-gmuwrapper-v4-0-e987eb79d03f@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v4-0-e987eb79d03f@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1678807716; l=1537; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=WDcj/M9aJ/8+tdxnVyFZAeDamawmN6hQgw+VzGKE91s=; b=T/5InnJU8B58RuzS79qY+AAoksalL8zOQ+JCAG2th1CRtFEh87n1KTepybkSWQo5GP+tt8vPUvkn 2Rj3TBOJD5wBtfFVeCWxK/FzGecgL0PHuYjTC/Z1POdGewZZIxo7 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Adreno 619 expects some tunables to be set differently. Make up for it. Fixes: b7616b5c69e6 ("drm/msm/adreno: Add A619 support") Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 776db13e2a26..f699f326021f 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1189,6 +1189,8 @@ static int hw_init(struct msm_gpu *gpu) gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00200200); else if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu)) gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300200); + else if (adreno_is_a619(adreno_gpu)) + gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00018000); else if (adreno_is_a610(adreno_gpu)) gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00080000); else @@ -1206,7 +1208,9 @@ static int hw_init(struct msm_gpu *gpu) a6xx_set_ubwc_config(gpu); /* Enable fault detection */ - if (adreno_is_a610(adreno_gpu)) + if (adreno_is_a619(adreno_gpu)) + gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x3fffff); + else if (adreno_is_a610(adreno_gpu)) gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x3ffff); else gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x1fffff); From patchwork Tue Mar 14 15:28:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 663696 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6BF6CC74A4B for ; Tue, 14 Mar 2023 15:29:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231439AbjCNP3m (ORCPT ); Tue, 14 Mar 2023 11:29:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59496 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231450AbjCNP3I (ORCPT ); Tue, 14 Mar 2023 11:29:08 -0400 Received: from mail-lj1-x22c.google.com (mail-lj1-x22c.google.com [IPv6:2a00:1450:4864:20::22c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 722E36BC33 for ; Tue, 14 Mar 2023 08:28:58 -0700 (PDT) Received: by mail-lj1-x22c.google.com with SMTP id a32so16413260ljr.9 for ; Tue, 14 Mar 2023 08:28:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678807738; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=b3xe4S3Sg3+fXQE7o6Jl9Wyr4UR5G14unF7soZYaMbg=; b=QZm8aOm8RbNlY40Q4XQU5d2gjJPbZzE/EPGKd9wIFP3yFDp4M3cFgET0nkBnXMXe/L bEm79j/TVkoRw9F/2BGgKcTpiB6bky/NEmE9CkdF1Z/Zt8U8C39U244fW229NNObm34/ ccvJGgfuH4axu1SJlvkP/6/4XO+BwbpLyyiFz6GRw87GBHcW+XBsZDK4hAKZFGo+cuOo DarmyslHPlLwRnDH/H/zNfF59z1r1exJ0qGBHH2zx/iuB2WjeuJB1ULy0DtcSbOCDMZO sP5NL6fM6M6Txdr9OTPBSZJem424Ayv4dnyf+wAht8gy5tn7P6ezpWFnvf1QofADTlXo +2dw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678807738; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=b3xe4S3Sg3+fXQE7o6Jl9Wyr4UR5G14unF7soZYaMbg=; b=TQxJ+FhhMI3neSgytiO0uVpiJGmQFHsMsCARIEtqKiX6Y+reu9zTVRPNvmuxwsy6Db dBgO9/HLvqMEWW6zTz1KR/4NDOKh+P4TkLUH8X96JaaFb+FYdFlnfXOKZlkJYEkuE+Vp bfW5qkBU89t8JQsDyutglQ7wYXQEyhJOttWSRDrpDVkAuWNzEOD97rt9TGXxbEis0ywu 2XE6gJPICVX6Jw2iHNatD45I/80j8w4G/AllqDWrCYEqDdrgp9sCQqYtyuQnXFrd4n6q 9bhOeVfOrfYSABLICYMkeXk9EsWa3wndmGBa7/XTBCTEfpcuTgJIBb5KGXLx3xy+pkRt K7/Q== X-Gm-Message-State: AO0yUKV6B0D45gJeg3Dfsm09W5sqef4IiU88gKiwJNOLrvg5BXswUJnO eEM2gVJuyCh37Cl3A4j8SFzeZQ== X-Google-Smtp-Source: AK7set/2lSTktOe20S80TTlPoFxsu2prw745PLGWGmCVZbk7wNrpyh/pjHPJ2hOD260NzZex7zfetA== X-Received: by 2002:a2e:8807:0:b0:295:9a9f:3f55 with SMTP id x7-20020a2e8807000000b002959a9f3f55mr11475513ljh.0.1678807737857; Tue, 14 Mar 2023 08:28:57 -0700 (PDT) Received: from [192.168.1.101] (abyj16.neoplus.adsl.tpnet.pl. [83.9.29.16]) by smtp.gmail.com with ESMTPSA id 27-20020a2e165b000000b002986a977bf2sm491529ljw.90.2023.03.14.08.28.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Mar 2023 08:28:57 -0700 (PDT) From: Konrad Dybcio Date: Tue, 14 Mar 2023 16:28:43 +0100 Subject: [PATCH v4 12/14] drm/msm/a6xx: Use adreno_is_aXYZ macros in speedbin matching MIME-Version: 1.0 Message-Id: <20230223-topic-gmuwrapper-v4-12-e987eb79d03f@linaro.org> References: <20230223-topic-gmuwrapper-v4-0-e987eb79d03f@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v4-0-e987eb79d03f@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1678807716; l=4256; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=k8ecRBr+PHIYBEN3eyTaSM0Q8/LOQMVQTU2+Qd88W0A=; b=3gvGXi1wDp8tvJizG2mCmembimJ6NEiodLsZGbAy715EhpeRtk7EXD8RLR26pFDIaz0VuTQeZ6k/ aWuHcLqxBjAMtTLuKKm/kvw2K8xAB56xwcwGeEjUcfSn3z7+hmO7 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Before transitioning to using per-SoC and not per-Adreno speedbin fuse values (need another patchset to land elsewhere), a good improvement/stopgap solution is to use adreno_is_aXYZ macros in place of explicit revision matching. Do so to allow differentiating between A619 and A619_holi. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 18 +++++++++--------- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 14 ++++++++++++-- 2 files changed, 21 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index dfd2d735e57f..71950a5fcc96 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2200,23 +2200,23 @@ static u32 adreno_7c3_get_speed_bin(u32 fuse) return UINT_MAX; } -static u32 fuse_to_supp_hw(struct device *dev, struct adreno_rev rev, u32 fuse) +static u32 fuse_to_supp_hw(struct device *dev, struct adreno_gpu *adreno_gpu, u32 fuse) { u32 val = UINT_MAX; - if (adreno_cmp_rev(ADRENO_REV(6, 1, 8, ANY_ID), rev)) + if (adreno_is_a618(adreno_gpu)) val = a618_get_speed_bin(fuse); - else if (adreno_cmp_rev(ADRENO_REV(6, 1, 9, ANY_ID), rev)) + else if (adreno_is_a619(adreno_gpu)) val = a619_get_speed_bin(fuse); - else if (adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), rev)) + else if (adreno_is_7c3(adreno_gpu)) val = adreno_7c3_get_speed_bin(fuse); - else if (adreno_cmp_rev(ADRENO_REV(6, 4, 0, ANY_ID), rev)) + else if (adreno_is_a640(adreno_gpu)) val = a640_get_speed_bin(fuse); - else if (adreno_cmp_rev(ADRENO_REV(6, 5, 0, ANY_ID), rev)) + else if (adreno_is_a650(adreno_gpu)) val = a650_get_speed_bin(fuse); if (val == UINT_MAX) { @@ -2229,7 +2229,7 @@ static u32 fuse_to_supp_hw(struct device *dev, struct adreno_rev rev, u32 fuse) return (1 << val); } -static int a6xx_set_supported_hw(struct device *dev, struct adreno_rev rev) +static int a6xx_set_supported_hw(struct device *dev, struct adreno_gpu *adreno_gpu) { u32 supp_hw; u32 speedbin; @@ -2248,7 +2248,7 @@ static int a6xx_set_supported_hw(struct device *dev, struct adreno_rev rev) return ret; } - supp_hw = fuse_to_supp_hw(dev, rev, speedbin); + supp_hw = fuse_to_supp_hw(dev, adreno_gpu, speedbin); ret = devm_pm_opp_set_supported_hw(dev, &supp_hw, 1); if (ret) @@ -2367,7 +2367,7 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) if (!adreno_has_gmu_wrapper(adreno_gpu)) a6xx_llc_slices_init(pdev, a6xx_gpu); - ret = a6xx_set_supported_hw(&pdev->dev, config->rev); + ret = a6xx_set_supported_hw(&pdev->dev, adreno_gpu); if (ret) { a6xx_destroy(&(a6xx_gpu->base.base)); return ERR_PTR(ret); diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 27c30a7694f4..da9f45a13b5d 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -268,9 +268,9 @@ static inline int adreno_is_a630(struct adreno_gpu *gpu) return gpu->revn == 630; } -static inline int adreno_is_a640_family(struct adreno_gpu *gpu) +static inline int adreno_is_a640(struct adreno_gpu *gpu) { - return (gpu->revn == 640) || (gpu->revn == 680); + return gpu->revn == 640; } static inline int adreno_is_a650(struct adreno_gpu *gpu) @@ -289,6 +289,11 @@ static inline int adreno_is_a660(struct adreno_gpu *gpu) return gpu->revn == 660; } +static inline int adreno_is_a680(struct adreno_gpu *gpu) +{ + return gpu->revn == 680; +} + /* check for a615, a616, a618, a619 or any derivatives */ static inline int adreno_is_a615_family(struct adreno_gpu *gpu) { @@ -306,6 +311,11 @@ static inline int adreno_is_a650_family(struct adreno_gpu *gpu) return gpu->revn == 650 || gpu->revn == 620 || adreno_is_a660_family(gpu); } +static inline int adreno_is_a640_family(struct adreno_gpu *gpu) +{ + return adreno_is_a640(gpu) || adreno_is_a680(gpu); +} + u64 adreno_private_address_space_size(struct msm_gpu *gpu); int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx, uint32_t param, uint64_t *value, uint32_t *len); From patchwork Tue Mar 14 15:28:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 663695 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4600BC7618A for ; Tue, 14 Mar 2023 15:30:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231126AbjCNPaF (ORCPT ); Tue, 14 Mar 2023 11:30:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59608 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231611AbjCNP3L (ORCPT ); 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[83.9.29.16]) by smtp.gmail.com with ESMTPSA id 27-20020a2e165b000000b002986a977bf2sm491529ljw.90.2023.03.14.08.28.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Mar 2023 08:28:59 -0700 (PDT) From: Konrad Dybcio Date: Tue, 14 Mar 2023 16:28:44 +0100 Subject: [PATCH v4 13/14] drm/msm/a6xx: Add A619_holi speedbin support MIME-Version: 1.0 Message-Id: <20230223-topic-gmuwrapper-v4-13-e987eb79d03f@linaro.org> References: <20230223-topic-gmuwrapper-v4-0-e987eb79d03f@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v4-0-e987eb79d03f@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1678807716; l=1972; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=YbHID1ebzUgv4FADFLbdTcRo/0BAqs1RT5mt5WqUfTo=; b=s3HhnOhKViZbWBYgyMxuzL4UDJa8iVASyV+mQYW3iO3PGPZl+eP/2Aeaw6ZMhwFz3SwSFoCG0y33 Q/Rx0heHCR/EvUr6sEUzL8fuAOHOSGF3DRC9eEc/4mROb2FGKAb7 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org A619_holi is implemented on at least two SoCs: SM4350 (holi) and SM6375 (blair). This is what seems to be a first occurrence of this happening, but it's easy to overcome by guarding the SoC-specific fuse values with of_machine_is_compatible(). Do just that to enable frequency limiting on these SoCs. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 71950a5fcc96..27b96a335039 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2148,6 +2148,34 @@ static u32 a618_get_speed_bin(u32 fuse) return UINT_MAX; } +static u32 a619_holi_get_speed_bin(u32 fuse) +{ + /* + * There are (at least) two SoCs implementing A619_holi: SM4350 (holi) + * and SM6375 (blair). Limit the fuse matching to the corresponding + * SoC to prevent bogus frequency setting (as improbable as it may be, + * given unexpected fuse values are.. unexpected! But still possible.) + */ + + if (fuse == 0) + return 0; + + if (of_machine_is_compatible("qcom,sm4350")) { + if (fuse == 138) + return 1; + else if (fuse == 92) + return 2; + } else if (of_machine_is_compatible("qcom,sm6375")) { + if (fuse == 190) + return 1; + else if (fuse == 177) + return 2; + } else + pr_warn("Unknown SoC implementing A619_holi!\n"); + + return UINT_MAX; +} + static u32 a619_get_speed_bin(u32 fuse) { if (fuse == 0) @@ -2207,6 +2235,9 @@ static u32 fuse_to_supp_hw(struct device *dev, struct adreno_gpu *adreno_gpu, u3 if (adreno_is_a618(adreno_gpu)) val = a618_get_speed_bin(fuse); + else if (adreno_is_a619_holi(adreno_gpu)) + val = a619_holi_get_speed_bin(fuse); + else if (adreno_is_a619(adreno_gpu)) val = a619_get_speed_bin(fuse);