From patchwork Wed Mar 15 06:23:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Siddharth Vadapalli X-Patchwork-Id: 664321 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D2496C61DA4 for ; Wed, 15 Mar 2023 06:23:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230511AbjCOGX2 (ORCPT ); Wed, 15 Mar 2023 02:23:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58602 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230494AbjCOGX1 (ORCPT ); Wed, 15 Mar 2023 02:23:27 -0400 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E93B25C9D9; Tue, 14 Mar 2023 23:23:25 -0700 (PDT) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 32F6NFfh090610; Wed, 15 Mar 2023 01:23:15 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1678861395; bh=eLo46IzbsOYCRryf+5dtB+lxf//RU+jJSuDqsVB1sH0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=hnBYD99WwvlIN/VRenk99jVy0jsHkSctMhHvgyp7jSUb4tg8gle3HNk00EJWQEG+7 xrUAEY7Z9F2JLbsynxKSPgo6XmmJq9xfmgsXc8Nd6l0nkOPdg0ezG/xbIF/jMGC9G1 TwdX//BrcTK5/VfdMQom33ZZdDX84xU1z2ymTeWI= Received: from DLEE102.ent.ti.com (dlee102.ent.ti.com [157.170.170.32]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 32F6NF7C105452 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 15 Mar 2023 01:23:15 -0500 Received: from DLEE105.ent.ti.com (157.170.170.35) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Wed, 15 Mar 2023 01:23:15 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Wed, 15 Mar 2023 01:23:15 -0500 Received: from uda0492258.dhcp.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 32F6N7bs024744; Wed, 15 Mar 2023 01:23:12 -0500 From: Siddharth Vadapalli To: , , , , , , CC: , , , , Subject: [PATCH v3 1/4] arm64: dts: ti: k3-j721e: Add CPSW9G nodes Date: Wed, 15 Mar 2023 11:53:04 +0530 Message-ID: <20230315062307.1612220-2-s-vadapalli@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230315062307.1612220-1-s-vadapalli@ti.com> References: <20230315062307.1612220-1-s-vadapalli@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org TI's J721E SoC has a 9 port Ethernet Switch instance with 8 external ports and 1 host port, referred to as CPSW9G. Add device-tree nodes for CPSW9G and disable it by default. Device-tree overlays will be used to enable it. Signed-off-by: Siddharth Vadapalli --- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 116 ++++++++++++++++++++++ arch/arm64/boot/dts/ti/k3-j721e.dtsi | 1 + 2 files changed, 117 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index c935622f0102..44f2833c5187 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -61,6 +61,13 @@ serdes_ln_ctrl: mux-controller@4080 { , ; }; + cpsw0_phy_gmii_sel: phy@4044 { + compatible = "ti,j721e-cpsw9g-phy-gmii-sel"; + ti,qsgmii-main-ports = <2>, <2>; + reg = <0x4044 0x20>; + #phy-cells = <1>; + }; + usb_serdes_mux: mux-controller@4000 { compatible = "mmio-mux"; #mux-control-cells = <1>; @@ -404,6 +411,115 @@ cpts@310d0000 { }; }; + cpsw0: ethernet@c000000 { + compatible = "ti,j721e-cpswxg-nuss"; + #address-cells = <2>; + #size-cells = <2>; + reg = <0x0 0xc000000 0x0 0x200000>; + reg-names = "cpsw_nuss"; + ranges = <0x0 0x0 0x0 0x0c000000 0x0 0x200000>; + clocks = <&k3_clks 19 89>; + clock-names = "fck"; + power-domains = <&k3_pds 19 TI_SCI_PD_EXCLUSIVE>; + + dmas = <&main_udmap 0xca00>, + <&main_udmap 0xca01>, + <&main_udmap 0xca02>, + <&main_udmap 0xca03>, + <&main_udmap 0xca04>, + <&main_udmap 0xca05>, + <&main_udmap 0xca06>, + <&main_udmap 0xca07>, + <&main_udmap 0x4a00>; + dma-names = "tx0", "tx1", "tx2", "tx3", + "tx4", "tx5", "tx6", "tx7", + "rx"; + + status = "disabled"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + cpsw0_port1: port@1 { + reg = <1>; + ti,mac-only; + label = "port1"; + status = "disabled"; + }; + + cpsw0_port2: port@2 { + reg = <2>; + ti,mac-only; + label = "port2"; + status = "disabled"; + }; + + cpsw0_port3: port@3 { + reg = <3>; + ti,mac-only; + label = "port3"; + status = "disabled"; + }; + + cpsw0_port4: port@4 { + reg = <4>; + ti,mac-only; + label = "port4"; + status = "disabled"; + }; + + cpsw0_port5: port@5 { + reg = <5>; + ti,mac-only; + label = "port5"; + status = "disabled"; + }; + + cpsw0_port6: port@6 { + reg = <6>; + ti,mac-only; + label = "port6"; + status = "disabled"; + }; + + cpsw0_port7: port@7 { + reg = <7>; + ti,mac-only; + label = "port7"; + status = "disabled"; + }; + + cpsw0_port8: port@8 { + reg = <8>; + ti,mac-only; + label = "port8"; + status = "disabled"; + }; + }; + + cpsw9g_mdio: mdio@f00 { + compatible = "ti,cpsw-mdio","ti,davinci_mdio"; + reg = <0x0 0xf00 0x0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&k3_clks 19 89>; + clock-names = "fck"; + bus_freq = <1000000>; + status = "disabled"; + }; + + cpts@3d000 { + compatible = "ti,j721e-cpts"; + reg = <0x0 0x3d000 0x0 0x400>; + clocks = <&k3_clks 19 16>; + clock-names = "cpts"; + interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cpts"; + ti,cpts-ext-ts-inputs = <4>; + ti,cpts-periodic-outputs = <2>; + }; + }; + main_crypto: crypto@4e00000 { compatible = "ti,j721e-sa2ul"; reg = <0x0 0x4e00000 0x0 0x1200>; diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi index 6975cae644d9..ddbaa06e21bd 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi @@ -135,6 +135,7 @@ cbass_main: bus@100000 { <0x00 0x06000000 0x00 0x06000000 0x00 0x00400000>, /* USBSS0 */ <0x00 0x06400000 0x00 0x06400000 0x00 0x00400000>, /* USBSS1 */ <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */ + <0x00 0x0c000000 0x00 0x0c000000 0x00 0x0d000000>, /* CPSW9G */ <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */ <0x00 0x0d000000 0x00 0x0d000000 0x00 0x01800000>, /* PCIe Core*/ <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01800000>, /* PCIe Core*/ From patchwork Wed Mar 15 06:23:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Siddharth Vadapalli X-Patchwork-Id: 663650 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9DB83C6FD1D for ; Wed, 15 Mar 2023 06:23:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230522AbjCOGXt (ORCPT ); Wed, 15 Mar 2023 02:23:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59152 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231297AbjCOGXj (ORCPT ); Wed, 15 Mar 2023 02:23:39 -0400 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 284A65CEC5; Tue, 14 Mar 2023 23:23:33 -0700 (PDT) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 32F6NJ17026505; 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Wed, 15 Mar 2023 01:23:19 -0500 Received: from uda0492258.dhcp.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 32F6N7bt024744; Wed, 15 Mar 2023 01:23:15 -0500 From: Siddharth Vadapalli To: , , , , , , CC: , , , , Subject: [PATCH v3 2/4] arm64: dts: ti: k3-j721e: Add overlay to enable CPSW9G ports in QSGMII mode Date: Wed, 15 Mar 2023 11:53:05 +0530 Message-ID: <20230315062307.1612220-3-s-vadapalli@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230315062307.1612220-1-s-vadapalli@ti.com> References: <20230315062307.1612220-1-s-vadapalli@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The J7 Quad Port Add-On Ethernet Card for J721E Common-Proc-Board supports QSGMII mode. Use the overlay to configure CPSW9G ports in QSGMII mode. Add support to reset the PHY from kernel by using gpio-hog and gpio-reset. Add aliases for CPSW9G ports to enable kernel to fetch MAC addresses directly from U-Boot. Signed-off-by: Siddharth Vadapalli --- arch/arm64/boot/dts/ti/Makefile | 3 +- .../ti/k3-j721e-evm-quad-port-eth-exp.dtso | 132 ++++++++++++++++++ 2 files changed, 134 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/ti/k3-j721e-evm-quad-port-eth-exp.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 6acd12409d59..7ded6dacd3f2 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -31,8 +31,9 @@ dtb-$(CONFIG_ARCH_K3) += k3-am654-base-board.dtb dtb-$(CONFIG_ARCH_K3) += k3-j7200-common-proc-board.dtb # Boards with J721e SoC +k3-j721e-evm-dtbs := k3-j721e-common-proc-board.dtb k3-j721e-evm-quad-port-eth-exp.dtbo dtb-$(CONFIG_ARCH_K3) += k3-j721e-beagleboneai64.dtb -dtb-$(CONFIG_ARCH_K3) += k3-j721e-common-proc-board.dtb +dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm.dtb dtb-$(CONFIG_ARCH_K3) += k3-j721e-sk.dtb # Boards with J721s2 SoC diff --git a/arch/arm64/boot/dts/ti/k3-j721e-evm-quad-port-eth-exp.dtso b/arch/arm64/boot/dts/ti/k3-j721e-evm-quad-port-eth-exp.dtso new file mode 100644 index 000000000000..0acdb59d789b --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j721e-evm-quad-port-eth-exp.dtso @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT Overlay for CPSW9G in QSGMII mode using J7 Quad Port ETH EXP Add-On Ethernet Card with + * J721E board. + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include + +&{/} { + aliases { + ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@1"; + ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@2"; + ethernet3 = "/bus@100000/ethernet@c000000/ethernet-ports/port@3"; + ethernet4 = "/bus@100000/ethernet@c000000/ethernet-ports/port@4"; + }; +}; + +&cpsw0 { + status = "okay"; +}; + +&cpsw0_port1 { + status = "okay"; + phy-handle = <&cpsw9g_phy0>; + phy-mode = "qsgmii"; + mac-address = [00 00 00 00 00 00]; + phys = <&cpsw0_phy_gmii_sel 1>; +}; + +&cpsw0_port2 { + status = "okay"; + phy-handle = <&cpsw9g_phy1>; + phy-mode = "qsgmii"; + mac-address = [00 00 00 00 00 00]; + phys = <&cpsw0_phy_gmii_sel 2>; +}; + +&cpsw0_port3 { + status = "okay"; + phy-handle = <&cpsw9g_phy2>; + phy-mode = "qsgmii"; + mac-address = [00 00 00 00 00 00]; + phys = <&cpsw0_phy_gmii_sel 3>; +}; + +&cpsw0_port4 { + status = "okay"; + phy-handle = <&cpsw9g_phy3>; + phy-mode = "qsgmii"; + mac-address = [00 00 00 00 00 00]; + phys = <&cpsw0_phy_gmii_sel 4>; +}; + +&cpsw9g_mdio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mdio0_pins_default>; + reset-gpios = <&exp2 17 GPIO_ACTIVE_LOW>; + reset-post-delay-us = <120000>; + #address-cells = <1>; + #size-cells = <0>; + + cpsw9g_phy0: ethernet-phy@17 { + reg = <17>; + }; + cpsw9g_phy1: ethernet-phy@16 { + reg = <16>; + }; + cpsw9g_phy2: ethernet-phy@18 { + reg = <18>; + }; + cpsw9g_phy3: ethernet-phy@19 { + reg = <19>; + }; +}; + +&exp2 { + qsgmii-line-hog { + gpio-hog; + gpios = <16 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "qsgmii-pwrdn-line"; + }; +}; + +&main_pmx0 { + mdio0_pins_default: mdio0-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x1bc, PIN_OUTPUT, 0) /* (V24) MDIO0_MDC */ + J721E_IOPAD(0x1b8, PIN_INPUT, 0) /* (V26) MDIO0_MDIO */ + >; + }; +}; + +&serdes_ln_ctrl { + idle-states = , , + , , + , , + , , + , , + , ; +}; + +&serdes_wiz0 { + status = "okay"; +}; + +&serdes0 { + status = "okay"; + + assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>, <&serdes0 CDNS_SIERRA_PLL_CMNLC1>; + assigned-clock-parents = <&wiz0_pll1_refclk>, <&wiz0_pll1_refclk>; + #address-cells = <1>; + #size-cells = <0>; + + serdes0_qsgmii_link: phy@1 { + reg = <1>; + cdns,num-lanes = <1>; + #phy-cells = <0>; + cdns,phy-type = ; + resets = <&serdes_wiz0 2>; + }; +}; From patchwork Wed Mar 15 06:23:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Siddharth Vadapalli X-Patchwork-Id: 663651 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 99CCFC6FD1D for ; Wed, 15 Mar 2023 06:23:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231228AbjCOGXg (ORCPT ); Wed, 15 Mar 2023 02:23:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58890 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231126AbjCOGXd (ORCPT ); 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Wed, 15 Mar 2023 01:23:22 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Wed, 15 Mar 2023 01:23:22 -0500 Received: from uda0492258.dhcp.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 32F6N7bu024744; Wed, 15 Mar 2023 01:23:19 -0500 From: Siddharth Vadapalli To: , , , , , , CC: , , , , Subject: [PATCH v3 3/4] arm64: dts: ti: j7200-main: Add CPSW5G nodes Date: Wed, 15 Mar 2023 11:53:06 +0530 Message-ID: <20230315062307.1612220-4-s-vadapalli@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230315062307.1612220-1-s-vadapalli@ti.com> References: <20230315062307.1612220-1-s-vadapalli@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org TI's J7200 SoC has a 5 port Ethernet Switch instance with 4 external ports and 1 host port, referred to as CPSW5G. Add device-tree nodes for CPSW5G and disable it by default. Device-tree overlays will be used to enable it. Signed-off-by: Siddharth Vadapalli --- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 88 +++++++++++++++++++++++ 1 file changed, 88 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index 138381f43ce4..abad0cb441ad 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -39,6 +39,13 @@ serdes_ln_ctrl: mux-controller@4080 { <0x4088 0x3>, <0x408c 0x3>; /* SERDES0 lane2/3 select */ }; + cpsw0_phy_gmii_sel: phy@4044 { + compatible = "ti,j7200-cpsw5g-phy-gmii-sel"; + ti,qsgmii-main-ports = <1>; + reg = <0x4044 0x10>; + #phy-cells = <1>; + }; + usb_serdes_mux: mux-controller@4000 { compatible = "mmio-mux"; #mux-control-cells = <1>; @@ -304,6 +311,87 @@ cpts@310d0000 { }; }; + cpsw0: ethernet@c000000 { + compatible = "ti,j7200-cpswxg-nuss"; + #address-cells = <2>; + #size-cells = <2>; + reg = <0x00 0xc000000 0x00 0x200000>; + reg-names = "cpsw_nuss"; + ranges = <0x00 0x00 0x00 0xc000000 0x00 0x200000>; + clocks = <&k3_clks 19 33>; + clock-names = "fck"; + power-domains = <&k3_pds 19 TI_SCI_PD_EXCLUSIVE>; + + dmas = <&main_udmap 0xca00>, + <&main_udmap 0xca01>, + <&main_udmap 0xca02>, + <&main_udmap 0xca03>, + <&main_udmap 0xca04>, + <&main_udmap 0xca05>, + <&main_udmap 0xca06>, + <&main_udmap 0xca07>, + <&main_udmap 0x4a00>; + dma-names = "tx0", "tx1", "tx2", "tx3", + "tx4", "tx5", "tx6", "tx7", + "rx"; + + status = "disabled"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + cpsw0_port1: port@1 { + reg = <1>; + ti,mac-only; + label = "port1"; + status = "disabled"; + }; + + cpsw0_port2: port@2 { + reg = <2>; + ti,mac-only; + label = "port2"; + status = "disabled"; + }; + + cpsw0_port3: port@3 { + reg = <3>; + ti,mac-only; + label = "port3"; + status = "disabled"; + }; + + cpsw0_port4: port@4 { + reg = <4>; + ti,mac-only; + label = "port4"; + status = "disabled"; + }; + }; + + cpsw5g_mdio: mdio@f00 { + compatible = "ti,cpsw-mdio","ti,davinci_mdio"; + reg = <0x00 0xf00 0x00 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&k3_clks 19 33>; + clock-names = "fck"; + bus_freq = <1000000>; + status = "disabled"; + }; + + cpts@3d000 { + compatible = "ti,j721e-cpts"; + reg = <0x00 0x3d000 0x00 0x400>; + clocks = <&k3_clks 19 16>; + clock-names = "cpts"; + interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cpts"; + ti,cpts-ext-ts-inputs = <4>; + ti,cpts-periodic-outputs = <2>; + }; + }; + main_pmx0: pinctrl@11c000 { compatible = "pinctrl-single"; /* Proxy 0 addressing */ From patchwork Wed Mar 15 06:23:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Siddharth Vadapalli X-Patchwork-Id: 664320 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CFB94C7618D for ; Wed, 15 Mar 2023 06:23:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231204AbjCOGXi (ORCPT ); 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Wed, 15 Mar 2023 01:23:26 -0500 Received: from DFLE111.ent.ti.com (10.64.6.32) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Wed, 15 Mar 2023 01:23:25 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Wed, 15 Mar 2023 01:23:25 -0500 Received: from uda0492258.dhcp.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 32F6N7bv024744; Wed, 15 Mar 2023 01:23:22 -0500 From: Siddharth Vadapalli To: , , , , , , CC: , , , , Subject: [PATCH v3 4/4] arm64: dts: ti: k3-j7200: Add overlay to enable CPSW5G ports in QSGMII mode Date: Wed, 15 Mar 2023 11:53:07 +0530 Message-ID: <20230315062307.1612220-5-s-vadapalli@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230315062307.1612220-1-s-vadapalli@ti.com> References: <20230315062307.1612220-1-s-vadapalli@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The J7 Quad Port Add-On Ethernet Card for J7200 Common-Proc-Board supports QSGMII mode. Use the overlay to configure CPSW5G ports in QSGMII mode. Add support to reset the PHY from kernel by using gpio-hog and gpio-reset. Add aliases for CPSW5G ports to enable kernel to fetch MAC addresses directly from U-Boot. Signed-off-by: Siddharth Vadapalli --- arch/arm64/boot/dts/ti/Makefile | 3 +- .../ti/k3-j7200-evm-quad-port-eth-exp.dtso | 100 ++++++++++++++++++ 2 files changed, 102 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/ti/k3-j7200-evm-quad-port-eth-exp.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 7ded6dacd3f2..5312e4adc4e3 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -28,7 +28,8 @@ dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced-pg2.dtb dtb-$(CONFIG_ARCH_K3) += k3-am654-base-board.dtb # Boards with J7200 SoC -dtb-$(CONFIG_ARCH_K3) += k3-j7200-common-proc-board.dtb +k3-j7200-evm-dtbs := k3-j7200-common-proc-board.dtb k3-j7200-evm-quad-port-eth-exp.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-j7200-evm.dtb # Boards with J721e SoC k3-j721e-evm-dtbs := k3-j721e-common-proc-board.dtb k3-j721e-evm-quad-port-eth-exp.dtbo diff --git a/arch/arm64/boot/dts/ti/k3-j7200-evm-quad-port-eth-exp.dtso b/arch/arm64/boot/dts/ti/k3-j7200-evm-quad-port-eth-exp.dtso new file mode 100644 index 000000000000..78ba7bcedf3f --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j7200-evm-quad-port-eth-exp.dtso @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT Overlay for CPSW5G in QSGMII mode using J7 Quad Port ETH EXP Add-On Ethernet Card with + * J7200 board. + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include + +&{/} { + aliases { + ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@1"; + ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@2"; + ethernet3 = "/bus@100000/ethernet@c000000/ethernet-ports/port@3"; + ethernet4 = "/bus@100000/ethernet@c000000/ethernet-ports/port@4"; + }; +}; + +&cpsw0 { + status = "okay"; +}; + +&cpsw0_port1 { + status = "okay"; + phy-handle = <&cpsw5g_phy0>; + phy-mode = "qsgmii"; + mac-address = [00 00 00 00 00 00]; + phys = <&cpsw0_phy_gmii_sel 1>; +}; + +&cpsw0_port2 { + status = "okay"; + phy-handle = <&cpsw5g_phy1>; + phy-mode = "qsgmii"; + mac-address = [00 00 00 00 00 00]; + phys = <&cpsw0_phy_gmii_sel 2>; +}; + +&cpsw0_port3 { + status = "okay"; + phy-handle = <&cpsw5g_phy2>; + phy-mode = "qsgmii"; + mac-address = [00 00 00 00 00 00]; + phys = <&cpsw0_phy_gmii_sel 3>; +}; + +&cpsw0_port4 { + status = "okay"; + phy-handle = <&cpsw5g_phy3>; + phy-mode = "qsgmii"; + mac-address = [00 00 00 00 00 00]; + phys = <&cpsw0_phy_gmii_sel 4>; +}; + +&cpsw5g_mdio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mdio0_pins_default>; + reset-gpios = <&exp2 17 GPIO_ACTIVE_LOW>; + reset-post-delay-us = <120000>; + #address-cells = <1>; + #size-cells = <0>; + + cpsw5g_phy0: ethernet-phy@16 { + reg = <16>; + }; + cpsw5g_phy1: ethernet-phy@17 { + reg = <17>; + }; + cpsw5g_phy2: ethernet-phy@18 { + reg = <18>; + }; + cpsw5g_phy3: ethernet-phy@19 { + reg = <19>; + }; +}; + +&exp2 { + qsgmii-line-hog { + gpio-hog; + gpios = <16 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "qsgmii-pwrdn-line"; + }; +}; + +&main_pmx0 { + mdio0_pins_default: mdio0-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x00a8, PIN_OUTPUT, 5) /* (W19) UART8_TXD.MDIO0_MDC */ + J721E_IOPAD(0x00a4, PIN_INPUT, 5) /* (W14) UART8_RXD.MDIO0_MDIO */ + >; + }; +};