From patchwork Wed Mar 15 07:28:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jacky Huang X-Patchwork-Id: 663639 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D0B5CC6FD1D for ; Wed, 15 Mar 2023 07:30:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231667AbjCOHa2 (ORCPT ); Wed, 15 Mar 2023 03:30:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38432 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231772AbjCOH36 (ORCPT ); Wed, 15 Mar 2023 03:29:58 -0400 Received: from mail-pj1-x102b.google.com (mail-pj1-x102b.google.com [IPv6:2607:f8b0:4864:20::102b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B39E76C690; Wed, 15 Mar 2023 00:29:11 -0700 (PDT) Received: by mail-pj1-x102b.google.com with SMTP id nn12so17846624pjb.5; Wed, 15 Mar 2023 00:29:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1678865351; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Ed17VsKqIYY1EHY3aBloZZET84zjPJ3dZSJioIcN9l0=; b=jCejio4JOFaEEdujj2UtxzkEnwWmbwdk4jb7/APQfQbPL7rfxOy4DfJrcSAHA4gSuw Ux7tgN+9bErK7Pe2KwoqNcZhxLHx6MG7MS97cnHTuIV5UZO3csvYS1aaPaGzntKQn3jL 40M0KAMMYQNOk1VZkNwUXNy6EF4gTgAQJsfurqyMxrN9SU3YaoTJXO6/TkY4GekXXrVH W0oluaacMemPG4fiEfsDvdv6pCpaKhYuq2OpP9/lN5VhTOWvXFPt7xAby8uu80Wv8Vpl GdWHojEfPr9CBIuy5CuXmZn0+2awb9Mq1meIV8IqrrNtFWDUu5HxmSswFRfmyGPKrQ4I sZ7g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678865351; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Ed17VsKqIYY1EHY3aBloZZET84zjPJ3dZSJioIcN9l0=; b=sdMT2DRDj794tAUfuXRRwWOsyebI0r4zlXI4Ep4Y6Ff+fW2iSErN2eJWXYikopCU6t JkRo8AApNs4yToFAUn2SjZSy/jiUR1os60Fgy8Ot6Ci1ZZ009LRJQs3lkByXa/+YRa9j THiUiIpDUZncn8j/IqP9OCXmv1Uzeza5/4bGcfIMRzDf5sGCxurfSs8lLpAUGR+HRfyu 8YaU0n+GunkqWz0hcsUZhGYqe2gHw9ae7oPIaKGTustycBFd6Q1zqrRRnUG67sUDLjc7 YudLJPZ+wVZ29RR/DnLRSbLxybVEE+Whl/rDDSkuU73qRWAoH3jFSBKoL8JeMMWIqa+X QQrg== X-Gm-Message-State: AO0yUKX9aRQktQPBo9fr8UHSzII29EfWC3urexifMHhW02g7kGo49hpA vw/Qe9dJcmY4wlXc2wH0uvA= X-Google-Smtp-Source: AK7set9KTk8ds9IJJR2XfY2NSP8RNVnPplOwDXkJJflpiW1QbzAegPBDrWjapjJZ8dsePZeKiNH6iQ== X-Received: by 2002:a17:902:d2d1:b0:19a:a520:b203 with SMTP id n17-20020a170902d2d100b0019aa520b203mr1677475plc.25.1678865351189; Wed, 15 Mar 2023 00:29:11 -0700 (PDT) Received: from a28aa0606c51.. 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[60.250.192.107]) by smtp.gmail.com with ESMTPSA id kz11-20020a170902f9cb00b001a0667822c8sm2740003plb.94.2023.03.15.00.29.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Mar 2023 00:29:10 -0700 (PDT) From: Jacky Huang To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, gregkh@linuxfoundation.org, jirislaby@kernel.org Cc: devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, schung@nuvoton.com, Jacky Huang Subject: [PATCH 01/15] arm64: Kconfig.platforms: Add config for Nuvoton MA35 platform Date: Wed, 15 Mar 2023 07:28:48 +0000 Message-Id: <20230315072902.9298-2-ychuang570808@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230315072902.9298-1-ychuang570808@gmail.com> References: <20230315072902.9298-1-ychuang570808@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Jacky Huang Add ARCH_NUVOTON configuration option for Nuvoton MA35 family SoCs. Signed-off-by: Jacky Huang --- arch/arm64/Kconfig.platforms | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 89a0b13b058d..c1f277c05569 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -236,6 +236,15 @@ config ARCH_NPCM General support for NPCM8xx BMC (Arbel). Nuvoton NPCM8xx BMC based on the Cortex A35. +config ARCH_NUVOTON + bool "Nuvoton MA35 Platforms" + select GPIOLIB + select PINCTRL + select RESET_CONTROLLER + help + This enables support for the ARMv8 based Nuvoton SoCs such + as MA35D1. + config ARCH_QCOM bool "Qualcomm Platforms" select GPIOLIB From patchwork Wed Mar 15 07:28:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jacky Huang X-Patchwork-Id: 663638 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 970E9C6FD1D for ; Wed, 15 Mar 2023 07:30:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231706AbjCOHan (ORCPT ); Wed, 15 Mar 2023 03:30:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39790 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231788AbjCOHaB (ORCPT ); Wed, 15 Mar 2023 03:30:01 -0400 Received: from mail-pl1-x634.google.com (mail-pl1-x634.google.com [IPv6:2607:f8b0:4864:20::634]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3A0BA6C19D; Wed, 15 Mar 2023 00:29:14 -0700 (PDT) Received: by mail-pl1-x634.google.com with SMTP id v21so8986333ple.9; Wed, 15 Mar 2023 00:29:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1678865353; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=skDrdHHxY4/PRNsG0BtA3PR+oADTeYv6w75S5aIGD+k=; b=ncX2cNjBBArloPVBvUzdqBSEYyE6q/RBxhKEBvLcOGoyzywiNysSunaU/OKu8S+zVG WJHnZNjf/npJfFzyniqVTE0/a1I5oVzxyTbHfzPBbihQrPqpmj6BkzoEmfQnFp1DIb4L ECR6fWzulpN+k1wQRBcvsx9Zh9RlS7q0vzi7jE3P5rOStskcjh/b1hSpeMRJUu/aQFi6 Kn+2HGlQglBJzN9Znoi0SI208RUeNBkZ3zTo/e2DH93ow7HirepCuW01sebh/NXx1cVq miTThLyV969evfDME579tdtogEZhgMpAgSD6wyWhfREWjf9YSgCw2GQ+aDk8ndRcST3D lTrw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678865353; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=skDrdHHxY4/PRNsG0BtA3PR+oADTeYv6w75S5aIGD+k=; b=agyfEPVS8wvmjES0I5jjGsUSIv+JPrOKd5xQ9qvKQ5zaL8yLYb0plr3jVlqzfsHJfQ 42BBLbobwH+UOF3z3rHPlP8cPPl7/UOyn3sPZlJ9gVLiWLeq8Xe22zJcsPv28iYOIkA7 IenaGJXnhIYeyLW0M7QwQ+AMXiHlyHvOJy9rPFJlx5sPVCFMYBp08wexV4HhQMVu9cM1 9fNGZlSRz/bJs0rUr4duAGa2fLuIcHlPOjcT1nVY7UvJeuV64TaI79glE9Q2GUD1o4wB OK3QZt4In4rNoGmmfm6CWYayh/VKHl4eoGKsM1nZPtDYCn8No+z/VwnS8zPS6pEYtDuI 8YEw== X-Gm-Message-State: AO0yUKXib2l+8Tp+RSIDXiawp6kioxK+3Uzvv5VeQYxZ+anO/NiSrmmb nDSeBRbrfx9lDf5rOt5BiVg= X-Google-Smtp-Source: AK7set9hHttrvRDC5H+g6AdgKuIgXIrQQYDTQpVx8MLNrRRywrLCA11rZ7KFHpOen4NeVzub6jLetw== X-Received: by 2002:a17:903:2846:b0:19c:e05a:ea6 with SMTP id kq6-20020a170903284600b0019ce05a0ea6mr1270462plb.56.1678865353712; Wed, 15 Mar 2023 00:29:13 -0700 (PDT) Received: from a28aa0606c51.. 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[60.250.192.107]) by smtp.gmail.com with ESMTPSA id kz11-20020a170902f9cb00b001a0667822c8sm2740003plb.94.2023.03.15.00.29.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Mar 2023 00:29:13 -0700 (PDT) From: Jacky Huang To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, gregkh@linuxfoundation.org, jirislaby@kernel.org Cc: devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, schung@nuvoton.com, Jacky Huang Subject: [PATCH 02/15] arm64: defconfig: Add Nuvoton MA35 family support Date: Wed, 15 Mar 2023 07:28:49 +0000 Message-Id: <20230315072902.9298-3-ychuang570808@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230315072902.9298-1-ychuang570808@gmail.com> References: <20230315072902.9298-1-ychuang570808@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Jacky Huang Enable basic drivers for ma35d1 booting up support: architecture, device tree, clock, reset, and uart. Signed-off-by: Jacky Huang --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 7790ee42c68a..c96189acb02c 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -53,6 +53,7 @@ CONFIG_ARCH_LAYERSCAPE=y CONFIG_ARCH_MXC=y CONFIG_ARCH_S32=y CONFIG_ARCH_NPCM=y +CONFIG_ARCH_NUVOTON=y CONFIG_ARCH_QCOM=y CONFIG_ARCH_RENESAS=y CONFIG_ARCH_ROCKCHIP=y From patchwork Wed Mar 15 07:28:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jacky Huang X-Patchwork-Id: 664307 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C1395C7618B for ; Wed, 15 Mar 2023 07:30:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231578AbjCOHa4 (ORCPT ); Wed, 15 Mar 2023 03:30:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37686 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230356AbjCOHaM (ORCPT ); Wed, 15 Mar 2023 03:30:12 -0400 Received: from mail-pj1-x1030.google.com (mail-pj1-x1030.google.com [IPv6:2607:f8b0:4864:20::1030]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E72616E690; Wed, 15 Mar 2023 00:29:17 -0700 (PDT) Received: by mail-pj1-x1030.google.com with SMTP id y15-20020a17090aa40f00b00237ad8ee3a0so962344pjp.2; Wed, 15 Mar 2023 00:29:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1678865356; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Kl1DmN2IDzWs6eE+G64vJDwMqsz/I4iopBdZT5NNSQk=; b=k9G2DOVgQ6pm6s12Sc1/HZa8/62vAaV6qqudCSXDRREVCyfMc39C3P26gZ0Nwu58+Y 7f2OzgOcs5PBcGbnvLxEi6k/EpK2JySxCKu/cC6Xs5eQhTMDUdqZoO8VWUIIkm17/Hec /+UEGOstnJM4TMbhgO3FoVhKKIiyWLA8l9jpYuC8tIzJb6eNsb6H5pO4QSnTi69PTKbq UEmVqxjThbTB1iG4V+lm4YdVPx6f+1wA4Hz5io6tAM/kYO5pl5dx7ZY7Fh+sX7/h0AI5 TnVeXm9TSPdrlnd1TgIzpGz+SpH47XCoitUX4aZad0XxIr51aSXuBEgDoq0sDhUJy6Xq Tn/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678865356; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Kl1DmN2IDzWs6eE+G64vJDwMqsz/I4iopBdZT5NNSQk=; b=5MyU9HzcSwb4uglsvEF1KX79qc5prvhDPfaLpSnJrFwxRkOufb6PKHr281PkxAv2QZ ZSMUcGNE7raeF5KGLiPs/hbIIlPwIowvzmijuWj66LeHy2hXzc36Sy1WZD89oVnNLeqt Qx/SoId8cPxyaVmhEqofmqQDTfiE21RjAZX6qainoeBGGolmAEZlolzVDKBdg53wRdZw LhAi0TU1hswV3evIsPRmoAaotYRXMgu9haZ3zksAyQPLxrCqrYf2KpQHIPha8nCRQ8Zp TBe87RTNcVmZErLHwvBp5iOBB/jRJ42RQAcTZCMmTRZt0VcDJ6/+NVkh+SwylG+NPVNz BjNA== X-Gm-Message-State: AO0yUKWvHoznhteQRnjfg01nZt/Rvq/g8gdAla5LPXi/yl4p0YG2zu6i hkBYKfGAx7kA+A1GOZkSgMg= X-Google-Smtp-Source: AK7set+N2OdtBNiqA1cKw3xxFr3aoK82s/uM1P8fD/ClXlB4B5hYwjCJO2ilP8o7HFBr+3w1L63yIw== X-Received: by 2002:a17:902:c60a:b0:19c:be09:20d5 with SMTP id r10-20020a170902c60a00b0019cbe0920d5mr1565510plr.11.1678865356329; Wed, 15 Mar 2023 00:29:16 -0700 (PDT) Received: from a28aa0606c51.. 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[60.250.192.107]) by smtp.gmail.com with ESMTPSA id kz11-20020a170902f9cb00b001a0667822c8sm2740003plb.94.2023.03.15.00.29.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Mar 2023 00:29:16 -0700 (PDT) From: Jacky Huang To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, gregkh@linuxfoundation.org, jirislaby@kernel.org Cc: devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, schung@nuvoton.com, Jacky Huang Subject: [PATCH 03/15] mfd: Add the header file of Nuvoton ma35d1 system manager Date: Wed, 15 Mar 2023 07:28:50 +0000 Message-Id: <20230315072902.9298-4-ychuang570808@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230315072902.9298-1-ychuang570808@gmail.com> References: <20230315072902.9298-1-ychuang570808@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Jacky Huang The system manager is a set of registers used for power control, multi-function pin control, USB phy control, IP reset, and other miscellaneous controls. It also contains some registers that provide SoC information and status. Signed-off-by: Jacky Huang --- include/linux/mfd/ma35d1-sys.h | 95 ++++++++++++++++++++++++++++++++++ 1 file changed, 95 insertions(+) create mode 100644 include/linux/mfd/ma35d1-sys.h diff --git a/include/linux/mfd/ma35d1-sys.h b/include/linux/mfd/ma35d1-sys.h new file mode 100644 index 000000000000..dcd85231125d --- /dev/null +++ b/include/linux/mfd/ma35d1-sys.h @@ -0,0 +1,95 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Nuvoton Technologies. + * Author: Chi-Fen Li + * + * System management control registers of MA35D1 SoC + */ +#ifndef __LINUX_MFD_MA35D1_SYS_H +#define __LINUX_MFD_MA35D1_SYS_H + +#define REG_SYS_PDID (0x000) /* Product and Device Identifier */ +#define REG_SYS_PWRONOTP (0x004) /* Power-on Setting OTP Source */ +#define REG_SYS_PWRONPIN (0x008) /* Power-on Setting Pin Source */ +#define REG_SYS_RSTSTS (0x010) /* Reset Source Active Status */ +#define REG_SYS_MISCRFCR (0x014) /* Miscellaneous Reset Function */ +#define REG_SYS_RSTDEBCTL (0x018) /* Reset Pin De-bounce Control */ +#define REG_SYS_LVRDCR (0x01C) /* Low Voltage Reset & Detect */ +#define REG_SYS_IPRST0 (0x020) /* Reset Control Register 0 */ +#define REG_SYS_IPRST1 (0x024) /* Reset Control Register 1 */ +#define REG_SYS_IPRST2 (0x028) /* Reset Control Register 2 */ +#define REG_SYS_IPRST3 (0x02C) /* Reset Control Register 3 */ +#define REG_SYS_PMUCR (0x030) /* Power Management Unit Control */ +#define REG_SYS_DDRCQCSR (0x034) /* DDR Q Channel Control and Status */ +#define REG_SYS_PMUIEN (0x038) /* PMU Interrupt Enable */ +#define REG_SYS_PMUSTS (0x03C) /* PMU Status */ +#define REG_SYS_CA35WRBADR1 (0x040) /* A35 Core 1 Warm-boot Address */ +#define REG_SYS_CA35WRBPAR1 (0x044) /* A35 Core 1 Warm-boot Parameter */ +#define REG_SYS_CA35WRBADR2 (0x048) /* A35 Core 2 Warm-boot Address */ +#define REG_SYS_CA35WRBPAR2 (0x04C) /* A35 Core 2 Warm-boot Parameter */ +#define REG_SYS_USBPMISCR (0x060) /* USB PHY Miscellaneous Control */ +#define REG_SYS_USBP0PCR (0x064) /* USB Port 0 PHY Control */ +#define REG_SYS_USBP1PCR (0x068) /* USB Port 1 PHY Control */ +#define REG_SYS_MISCFCR0 (0x070) /* Miscellaneous Function Control 0 */ +#define REG_SYS_MISCFCR1 (0x074) /* Miscellaneous Function Control 1 */ +#define REG_SYS_MISCIER (0x078) /* Miscellaneous Interrupt Enable */ +#define REG_SYS_MISCISR (0x07C) /* Miscellaneous Interrupt Status */ +#define REG_SYS_GPA_MFPL (0x080) /* GPIOA Multi-Function Control LSB */ +#define REG_SYS_GPA_MFPH (0x084) /* GPIOA Multi-Function Control MSB */ +#define REG_SYS_GPB_MFPL (0x088) /* GPIOB Multi-Function Control LSB */ +#define REG_SYS_GPB_MFPH (0x08C) /* GPIOB Multi-Function Control MSB */ +#define REG_SYS_GPC_MFPL (0x090) /* GPIOC Multi-Function Control LSB */ +#define REG_SYS_GPC_MFPH (0x094) /* GPIOC Multi-Function Control MSB */ +#define REG_SYS_GPD_MFPL (0x098) /* GPIOD Multi-Function Control LSB */ +#define REG_SYS_GPD_MFPH (0x09C) /* GPIOD Multi-Function Control MSB */ +#define REG_SYS_GPE_MFPL (0x0A0) /* GPIOE Multi-Function Control LSB */ +#define REG_SYS_GPE_MFPH (0x0A4) /* GPIOE Multi-Function Control MSB */ +#define REG_SYS_GPF_MFPL (0x0A8) /* GPIOF Multi-Function Control LSB */ +#define REG_SYS_GPF_MFPH (0x0AC) /* GPIOF Multi-Function Control MSB */ +#define REG_SYS_GPG_MFPL (0x0B0) /* GPIOG Multi-Function Control LSB */ +#define REG_SYS_GPG_MFPH (0x0B4) /* GPIOG Multi-Function Control MSB */ +#define REG_SYS_GPH_MFPL (0x0B8) /* GPIOH Multi-Function Control LSB */ +#define REG_SYS_GPH_MFPH (0x0BC) /* GPIOH Multi-Function Control MSB */ +#define REG_SYS_GPI_MFPL (0x0C0) /* GPIOI Multi-Function Control LSB */ +#define REG_SYS_GPI_MFPH (0x0C4) /* GPIOI Multi-Function Control MSB */ +#define REG_SYS_GPJ_MFPL (0x0C8) /* GPIOJ Multi-Function Control LSB */ +#define REG_SYS_GPJ_MFPH (0x0CC) /* GPIOJ Multi-Function Control MSB */ +#define REG_SYS_GPK_MFPL (0x0D0) /* GPIOK Multi-Function Control LSB */ +#define REG_SYS_GPK_MFPH (0x0D4) /* GPIOK Multi-Function Control MSB */ +#define REG_SYS_GPL_MFPL (0x0D8) /* GPIOL Multi-Function Control LSB */ +#define REG_SYS_GPL_MFPH (0x0DC) /* GPIOL Multi-Function Control MSB */ +#define REG_SYS_GPM_MFPL (0x0E0) /* GPIOM Multi-Function Control LSB */ +#define REG_SYS_GPM_MFPH (0x0E4) /* GPIOM Multi-Function Control MSB */ +#define REG_SYS_GPN_MFPL (0x0E8) /* GPION Multi-Function Control LSB */ +#define REG_SYS_GPN_MFPH (0x0EC) /* GPION Multi-Function Control MSB */ +#define REG_SYS_HIRCFTRIM (0x100) /* HIRC Frequency Trim Value */ +#define REG_SYS_TSENSRFCR (0x104) /* Temperature Sensor Control */ +#define REG_SYS_GMAC0MISCR (0x108) /* GMAC 0 Miscellaneous Control */ +#define REG_SYS_GMAC1MISCR (0x10C) /* GMAC 1 Miscellaneous Control */ +#define REG_SYS_MACAD0LSR (0x110) /* MAC Address 0 LSW */ +#define REG_SYS_MACAD0HSR (0x114) /* MAC Address 0 HSW */ +#define REG_SYS_MACAD1LSR (0x118) /* MAC Address 1 LSW */ +#define REG_SYS_MACAD1HSR (0x11C) /* MAC Address 1 HSW */ +#define REG_SYS_CSDBGCTL (0x120) /* CoreSight Debug Control */ +#define REG_SYS_GPAB_MFOS (0x140) /* GPIOA/B Output Mode Select */ +#define REG_SYS_GPCD_MFOS (0x144) /* GPIOC/D Output Mode Select */ +#define REG_SYS_GPEF_MFOS (0x148) /* GPIOE/F Output Mode Select */ +#define REG_SYS_GPGH_MFOS (0x14C) /* GPIOG/H Output Mode Select */ +#define REG_SYS_GPIJ_MFOS (0x150) /* GPIOI/J Output Mode Select */ +#define REG_SYS_GPKL_MFOS (0x154) /* GPIOK/L Output Mode Select */ +#define REG_SYS_GPMN_MFOS (0x158) /* GPIOM/N Output Mode Select */ +#define REG_SYS_UID0 (0x180) /* Unique Identifier Word 0 */ +#define REG_SYS_UID1 (0x184) /* Unique Identifier Word 1 */ +#define REG_SYS_UID2 (0x188) /* Unique Identifier Word 2 */ +#define REG_SYS_UCID0 (0x190) /* Unique Customer Identifier 0 */ +#define REG_SYS_UCID1 (0x194) /* Unique Customer Identifier 1 */ +#define REG_SYS_UCID2 (0x198) /* Unique Customer Identifier 2 */ +#define REG_SYS_RLKTZS (0x1A0) /* TZS Register Lock Control */ +#define REG_SYS_RLKTZNS (0x1A4) /* TZNS Register Lock Control */ +#define REG_SYS_RLKSUBM (0x1A8) /* SubM Register Lock Control */ +#define REG_SYS_DPLPASWD (0x1B0) /* Deployed Password */ + +void ma35d1_reg_lock(void); +void ma35d1_reg_unlock(void); + +#endif /* __LINUX_MFD_MA35D1_SYS_H */ From patchwork Wed Mar 15 07:28:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jacky Huang X-Patchwork-Id: 663637 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 370D1C76195 for ; Wed, 15 Mar 2023 07:31:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231731AbjCOHa6 (ORCPT ); Wed, 15 Mar 2023 03:30:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38228 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id 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[60.250.192.107]) by smtp.gmail.com with ESMTPSA id kz11-20020a170902f9cb00b001a0667822c8sm2740003plb.94.2023.03.15.00.29.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Mar 2023 00:29:18 -0700 (PDT) From: Jacky Huang To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, gregkh@linuxfoundation.org, jirislaby@kernel.org Cc: devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, schung@nuvoton.com, Jacky Huang Subject: [PATCH 04/15] dt-bindings: clock: nuvoton: add binding for ma35d1 clock controller Date: Wed, 15 Mar 2023 07:28:51 +0000 Message-Id: <20230315072902.9298-5-ychuang570808@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230315072902.9298-1-ychuang570808@gmail.com> References: <20230315072902.9298-1-ychuang570808@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Jacky Huang Add the dt-bindings header for Nuvoton ma35d1, that gets shared between the clock controller and clock references in the dts. Signed-off-by: Jacky Huang --- .../dt-bindings/clock/nuvoton,ma35d1-clk.h | 253 ++++++++++++++++++ 1 file changed, 253 insertions(+) create mode 100644 include/dt-bindings/clock/nuvoton,ma35d1-clk.h diff --git a/include/dt-bindings/clock/nuvoton,ma35d1-clk.h b/include/dt-bindings/clock/nuvoton,ma35d1-clk.h new file mode 100644 index 000000000000..6c569fdd6e06 --- /dev/null +++ b/include/dt-bindings/clock/nuvoton,ma35d1-clk.h @@ -0,0 +1,253 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Nuvoton Technologies. + */ + +#ifndef __DT_BINDINGS_CLOCK_NUVOTON_MA35D1_CLK_H +#define __DT_BINDINGS_CLOCK_NUVOTON_MA35D1_CLK_H + +/* external and internal oscillator clocks */ +#define HXT 0 +#define HXT_GATE 1 +#define LXT 2 +#define LXT_GATE 3 +#define HIRC 4 +#define HIRC_GATE 5 +#define LIRC 6 +#define LIRC_GATE 7 +/* PLLs */ +#define CAPLL 8 +#define SYSPLL 9 +#define DDRPLL 10 +#define APLL 11 +#define EPLL 12 +#define VPLL 13 +/* EPLL divider */ +#define EPLL_DIV2 14 +#define EPLL_DIV4 15 +#define EPLL_DIV8 16 +/* CPU clock, system clock, AXI, HCLK and PCLK */ +#define CA35CLK_MUX 17 +#define AXICLK_DIV2 18 +#define AXICLK_DIV4 19 +#define AXICLK_MUX 20 +#define SYSCLK0_MUX 21 +#define SYSCLK1_MUX 22 +#define SYSCLK1_DIV2 23 +#define HCLK0 24 +#define HCLK1 25 +#define HCLK2 26 +#define PCLK0 27 +#define PCLK1 28 +#define PCLK2 29 +#define HCLK3 30 +#define PCLK3 31 +#define PCLK4 32 +/* AXI and AHB peripheral clocks */ +#define USBPHY0 33 +#define USBPHY1 34 +#define DDR0_GATE 35 +#define DDR6_GATE 36 +#define CAN0_MUX 37 +#define CAN0_DIV 38 +#define CAN0_GATE 39 +#define CAN1_MUX 40 +#define CAN1_DIV 41 +#define CAN1_GATE 42 +#define CAN2_MUX 43 +#define CAN2_DIV 44 +#define CAN2_GATE 45 +#define CAN3_MUX 46 +#define CAN3_DIV 47 +#define CAN3_GATE 48 +#define SDH0_MUX 49 +#define SDH0_GATE 50 +#define SDH1_MUX 51 +#define SDH1_GATE 52 +#define NAND_GATE 53 +#define USBD_GATE 54 +#define USBH_GATE 55 +#define HUSBH0_GATE 56 +#define HUSBH1_GATE 57 +#define GFX_MUX 58 +#define GFX_GATE 59 +#define VC8K_GATE 60 +#define DCU_MUX 61 +#define DCU_GATE 62 +#define DCUP_DIV 63 +#define EMAC0_GATE 64 +#define EMAC1_GATE 65 +#define CCAP0_MUX 66 +#define CCAP0_DIV 67 +#define CCAP0_GATE 68 +#define CCAP1_MUX 69 +#define CCAP1_DIV 70 +#define CCAP1_GATE 71 +#define PDMA0_GATE 72 +#define PDMA1_GATE 73 +#define PDMA2_GATE 74 +#define PDMA3_GATE 75 +#define WH0_GATE 76 +#define WH1_GATE 77 +#define HWS_GATE 78 +#define EBI_GATE 79 +#define SRAM0_GATE 80 +#define SRAM1_GATE 81 +#define ROM_GATE 82 +#define TRA_GATE 83 +#define DBG_MUX 84 +#define DBG_GATE 85 +#define CKO_MUX 86 +#define CKO_DIV 87 +#define CKO_GATE 88 +#define GTMR_GATE 89 +#define GPA_GATE 90 +#define GPB_GATE 91 +#define GPC_GATE 92 +#define GPD_GATE 93 +#define GPE_GATE 94 +#define GPF_GATE 95 +#define GPG_GATE 96 +#define GPH_GATE 97 +#define GPI_GATE 98 +#define GPJ_GATE 99 +#define GPK_GATE 100 +#define GPL_GATE 101 +#define GPM_GATE 102 +#define GPN_GATE 103 +/* APB peripheral clocks */ +#define TMR0_MUX 104 +#define TMR0_GATE 105 +#define TMR1_MUX 106 +#define TMR1_GATE 107 +#define TMR2_MUX 108 +#define TMR2_GATE 109 +#define TMR3_MUX 110 +#define TMR3_GATE 111 +#define TMR4_MUX 112 +#define TMR4_GATE 113 +#define TMR5_MUX 114 +#define TMR5_GATE 115 +#define TMR6_MUX 116 +#define TMR6_GATE 117 +#define TMR7_MUX 118 +#define TMR7_GATE 119 +#define TMR8_MUX 120 +#define TMR8_GATE 121 +#define TMR9_MUX 122 +#define TMR9_GATE 123 +#define TMR10_MUX 124 +#define TMR10_GATE 125 +#define TMR11_MUX 126 +#define TMR11_GATE 127 +#define UART0_MUX 128 +#define UART0_DIV 129 +#define UART0_GATE 130 +#define UART1_MUX 131 +#define UART1_DIV 132 +#define UART1_GATE 133 +#define UART2_MUX 134 +#define UART2_DIV 135 +#define UART2_GATE 136 +#define UART3_MUX 137 +#define UART3_DIV 138 +#define UART3_GATE 139 +#define UART4_MUX 140 +#define UART4_DIV 141 +#define UART4_GATE 142 +#define UART5_MUX 143 +#define UART5_DIV 144 +#define UART5_GATE 145 +#define UART6_MUX 146 +#define UART6_DIV 147 +#define UART6_GATE 148 +#define UART7_MUX 149 +#define UART7_DIV 150 +#define UART7_GATE 151 +#define UART8_MUX 152 +#define UART8_DIV 153 +#define UART8_GATE 154 +#define UART9_MUX 155 +#define UART9_DIV 156 +#define UART9_GATE 157 +#define UART10_MUX 158 +#define UART10_DIV 159 +#define UART10_GATE 160 +#define UART11_MUX 161 +#define UART11_DIV 162 +#define UART11_GATE 163 +#define UART12_MUX 164 +#define UART12_DIV 165 +#define UART12_GATE 166 +#define UART13_MUX 167 +#define UART13_DIV 168 +#define UART13_GATE 169 +#define UART14_MUX 170 +#define UART14_DIV 171 +#define UART14_GATE 172 +#define UART15_MUX 173 +#define UART15_DIV 174 +#define UART15_GATE 175 +#define UART16_MUX 176 +#define UART16_DIV 177 +#define UART16_GATE 178 +#define RTC_GATE 179 +#define DDR_GATE 180 +#define KPI_MUX 181 +#define KPI_DIV 182 +#define KPI_GATE 183 +#define I2C0_GATE 184 +#define I2C1_GATE 185 +#define I2C2_GATE 186 +#define I2C3_GATE 187 +#define I2C4_GATE 188 +#define I2C5_GATE 189 +#define QSPI0_MUX 190 +#define QSPI0_GATE 191 +#define QSPI1_MUX 192 +#define QSPI1_GATE 193 +#define SMC0_MUX 194 +#define SMC0_DIV 195 +#define SMC0_GATE 196 +#define SMC1_MUX 197 +#define SMC1_DIV 198 +#define SMC1_GATE 199 +#define WDT0_MUX 200 +#define WDT0_GATE 201 +#define WDT1_MUX 202 +#define WDT1_GATE 203 +#define WDT2_MUX 204 +#define WDT2_GATE 205 +#define WWDT0_MUX 206 +#define WWDT1_MUX 207 +#define WWDT2_MUX 208 +#define EPWM0_GATE 209 +#define EPWM1_GATE 210 +#define EPWM2_GATE 211 +#define I2S0_MUX 212 +#define I2S0_GATE 213 +#define I2S1_MUX 214 +#define I2S1_GATE 215 +#define SSMCC_GATE 216 +#define SSPCC_GATE 217 +#define SPI0_MUX 218 +#define SPI0_GATE 219 +#define SPI1_MUX 220 +#define SPI1_GATE 221 +#define SPI2_MUX 222 +#define SPI2_GATE 223 +#define SPI3_MUX 224 +#define SPI3_GATE 225 +#define ECAP0_GATE 226 +#define ECAP1_GATE 227 +#define ECAP2_GATE 228 +#define QEI0_GATE 229 +#define QEI1_GATE 230 +#define QEI2_GATE 231 +#define ADC_DIV 232 +#define ADC_GATE 233 +#define EADC_DIV 234 +#define EADC_GATE 235 +#define CLK_MAX_IDX 236 + +#endif /* __DT_BINDINGS_CLOCK_NUVOTON_MA35D1_CLK_H */ From patchwork Wed Mar 15 07:28:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jacky Huang X-Patchwork-Id: 664306 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BBD40C7618B for ; Wed, 15 Mar 2023 07:31:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231626AbjCOHbV (ORCPT ); Wed, 15 Mar 2023 03:31:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39450 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231428AbjCOHaU (ORCPT ); Wed, 15 Mar 2023 03:30:20 -0400 Received: from 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[60.250.192.107]) by smtp.gmail.com with ESMTPSA id kz11-20020a170902f9cb00b001a0667822c8sm2740003plb.94.2023.03.15.00.29.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Mar 2023 00:29:21 -0700 (PDT) From: Jacky Huang To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, gregkh@linuxfoundation.org, jirislaby@kernel.org Cc: devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, schung@nuvoton.com, Jacky Huang Subject: [PATCH 05/15] dt-bindings: reset: nuvoton: add binding for ma35d1 IP reset control Date: Wed, 15 Mar 2023 07:28:52 +0000 Message-Id: <20230315072902.9298-6-ychuang570808@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230315072902.9298-1-ychuang570808@gmail.com> References: <20230315072902.9298-1-ychuang570808@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Jacky Huang Add the dt-bindings header for Nuvoton ma35d1, that gets shared between the reset controller and reset references in the dts. Signed-off-by: Jacky Huang --- .../dt-bindings/reset/nuvoton,ma35d1-reset.h | 108 ++++++++++++++++++ 1 file changed, 108 insertions(+) create mode 100644 include/dt-bindings/reset/nuvoton,ma35d1-reset.h diff --git a/include/dt-bindings/reset/nuvoton,ma35d1-reset.h b/include/dt-bindings/reset/nuvoton,ma35d1-reset.h new file mode 100644 index 000000000000..6d0791b04d52 --- /dev/null +++ b/include/dt-bindings/reset/nuvoton,ma35d1-reset.h @@ -0,0 +1,108 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Nuvoton Technologies. + * Author: Chi-Fen Li + * + * Device Tree binding constants for MA35D1 reset controller. + */ + +#ifndef __DT_BINDINGS_RESET_MA35D1_H +#define __DT_BINDINGS_RESET_MA35D1_H + +#define MA35D1_RESET_CHIP 0 +#define MA35D1_RESET_CA35CR0 1 +#define MA35D1_RESET_CA35CR1 2 +#define MA35D1_RESET_CM4 3 +#define MA35D1_RESET_PDMA0 4 +#define MA35D1_RESET_PDMA1 5 +#define MA35D1_RESET_PDMA2 6 +#define MA35D1_RESET_PDMA3 7 +#define MA35D1_RESET_DISP 9 +#define MA35D1_RESET_VCAP0 10 +#define MA35D1_RESET_VCAP1 11 +#define MA35D1_RESET_GFX 12 +#define MA35D1_RESET_VDEC 13 +#define MA35D1_RESET_WHC0 14 +#define MA35D1_RESET_WHC1 15 +#define MA35D1_RESET_GMAC0 16 +#define MA35D1_RESET_GMAC1 17 +#define MA35D1_RESET_HWSEM 18 +#define MA35D1_RESET_EBI 19 +#define MA35D1_RESET_HSUSBH0 20 +#define MA35D1_RESET_HSUSBH1 21 +#define MA35D1_RESET_HSUSBD 22 +#define MA35D1_RESET_USBHL 23 +#define MA35D1_RESET_SDH0 24 +#define MA35D1_RESET_SDH1 25 +#define MA35D1_RESET_NAND 26 +#define MA35D1_RESET_GPIO 27 +#define MA35D1_RESET_MCTLP 28 +#define MA35D1_RESET_MCTLC 29 +#define MA35D1_RESET_DDRPUB 30 +#define MA35D1_RESET_TMR0 34 +#define MA35D1_RESET_TMR1 35 +#define MA35D1_RESET_TMR2 36 +#define MA35D1_RESET_TMR3 37 +#define MA35D1_RESET_I2C0 40 +#define MA35D1_RESET_I2C1 41 +#define MA35D1_RESET_I2C2 42 +#define MA35D1_RESET_I2C3 43 +#define MA35D1_RESET_QSPI0 44 +#define MA35D1_RESET_SPI0 45 +#define MA35D1_RESET_SPI1 46 +#define MA35D1_RESET_SPI2 47 +#define MA35D1_RESET_UART0 48 +#define MA35D1_RESET_UART1 49 +#define MA35D1_RESET_UART2 50 +#define MA35D1_RESET_UAER3 51 +#define MA35D1_RESET_UART4 52 +#define MA35D1_RESET_UART5 53 +#define MA35D1_RESET_UART6 54 +#define MA35D1_RESET_UART7 55 +#define MA35D1_RESET_CANFD0 56 +#define MA35D1_RESET_CANFD1 57 +#define MA35D1_RESET_EADC0 60 +#define MA35D1_RESET_I2S0 61 +#define MA35D1_RESET_SC0 64 +#define MA35D1_RESET_SC1 65 +#define MA35D1_RESET_QSPI1 68 +#define MA35D1_RESET_SPI3 70 +#define MA35D1_RESET_EPWM0 80 +#define MA35D1_RESET_EPWM1 81 +#define MA35D1_RESET_QEI0 86 +#define MA35D1_RESET_QEI1 87 +#define MA35D1_RESET_ECAP0 90 +#define MA35D1_RESET_ECAP1 91 +#define MA35D1_RESET_CANFD2 92 +#define MA35D1_RESET_ADC0 95 +#define MA35D1_RESET_TMR4 96 +#define MA35D1_RESET_TMR5 97 +#define MA35D1_RESET_TMR6 98 +#define MA35D1_RESET_TMR7 99 +#define MA35D1_RESET_TMR8 100 +#define MA35D1_RESET_TMR9 101 +#define MA35D1_RESET_TMR10 102 +#define MA35D1_RESET_TMR11 103 +#define MA35D1_RESET_UART8 104 +#define MA35D1_RESET_UART9 105 +#define MA35D1_RESET_UART10 106 +#define MA35D1_RESET_UART11 107 +#define MA35D1_RESET_UART12 108 +#define MA35D1_RESET_UART13 109 +#define MA35D1_RESET_UART14 110 +#define MA35D1_RESET_UART15 111 +#define MA35D1_RESET_UART16 112 +#define MA35D1_RESET_I2S1 113 +#define MA35D1_RESET_I2C4 114 +#define MA35D1_RESET_I2C5 115 +#define MA35D1_RESET_EPWM2 116 +#define MA35D1_RESET_ECAP2 117 +#define MA35D1_RESET_QEI2 118 +#define MA35D1_RESET_CANFD3 119 +#define MA35D1_RESET_KPI 120 +#define MA35D1_RESET_GIC 124 +#define MA35D1_RESET_SSMCC 126 +#define MA35D1_RESET_SSPCC 127 +#define MA35D1_RESET_COUNT 128 + +#endif From patchwork Wed Mar 15 07:28:53 2023 Content-Type: text/plain; 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[60.250.192.107]) by smtp.gmail.com with ESMTPSA id kz11-20020a170902f9cb00b001a0667822c8sm2740003plb.94.2023.03.15.00.29.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Mar 2023 00:29:23 -0700 (PDT) From: Jacky Huang To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, gregkh@linuxfoundation.org, jirislaby@kernel.org Cc: devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, schung@nuvoton.com, Jacky Huang Subject: [PATCH 06/15] dt-bindings: mfd: syscon: Add nuvoton,ma35d1-sys compatible Date: Wed, 15 Mar 2023 07:28:53 +0000 Message-Id: <20230315072902.9298-7-ychuang570808@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230315072902.9298-1-ychuang570808@gmail.com> References: <20230315072902.9298-1-ychuang570808@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Jacky Huang Add Nuvoton ma35d1 system registers compatible Signed-off-by: Jacky Huang --- Documentation/devicetree/bindings/mfd/syscon.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml index c828c4f5e4a7..e7a3c6e1e77f 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -57,6 +57,7 @@ properties: - microchip,sparx5-cpu-syscon - mstar,msc313-pmsleep - nuvoton,wpcm450-shm + - nuvoton,ma35d1-sys - rockchip,px30-qos - rockchip,rk3036-qos - rockchip,rk3066-qos From patchwork Wed Mar 15 07:28:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jacky Huang X-Patchwork-Id: 664305 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5BE15C7618B for ; Wed, 15 Mar 2023 07:31:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231656AbjCOHbf (ORCPT ); Wed, 15 Mar 2023 03:31:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38968 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231650AbjCOHa0 (ORCPT ); Wed, 15 Mar 2023 03:30:26 -0400 Received: from mail-pj1-x1033.google.com (mail-pj1-x1033.google.com [IPv6:2607:f8b0:4864:20::1033]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B4CB46A9D1; Wed, 15 Mar 2023 00:29:32 -0700 (PDT) Received: by mail-pj1-x1033.google.com with SMTP id gp15-20020a17090adf0f00b0023d1bbd9f9eso959537pjb.0; Wed, 15 Mar 2023 00:29:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1678865366; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=j6YPhoB5qekiIB/bKEm014j3Zxx30bCFcgqCGfR6z6o=; b=KaSZFRDcSfDYojn0W3HzDZomplXOMqkSExLU5RK9/6ItjmFVN6YM1XrO+ffdc1XQom ErHjz7FqLMcjZ/Siz6VbHYrjqbkgZsYACbZ1gK4DfBKKJBDNAOyXshyf/GDIcE6IQlMj 7CHjIOfpS2qNzQl0HvG2fDvtQ8ueNvHON2G/wwXii0HJrcesdXHRfiJcwEYAOLDBpyB6 D/XB+JltGQdtwd1uo+Mm0l/+t+xcFKccXqJiGbDSK9PL5H91PdZnJdluBY2G7zlgBuOS xS2XfqNHkIdJP9/m5KryRgrUJ2/C05XsPFHAljkTmp7lGeiuG3sssuzo9/n8qb2p2SD7 s4BA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678865366; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=j6YPhoB5qekiIB/bKEm014j3Zxx30bCFcgqCGfR6z6o=; b=OwogfGd9G94KiCpFfa6WHNxdI6YaWqXf4dTLhIXy5wa26J2QlUXBO96mSiuH9B4rZJ j+o2HsNLGk2RUvz3wiEHgUYl5kW0zRqCWRsXkBE81NkibqdMw9OY3K3BSdJph9bG0gZM 5KfG4YpzbZlEkqhyt122FgzvWVOMoxV9xqpf8xlhFbJyaEhaHwInTQp4N/uJgnjtg7/M jIfM+UKiAsCWiAHZtLAghBAfUdUVV9oL2FQzlpNkC/08hhU0m0zaUzyjZN/e5eDSwTLX XHvzqjfM0UoE83DpeDNTaiDvJ3IemiOqHsrHY+/oITz54sigNlqz5nkZD/VGbTSet8Ox wfsg== X-Gm-Message-State: AO0yUKWoeRg1kRve82fvM2sshI1U379PcKGE8geuYtaaIjaM3c4kDn2c fxKQfcEcnqeCFdEyFD4JZUU= X-Google-Smtp-Source: AK7set/b7j+BfnZ03YOFaKwQRt507Sb+df2V7nZpgVaR499M/+nW3gW/5ViTUwamAsa2nFyH4Vczpw== X-Received: by 2002:a17:902:db05:b0:19c:3d78:6a54 with SMTP id m5-20020a170902db0500b0019c3d786a54mr1521147plx.14.1678865366293; Wed, 15 Mar 2023 00:29:26 -0700 (PDT) Received: from a28aa0606c51.. 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[60.250.192.107]) by smtp.gmail.com with ESMTPSA id kz11-20020a170902f9cb00b001a0667822c8sm2740003plb.94.2023.03.15.00.29.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Mar 2023 00:29:26 -0700 (PDT) From: Jacky Huang To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, gregkh@linuxfoundation.org, jirislaby@kernel.org Cc: devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, schung@nuvoton.com, Jacky Huang Subject: [PATCH 07/15] dt-bindings: arm: Add initial bindings for Nuvoton platform Date: Wed, 15 Mar 2023 07:28:54 +0000 Message-Id: <20230315072902.9298-8-ychuang570808@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230315072902.9298-1-ychuang570808@gmail.com> References: <20230315072902.9298-1-ychuang570808@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Jacky Huang Add binding for ARMv8 based Nuvotn SoCs and platform boards. Add initial bindings for ma35d1 series development boards. Signed-off-by: Jacky Huang --- .../devicetree/bindings/arm/nuvoton.yaml | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/nuvoton.yaml diff --git a/Documentation/devicetree/bindings/arm/nuvoton.yaml b/Documentation/devicetree/bindings/arm/nuvoton.yaml new file mode 100644 index 000000000000..f95e7b30711e --- /dev/null +++ b/Documentation/devicetree/bindings/arm/nuvoton.yaml @@ -0,0 +1,30 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/nuvoton.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton MA35 series SoC based platforms + +maintainers: + - Jacky Huang + +description: | + Boards with an ARMv8 based Nuvoton MA35 series SoC shall have + the following properties. + +properties: + $nodename: + const: '/' + compatible: + oneOf: + + - description: MA35D1 based boards + items: + - enum: + - nuvoton,ma35d1-iot + - nuvoton,ma35d1-som + - const: nuvoton,ma35d1 + +additionalProperties: true +... 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[60.250.192.107]) by smtp.gmail.com with ESMTPSA id kz11-20020a170902f9cb00b001a0667822c8sm2740003plb.94.2023.03.15.00.29.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Mar 2023 00:29:28 -0700 (PDT) From: Jacky Huang To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, gregkh@linuxfoundation.org, jirislaby@kernel.org Cc: devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, schung@nuvoton.com, Jacky Huang Subject: [PATCH 08/15] dt-bindings: clock: Document ma35d1 clock controller bindings Date: Wed, 15 Mar 2023 07:28:55 +0000 Message-Id: <20230315072902.9298-9-ychuang570808@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230315072902.9298-1-ychuang570808@gmail.com> References: <20230315072902.9298-1-ychuang570808@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Jacky Huang Add documentation to describe nuvoton ma35d1 clock driver bindings. Signed-off-by: Jacky Huang --- .../bindings/clock/nuvoton,ma35d1-clk.yaml | 83 +++++++++++++++++++ 1 file changed, 83 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/nuvoton,ma35d1-clk.yaml diff --git a/Documentation/devicetree/bindings/clock/nuvoton,ma35d1-clk.yaml b/Documentation/devicetree/bindings/clock/nuvoton,ma35d1-clk.yaml new file mode 100644 index 000000000000..5c2dea071b38 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/nuvoton,ma35d1-clk.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/nuvoton,ma35d1-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton MA35D1 Clock Controller Module Binding + +maintainers: + - Chi-Fang Li + - Jacky Huang + +description: | + The MA35D1 clock controller generates clocks for the whole chip, + including system clocks and all peripheral clocks. + + See also: + include/dt-bindings/clock/ma35d1-clk.h + +properties: + compatible: + items: + - const: nuvoton,ma35d1-clk + - const: syscon + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + clocks: + maxItems: 1 + + clock-names: + const: clk_hxt + + assigned-clocks: + maxItems: 5 + + assigned-clock-rates: + maxItems: 5 + + nuvoton,pll-mode: + description: + A list of PLL operation mode corresponding to CAPLL, DDRPLL, APLL, + EPLL, and VPLL in sequential. The operation mode value 0 is for + integer mode, 1 is for fractional mode, and 2 is for spread + spectrum mode. + $ref: /schemas/types.yaml#/definitions/uint32-array + maxItems: 5 + items: + minimum: 0 + maximum: 2 + + nuvoton,sys: + description: + Phandle to the system management controller. + $ref: "/schemas/types.yaml#/definitions/phandle-array" + +required: + - compatible + - reg + - "#clock-cells" + - clocks + - clock-names + - nuvoton,sys + +additionalProperties: false + +examples: + - | + #include + + clk: clock-controller@40460200 { + compatible = "nuvoton,ma35d1-clk", "syscon"; + reg = <0x40460200 0x100>; + #clock-cells = <1>; + clocks = <&clk_hxt>; + clock-names = "clk_hxt"; + nuvoton,sys = <&sys>; + }; +... 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[60.250.192.107]) by smtp.gmail.com with ESMTPSA id kz11-20020a170902f9cb00b001a0667822c8sm2740003plb.94.2023.03.15.00.29.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Mar 2023 00:29:31 -0700 (PDT) From: Jacky Huang To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, gregkh@linuxfoundation.org, jirislaby@kernel.org Cc: devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, schung@nuvoton.com, Jacky Huang Subject: [PATCH 09/15] dt-bindings: reset: Document ma35d1 reset controller bindings Date: Wed, 15 Mar 2023 07:28:56 +0000 Message-Id: <20230315072902.9298-10-ychuang570808@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230315072902.9298-1-ychuang570808@gmail.com> References: <20230315072902.9298-1-ychuang570808@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Jacky Huang Add documentation to describe nuvoton ma35d1 reset driver bindings. Signed-off-by: Jacky Huang --- .../bindings/reset/nuvoton,ma35d1-reset.yaml | 50 +++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/nuvoton,ma35d1-reset.yaml diff --git a/Documentation/devicetree/bindings/reset/nuvoton,ma35d1-reset.yaml b/Documentation/devicetree/bindings/reset/nuvoton,ma35d1-reset.yaml new file mode 100644 index 000000000000..f66c566c6dce --- /dev/null +++ b/Documentation/devicetree/bindings/reset/nuvoton,ma35d1-reset.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/nuvoton,ma35d1-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton MA35D1 Reset Controller + +maintainers: + - Chi-Fang Li + - Jacky Huang + +description: + The system reset controller can be used to reset various peripheral + controllers in MA35D1 SoC. + +properties: + compatible: + const: nuvoton,ma35d1-reset + + regmap: + $ref: /schemas/types.yaml#/definitions/phandle + description: Phandle to the register map node. + + '#reset-cells': + const: 1 + +required: + - compatible + - regmap + - '#reset-cells' + +additionalProperties: false + +examples: + # system reset controller node: + - | + #include + + sys: system-management@40460000 { + compatible = "nuvoton,ma35d1-sys", "syscon", "simple-mfd"; + reg = <0x40460000 0x200>; + + reset: reset-controller { + compatible = "nuvoton,ma35d1-reset"; + regmap = <&sys>; + #reset-cells = <1>; + }; + }; +... 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[60.250.192.107]) by smtp.gmail.com with ESMTPSA id kz11-20020a170902f9cb00b001a0667822c8sm2740003plb.94.2023.03.15.00.29.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Mar 2023 00:29:33 -0700 (PDT) From: Jacky Huang To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, gregkh@linuxfoundation.org, jirislaby@kernel.org Cc: devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, schung@nuvoton.com, Jacky Huang Subject: [PATCH 10/15] dt-bindings: serial: Document ma35d1 uart controller bindings Date: Wed, 15 Mar 2023 07:28:57 +0000 Message-Id: <20230315072902.9298-11-ychuang570808@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230315072902.9298-1-ychuang570808@gmail.com> References: <20230315072902.9298-1-ychuang570808@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Jacky Huang Add documentation to describe nuvoton ma35d1 uart driver bindings. Signed-off-by: Jacky Huang --- .../serial/nuvoton,ma35d1-serial.yaml | 52 +++++++++++++++++++ 1 file changed, 52 insertions(+) create mode 100644 Documentation/devicetree/bindings/serial/nuvoton,ma35d1-serial.yaml diff --git a/Documentation/devicetree/bindings/serial/nuvoton,ma35d1-serial.yaml b/Documentation/devicetree/bindings/serial/nuvoton,ma35d1-serial.yaml new file mode 100644 index 000000000000..9daa2efd4734 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/nuvoton,ma35d1-serial.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/nuvoton,ma35d1-serial.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton MA35D1 Universal Asynchronous Receiver/Transmitter (UART) + +maintainers: + - Min-Jen Chen + - Jacky Huang + +allOf: + - $ref: "serial.yaml" + +properties: + compatible: + const: nuvoton,ma35d1-uart + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + +unevaluatedProperties: false + +examples: + - | + #include + #include + + aliases { + serial0 = &uart0; + }; + + uart0:serial@40700000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x40700000 0x100>; + interrupts = ; + clocks = <&clk UART0_GATE>; + }; +... From patchwork Wed Mar 15 07:28:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jacky Huang X-Patchwork-Id: 664303 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EB8AFC76196 for ; Wed, 15 Mar 2023 07:32:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231743AbjCOHcC (ORCPT ); Wed, 15 Mar 2023 03:32:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38448 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230255AbjCOHav (ORCPT ); Wed, 15 Mar 2023 03:30:51 -0400 Received: from mail-pj1-x1029.google.com (mail-pj1-x1029.google.com [IPv6:2607:f8b0:4864:20::1029]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 008F36C1AD; Wed, 15 Mar 2023 00:29:38 -0700 (PDT) Received: by mail-pj1-x1029.google.com with SMTP id cn6so5261533pjb.2; Wed, 15 Mar 2023 00:29:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1678865376; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=oxf2iuQCA7nEtSMFt+3Of43dgLj8kzulTG3yBMHVzIk=; b=WxxYlTV5kHOUj12ysBMBsJpzBPqVDgM+hhnbBssqv+wpaHVRoBWHAZQYX++u8WSoZ6 wsI5S5Scw41VhKLawzko2xQR4LRFnHVF9Y9uBuAZMmA//4o1oWtpyHJooJdMbLhJrlnd M8+UyXl4Ey8M2QZokZLdSoK+kWpDYsOOK7UATUGQFJ89y5OXVAG+QPC2ySXmXZQdu21E j6r7qBadYSM2UzGfUZAs9zPg8rIbLv5TQd1GIR2Trd+eEvh9ZiZGqWces6Z98jJu/vOT Bzj9oyIR/E17v7QwTEbOZijsnWW/Ylt9/dlraKQGxz7mrfpbQ+UqrfThfF3U+RPGn58R CvaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678865376; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oxf2iuQCA7nEtSMFt+3Of43dgLj8kzulTG3yBMHVzIk=; b=5crIZU6NZxSErEnWgavGba/if49cwiQQFj8syeqtFP475Muu2IuZHh1aln6CCR9oca KO2y03DqNCReSTauhVsXUzgkqUeXAKbA8px+7RQzGeyzNnAFlTr8IL32zSgIJLHi/WIV 1Bztd5V6RsC686fFt55XgfqvHQFSlJc0rWetenDXVRQKeOQF2JpDzQV+gqQRa0jJS1kd dx5QpvVsPwyEE7makot85WD0PTNcA6tSXSUlA7QiH6wexmPWvA7fdAdLlQOypX4UJ8Ga nwDd8wWPCnYvbXKjncL8FmWfoz3C6NC1ocVDgS6YKX1vst8yQ3GDwJQvGtpqhMAdZ0Jc kZ9Q== X-Gm-Message-State: AO0yUKWK+44kr3VSFmqsb/3FtgXaKdPe6mRsMHFnV+5u/2SSZ/9W1qb1 NL7rVtrrZZudzFmceUCa/iw= X-Google-Smtp-Source: AK7set/OpbEZ1OSLmu8a+XAiyrbXKulXANL1WZM4L8qqiY0W4sIUxVpt+grwwpQLztGLeXqo6I2d8A== X-Received: by 2002:a17:903:120b:b0:19d:14c:e590 with SMTP id l11-20020a170903120b00b0019d014ce590mr1869475plh.9.1678865376311; Wed, 15 Mar 2023 00:29:36 -0700 (PDT) Received: from a28aa0606c51.. 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[60.250.192.107]) by smtp.gmail.com with ESMTPSA id kz11-20020a170902f9cb00b001a0667822c8sm2740003plb.94.2023.03.15.00.29.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Mar 2023 00:29:36 -0700 (PDT) From: Jacky Huang To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, gregkh@linuxfoundation.org, jirislaby@kernel.org Cc: devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, schung@nuvoton.com, Jacky Huang Subject: [PATCH 11/15] arm64: dts: nuvoton: Add initial ma35d1 device tree Date: Wed, 15 Mar 2023 07:28:58 +0000 Message-Id: <20230315072902.9298-12-ychuang570808@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230315072902.9298-1-ychuang570808@gmail.com> References: <20230315072902.9298-1-ychuang570808@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Jacky Huang Add initial device tree support for Nuvoton ma35d1 SoC, including cpu, clock, reset, and serial controllers. Add reference boards som-256m and iot-512m. Signed-off-by: Jacky Huang --- arch/arm64/boot/dts/nuvoton/Makefile | 2 + .../boot/dts/nuvoton/ma35d1-iot-512m.dts | 24 ++ .../boot/dts/nuvoton/ma35d1-som-256m.dts | 23 ++ arch/arm64/boot/dts/nuvoton/ma35d1.dtsi | 272 ++++++++++++++++++ 4 files changed, 321 insertions(+) create mode 100644 arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts create mode 100644 arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts create mode 100644 arch/arm64/boot/dts/nuvoton/ma35d1.dtsi diff --git a/arch/arm64/boot/dts/nuvoton/Makefile b/arch/arm64/boot/dts/nuvoton/Makefile index a99dab90472a..c11ab4eac9c7 100644 --- a/arch/arm64/boot/dts/nuvoton/Makefile +++ b/arch/arm64/boot/dts/nuvoton/Makefile @@ -1,2 +1,4 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_NPCM) += nuvoton-npcm845-evb.dtb +dtb-$(CONFIG_ARCH_NUVOTON) += ma35d1-iot-512m.dtb +dtb-$(CONFIG_ARCH_NUVOTON) += ma35d1-som-256m.dtb diff --git a/arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts b/arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts new file mode 100644 index 000000000000..dffcaef1e6d8 --- /dev/null +++ b/arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 Nuvoton Technology Corp. + * Author: Shan-Chun Hung + * Jacky huang + */ + +/dts-v1/; +#include "ma35d1.dtsi" + +/ { + model = "Nuvoton MA35D1-IoT"; + compatible = "nuvoton,ma35d1-iot", "nuvoton,ma35d1"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + mem: memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x20000000>; /* 512M DRAM */ + }; +}; + diff --git a/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts b/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts new file mode 100644 index 000000000000..3e6c3d5469ac --- /dev/null +++ b/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 Nuvoton Technology Corp. + * Author: Shan-Chun Hung + * Jacky huang + */ + +/dts-v1/; +#include "ma35d1.dtsi" + +/ { + model = "Nuvoton MA35D1-SOM"; + compatible = "nuvoton,ma35d1-som", "nuvoton,ma35d1"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + mem: memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x10000000>; /* 256M DRAM */ + }; +}; diff --git a/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi b/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi new file mode 100644 index 000000000000..8c855f6b330a --- /dev/null +++ b/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi @@ -0,0 +1,272 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 Nuvoton Technology Corp. + * Author: Shan-Chun Hung + * Jacky huang + */ + +#include +#include +#include +#include +#include + +/ { + compatible = "nuvoton,ma35d1"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; + serial6 = &uart6; + serial7 = &uart7; + serial8 = &uart8; + serial9 = &uart9; + serial10 = &uart10; + serial11 = &uart11; + serial12 = &uart12; + serial13 = &uart13; + serial14 = &uart14; + serial15 = &uart15; + serial16 = &uart16; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x1>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + L2_0: l2-cache0 { + compatible = "cache"; + cache-level = <2>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + clk_hxt: clock_hxt { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "clk_hxt"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , /* Physical Secure */ + , /* Physical Non-Secure */ + , /* Virtual */ + ; /* Hypervisor */ + clock-frequency = <12000000>; + interrupt-parent = <&gic>; + }; + + sys: system-management@40460000 { + compatible = "nuvoton,ma35d1-sys", "syscon", "simple-mfd"; + reg = <0x0 0x40460000 0x0 0x200>; + + reset: reset-controller { + compatible = "nuvoton,ma35d1-reset"; + regmap = <&sys>; + #reset-cells = <1>; + }; + }; + + clk: clock-controller@40460200 { + compatible = "nuvoton,ma35d1-clk", "syscon"; + reg = <0x00000000 0x40460200 0x0 0x100>; + #clock-cells = <1>; + clocks = <&clk_hxt>; + clock-names = "clk_hxt"; + assigned-clocks = <&clk CAPLL>, + <&clk DDRPLL>, + <&clk APLL>, + <&clk EPLL>, + <&clk VPLL>; + assigned-clock-rates = <800000000>, + <266000000>, + <180000000>, + <500000000>, + <102000000>; + nuvoton,pll-mode = <0>, <1>, <0>, <0>, <0>; + nuvoton,sys = <&sys>; + }; + + gic: interrupt-controller@50801000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + interrupt-controller; + reg = <0x0 0x50801000 0 0x1000>, /* GICD */ + <0x0 0x50802000 0 0x2000>, /* GICC */ + <0x0 0x50804000 0 0x2000>, /* GICH */ + <0x0 0x50806000 0 0x2000>; /* GICV */ + interrupts = ; + }; + + uart0:serial@40700000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x40700000 0x0 0x100>; + interrupts = ; + clocks = <&clk UART0_GATE>; + status = "okay"; + }; + + uart1:serial@40710000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x40710000 0x0 0x100>; + interrupts = ; + clocks = <&clk UART1_GATE>; + status = "disabled"; + }; + + uart2:serial@40720000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x40720000 0x0 0x100>; + interrupts = ; + clocks = <&clk UART2_GATE>; + status = "disabled"; + }; + + uart3:serial@40730000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x40730000 0x0 0x100>; + interrupts = ; + clocks = <&clk UART3_GATE>; + status = "disabled"; + }; + + uart4:serial@40740000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x40740000 0x0 0x100>; + interrupts = ; + clocks = <&clk UART4_GATE>; + status = "disabled"; + }; + + uart5:serial@40750000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x40750000 0x0 0x100>; + interrupts = ; + clocks = <&clk UART5_GATE>; + status = "disabled"; + }; + + uart6:serial@40760000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x40760000 0x0 0x100>; + interrupts = ; + clocks = <&clk UART6_GATE>; + status = "disabled"; + }; + + uart7:serial@40770000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x40770000 0x0 0x100>; + interrupts = ; + clocks = <&clk UART7_GATE>; + status = "disabled"; + }; + + uart8:serial@40780000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x40780000 0x0 0x100>; + interrupts = ; + clocks = <&clk UART8_GATE>; + status = "disabled"; + }; + + uart9:serial@40790000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x40790000 0x0 0x100>; + interrupts = ; + clocks = <&clk UART9_GATE>; + status = "disabled"; + }; + + uart10:serial@407a0000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x407a0000 0x0 0x100>; + interrupts = ; + clocks = <&clk UART10_GATE>; + status = "disabled"; + }; + + uart11:serial@407b0000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x407b0000 0x0 0x100>; + interrupts = ; + clocks = <&clk UART11_GATE>; + status = "disabled"; + }; + + uart12:serial@407c0000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x407c0000 0x0 0x100>; + interrupts = ; + clocks = <&clk UART12_GATE>; + status = "disabled"; + }; + + uart13:serial@407d0000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x407d0000 0x0 0x100>; + interrupts = ; + clocks = <&clk UART13_GATE>; + status = "disabled"; + }; + + uart14:serial@407e0000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x407e0000 0x0 0x100>; + interrupts = ; + clocks = <&clk UART14_GATE>; + status = "disabled"; + }; + + uart15:serial@407f0000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x407f0000 0x0 0x100>; + interrupts = ; + clocks = <&clk UART15_GATE>; + status = "disabled"; + }; + + uart16:serial@40880000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x40880000 0x0 0x100>; + interrupts = ; + clocks = <&clk UART16_GATE>; + status = "disabled"; + }; +}; From patchwork Wed Mar 15 07:28:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jacky Huang X-Patchwork-Id: 664302 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 77F9EC76195 for ; Wed, 15 Mar 2023 07:32:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231803AbjCOHcS (ORCPT ); Wed, 15 Mar 2023 03:32:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39144 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231522AbjCOHax (ORCPT ); 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[60.250.192.107]) by smtp.gmail.com with ESMTPSA id kz11-20020a170902f9cb00b001a0667822c8sm2740003plb.94.2023.03.15.00.29.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Mar 2023 00:29:38 -0700 (PDT) From: Jacky Huang To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, gregkh@linuxfoundation.org, jirislaby@kernel.org Cc: devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, schung@nuvoton.com, Jacky Huang Subject: [PATCH 12/15] clk: nuvoton: Add clock driver for ma35d1 clock controller Date: Wed, 15 Mar 2023 07:28:59 +0000 Message-Id: <20230315072902.9298-13-ychuang570808@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230315072902.9298-1-ychuang570808@gmail.com> References: <20230315072902.9298-1-ychuang570808@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Jacky Huang The clock controller generates clocks for the whole chip, including system clocks and all peripheral clocks. This driver support ma35d1 clock gating, divider, and individual PLL configuration. There are 6 PLLs in ma35d1 SoC: - CA-PLL for the two Cortex-A35 CPU clock - SYS-PLL for system bus, which comes from the companion MCU and cannot be programmed by clock controller. - DDR-PLL for DDR - EPLL for GMAC and GFX, Display, and VDEC IPs. - VPLL for video output pixel clock - APLL for SDHC, I2S audio, and other IPs. CA-PLL has only one operation mode. DDR-PLL, EPLL, VPLL, and APLL are advanced PLLs which have 3 operation modes: integer mode, fraction mode, and spread specturm mode. Signed-off-by: Jacky Huang --- drivers/clk/Makefile | 1 + drivers/clk/nuvoton/Makefile | 4 + drivers/clk/nuvoton/clk-ma35d1-divider.c | 144 ++++ drivers/clk/nuvoton/clk-ma35d1-pll.c | 534 +++++++++++++ drivers/clk/nuvoton/clk-ma35d1.c | 970 +++++++++++++++++++++++ drivers/clk/nuvoton/clk-ma35d1.h | 198 +++++ 6 files changed, 1851 insertions(+) create mode 100644 drivers/clk/nuvoton/Makefile create mode 100644 drivers/clk/nuvoton/clk-ma35d1-divider.c create mode 100644 drivers/clk/nuvoton/clk-ma35d1-pll.c create mode 100644 drivers/clk/nuvoton/clk-ma35d1.c create mode 100644 drivers/clk/nuvoton/clk-ma35d1.h diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index e3ca0d058a25..2e7916d269e1 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -103,6 +103,7 @@ endif obj-y += mstar/ obj-y += mvebu/ obj-$(CONFIG_ARCH_MXS) += mxs/ +obj-$(CONFIG_ARCH_NUVOTON) += nuvoton/ obj-$(CONFIG_COMMON_CLK_NXP) += nxp/ obj-$(CONFIG_COMMON_CLK_PISTACHIO) += pistachio/ obj-$(CONFIG_COMMON_CLK_PXA) += pxa/ diff --git a/drivers/clk/nuvoton/Makefile b/drivers/clk/nuvoton/Makefile new file mode 100644 index 000000000000..d2c092541b8d --- /dev/null +++ b/drivers/clk/nuvoton/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_ARCH_NUVOTON) += clk-ma35d1.o +obj-$(CONFIG_ARCH_NUVOTON) += clk-ma35d1-divider.o +obj-$(CONFIG_ARCH_NUVOTON) += clk-ma35d1-pll.o diff --git a/drivers/clk/nuvoton/clk-ma35d1-divider.c b/drivers/clk/nuvoton/clk-ma35d1-divider.c new file mode 100644 index 000000000000..5f4791531e47 --- /dev/null +++ b/drivers/clk/nuvoton/clk-ma35d1-divider.c @@ -0,0 +1,144 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023 Nuvoton Technology Corp. + * Author: Chi-Fang Li + */ + +#include +#include +#include +#include +#include + +#include "clk-ma35d1.h" + +#define div_mask(width) ((1 << (width)) - 1) + +struct ma35d1_adc_clk_divider { + struct clk_hw hw; + void __iomem *reg; + u8 shift; + u8 width; + u32 mask; + const struct clk_div_table *table; + spinlock_t *lock; +}; + +#define to_ma35d1_adc_clk_divider(_hw) \ + container_of(_hw, struct ma35d1_adc_clk_divider, hw) + +static unsigned long ma35d1_clkdiv_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + unsigned int val; + struct ma35d1_adc_clk_divider *dclk = to_ma35d1_adc_clk_divider(hw); + + val = readl_relaxed(dclk->reg) >> dclk->shift; + val &= div_mask(dclk->width); + val += 1; + return divider_recalc_rate(hw, parent_rate, val, dclk->table, + CLK_DIVIDER_ROUND_CLOSEST, dclk->width); +} + +static long ma35d1_clkdiv_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + struct ma35d1_adc_clk_divider *dclk = to_ma35d1_adc_clk_divider(hw); + + return divider_round_rate(hw, rate, prate, dclk->table, + dclk->width, CLK_DIVIDER_ROUND_CLOSEST); +} + +static int ma35d1_clkdiv_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + int value; + unsigned long flags = 0; + u32 data; + struct ma35d1_adc_clk_divider *dclk = to_ma35d1_adc_clk_divider(hw); + + value = divider_get_val(rate, parent_rate, dclk->table, + dclk->width, CLK_DIVIDER_ROUND_CLOSEST); + + if (dclk->lock) + spin_lock_irqsave(dclk->lock, flags); + + data = readl_relaxed(dclk->reg); + data &= ~(div_mask(dclk->width) << dclk->shift); + data |= (value - 1) << dclk->shift; + data |= dclk->mask; + + writel_relaxed(data, dclk->reg); + + if (dclk->lock) + spin_unlock_irqrestore(dclk->lock, flags); + + return 0; +} + +static const struct clk_ops ma35d1_adc_clkdiv_ops = { + .recalc_rate = ma35d1_clkdiv_recalc_rate, + .round_rate = ma35d1_clkdiv_round_rate, + .set_rate = ma35d1_clkdiv_set_rate, +}; + +struct clk_hw *ma35d1_reg_adc_clkdiv(struct device *dev, const char *name, + const char *parent_name, + unsigned long flags, void __iomem *reg, + u8 shift, u8 width, u32 mask_bit) +{ + struct ma35d1_adc_clk_divider *div; + struct clk_init_data init; + struct clk_div_table *table; + u32 max_div, min_div; + struct clk_hw *hw; + int ret; + int i; + + /* allocate the divider */ + div = kzalloc(sizeof(*div), GFP_KERNEL); + if (!div) + return ERR_PTR(-ENOMEM); + + /* Init the divider table */ + max_div = div_mask(width) + 1; + min_div = 1; + + table = kcalloc(max_div + 1, sizeof(*table), GFP_KERNEL); + if (!table) { + kfree(div); + return ERR_PTR(-ENOMEM); + } + + for (i = 0; i < max_div; i++) { + table[i].val = (min_div + i); + table[i].div = 2 * table[i].val; + } + table[max_div].val = 0; + table[max_div].div = 0; + + init.name = name; + init.ops = &ma35d1_adc_clkdiv_ops; + init.flags |= flags; + init.parent_names = parent_name ? &parent_name : NULL; + init.num_parents = parent_name ? 1 : 0; + + /* struct ma35d1_adc_clk_divider assignments */ + div->reg = reg; + div->shift = shift; + div->width = width; + div->mask = mask_bit ? BIT(mask_bit) : 0; + div->lock = &ma35d1_lock; + div->hw.init = &init; + div->table = table; + + /* Register the clock */ + hw = &div->hw; + ret = clk_hw_register(NULL, hw); + if (ret) { + kfree(table); + kfree(div); + return ERR_PTR(ret); + } + return hw; +} diff --git a/drivers/clk/nuvoton/clk-ma35d1-pll.c b/drivers/clk/nuvoton/clk-ma35d1-pll.c new file mode 100644 index 000000000000..79e724b148fa --- /dev/null +++ b/drivers/clk/nuvoton/clk-ma35d1-pll.c @@ -0,0 +1,534 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023 Nuvoton Technology Corp. + * Author: Chi-Fang Li + */ + +#include +#include +#include +#include +#include + +#include "clk-ma35d1.h" + +#define to_ma35d1_clk_pll(clk) \ + (container_of(clk, struct ma35d1_clk_pll, clk)) + +#define PLL0CTL0_FBDIV_MSK GENMASK(7, 0) +#define PLL0CTL0_INDIV_MSK GENMASK(11, 8) +#define PLL0CTL0_OUTDIV_MSK GENMASK(13, 12) +#define PLL0CTL0_PD_MSK BIT(16) +#define PLL0CTL0_BP_MSK BIT(17) +#define PLLXCTL0_FBDIV_MSK GENMASK(10, 0) +#define PLLXCTL0_INDIV_MSK GENMASK(17, 12) +#define PLLXCTL0_MODE_MSK GENMASK(19, 18) +#define PLLXCTL0_SSRATE_MSK GENMASK(30, 20) +#define PLLXCTL1_PD_MSK BIT(0) +#define PLLXCTL1_BP_MSK BIT(1) +#define PLLXCTL1_OUTDIV_MSK GENMASK(6, 4) +#define PLLXCTL1_FRAC_MSK GENMASK(31, 8) +#define PLLXCTL2_SLOPE_MSK GENMASK(23, 0) + +struct ma35d1_clk_pll { + struct clk_hw hw; + u8 type; + u8 mode; + unsigned long rate; + void __iomem *ctl0_base; + void __iomem *ctl1_base; + void __iomem *ctl2_base; + struct regmap *regmap; +}; + +struct vsipll_freq_conf_reg_tbl { + unsigned long freq; + u8 mode; + u32 ctl0_reg; + u32 ctl1_reg; + u32 ctl2_reg; +}; + +static const struct vsipll_freq_conf_reg_tbl ma35d1pll_freq[] = { + { 1000000000, VSIPLL_INTEGER_MODE, 0x307d, 0x10, 0 }, + { 884736000, VSIPLL_FRACTIONAL_MODE, 0x41024, 0xdd2f1b11, 0 }, + { 533000000, VSIPLL_SS_MODE, 0x12b8102c, 0x6aaaab20, 0x12317 }, + { } +}; + +static void CLK_UnLockReg(struct ma35d1_clk_pll *pll) +{ + int ret; + + /* Unlock PLL registers */ + do { + regmap_write(pll->regmap, REG_SYS_RLKTZNS, 0x59); + regmap_write(pll->regmap, REG_SYS_RLKTZNS, 0x16); + regmap_write(pll->regmap, REG_SYS_RLKTZNS, 0x88); + regmap_read(pll->regmap, REG_SYS_RLKTZNS, &ret); + } while (ret == 0); +} + +static void CLK_LockReg(struct ma35d1_clk_pll *pll) +{ + /* Lock PLL registers */ + regmap_write(pll->regmap, REG_SYS_RLKTZNS, 0x0); +} + +/* SMIC PLL for CAPLL */ +unsigned long CLK_GetPLLFreq_SMICPLL(struct ma35d1_clk_pll *pll, + unsigned long PllSrcClk) +{ + u32 u32M, u32N, u32P, u32OutDiv; + u32 val; + unsigned long u64PllClk; + u32 clk_div_table[] = { 1, 2, 4, 8}; + + val = __raw_readl(pll->ctl0_base); + + u32N = FIELD_GET(PLL0CTL0_FBDIV_MSK, val); + u32M = FIELD_GET(PLL0CTL0_INDIV_MSK, val); + u32P = FIELD_GET(PLL0CTL0_OUTDIV_MSK, val); + u32OutDiv = clk_div_table[u32P]; + + if (val & PLL0CTL0_BP_MSK) { + u64PllClk = PllSrcClk; + } else { + u64PllClk = PllSrcClk * u32N; + do_div(u64PllClk, u32M * u32OutDiv); + } + return u64PllClk; +} + +/* VSI-PLL: INTEGER_MODE */ +unsigned long CLK_CalPLLFreq_Mode0(unsigned long PllSrcClk, + unsigned long u64PllFreq, u32 *u32Reg) +{ + u32 u32TmpM, u32TmpN, u32TmpP; + u32 u32RngMinN, u32RngMinM, u32RngMinP; + u32 u32RngMaxN, u32RngMaxM, u32RngMaxP; + u32 u32Tmp, u32Min, u32MinN, u32MinM, u32MinP; + unsigned long u64PllClk; + unsigned long u64Con1, u64Con2, u64Con3; + + u64PllClk = 0; + u32Min = (u32) -1; + + if (!((u64PllFreq >= VSIPLL_FCLKO_MIN_FREQ) && + (u64PllFreq <= VSIPLL_FCLKO_MAX_FREQ))) { + u32Reg[0] = ma35d1pll_freq[0].ctl0_reg; + u32Reg[1] = ma35d1pll_freq[0].ctl1_reg; + u64PllClk = ma35d1pll_freq[0].freq; + return u64PllClk; + } + + u32RngMinM = 1UL; + u32RngMaxM = 63UL; + u32RngMinM = ((PllSrcClk / VSIPLL_FREFDIVM_MAX_FREQ) > 1) ? + (PllSrcClk / VSIPLL_FREFDIVM_MAX_FREQ) : 1; + u32RngMaxM = ((PllSrcClk / VSIPLL_FREFDIVM_MIN_FREQ0) < u32RngMaxM) ? + (PllSrcClk / VSIPLL_FREFDIVM_MIN_FREQ0) : u32RngMaxM; + + for (u32TmpM = u32RngMinM; u32TmpM < (u32RngMaxM + 1); u32TmpM++) { + u64Con1 = PllSrcClk / u32TmpM; + u32RngMinN = 16UL; + u32RngMaxN = 2047UL; + u32RngMinN = ((VSIPLL_FCLK_MIN_FREQ / u64Con1) > u32RngMinN) ? + (VSIPLL_FCLK_MIN_FREQ / u64Con1) : u32RngMinN; + u32RngMaxN = ((VSIPLL_FCLK_MAX_FREQ / u64Con1) < u32RngMaxN) ? + (VSIPLL_FCLK_MAX_FREQ / u64Con1) : u32RngMaxN; + + for (u32TmpN = u32RngMinN; u32TmpN < (u32RngMaxN + 1); + u32TmpN++) { + u64Con2 = u64Con1 * u32TmpN; + u32RngMinP = 1UL; + u32RngMaxP = 7UL; + u32RngMinP = ((u64Con2 / VSIPLL_FCLKO_MAX_FREQ) > 1) ? + (u64Con2 / VSIPLL_FCLKO_MAX_FREQ) : 1; + u32RngMaxP = ((u64Con2 / VSIPLL_FCLKO_MIN_FREQ) < + u32RngMaxP) ? + (u64Con2 / VSIPLL_FCLKO_MIN_FREQ) : + u32RngMaxP; + for (u32TmpP = u32RngMinP; u32TmpP < (u32RngMaxP + 1); + u32TmpP++) { + u64Con3 = u64Con2 / u32TmpP; + if (u64Con3 > u64PllFreq) + u32Tmp = u64Con3 - u64PllFreq; + else + u32Tmp = u64PllFreq - u64Con3; + + if (u32Tmp < u32Min) { + u32Min = u32Tmp; + u32MinM = u32TmpM; + u32MinN = u32TmpN; + u32MinP = u32TmpP; + + if (u32Min == 0UL) { + u32Reg[0] = (u32MinM << 12) | + (u32MinN); + u32Reg[1] = (u32MinP << 4); + return ((PllSrcClk * u32MinN) / + (u32MinP * u32MinM)); + } + } + } + } + } + + u32Reg[0] = (u32MinM << 12) | (u32MinN); + u32Reg[1] = (u32MinP << 4); + u64PllClk = (PllSrcClk * u32MinN) / (u32MinP * u32MinM); + return u64PllClk; +} + +/* VSI-PLL: FRACTIONAL_MODE */ +unsigned long CLK_CalPLLFreq_Mode1(unsigned long PllSrcClk, + unsigned long u64PllFreq, u32 *u32Reg) +{ + unsigned long u64X, u64N, u64M, u64P, u64tmp; + unsigned long u64PllClk, u64FCLKO; + u32 u32FRAC; + + if (u64PllFreq > VSIPLL_FCLKO_MAX_FREQ) { + u32Reg[0] = ma35d1pll_freq[1].ctl0_reg; + u32Reg[1] = ma35d1pll_freq[1].ctl1_reg; + u64PllClk = ma35d1pll_freq[1].freq; + return u64PllClk; + } + + if (u64PllFreq > (VSIPLL_FCLKO_MIN_FREQ/(100-1))) { + u64FCLKO = u64PllFreq * ((VSIPLL_FCLKO_MIN_FREQ / u64PllFreq) + + ((VSIPLL_FCLKO_MIN_FREQ % u64PllFreq) ? 1 : 0)); + } else { + pr_err("Failed to set rate %ld\n", u64PllFreq); + return 0; + } + + u64P = (u64FCLKO >= VSIPLL_FCLK_MIN_FREQ) ? 1 : + ((VSIPLL_FCLK_MIN_FREQ / u64FCLKO) + + ((VSIPLL_FCLK_MIN_FREQ % u64FCLKO) ? 1 : 0)); + + if ((PllSrcClk > (VSIPLL_FREFDIVM_MAX_FREQ * (64-1))) || + (PllSrcClk < VSIPLL_FREFDIVM_MIN_FREQ1)) + return 0; + + u64M = (PllSrcClk <= VSIPLL_FREFDIVM_MAX_FREQ) ? 1 : + ((PllSrcClk / VSIPLL_FREFDIVM_MAX_FREQ) + + ((PllSrcClk % VSIPLL_FREFDIVM_MAX_FREQ) ? 1 : 0)); + + u64tmp = (u64FCLKO * u64P * u64M * 1000) / PllSrcClk; + u64N = u64tmp / 1000; + u64X = u64tmp % 1000; + u32FRAC = ((u64X << 24) + 500) / 1000; + u64PllClk = (PllSrcClk * u64tmp) / u64P / u64M / 1000; + + u32Reg[0] = (u64M << 12) | (u64N); + u32Reg[1] = (u64P << 4) | (u32FRAC << 8); + return u64PllClk; +} + +/* VSI-PLL: SS_MODE */ +unsigned long CLK_CalPLLFreq_Mode2(unsigned long PllSrcClk, + unsigned long u64PllFreq, + u32 u32SR, u32 u32Fmod, u32 *u32Reg) +{ + unsigned long u64X, u64N, u64M, u64P, u64tmp, u64tmpP, u64tmpM; + unsigned long u64SSRATE, u64SLOPE, u64PllClk, u64FCLKO; + u32 u32FRAC, i; + + if (u64PllFreq >= VSIPLL_FCLKO_MAX_FREQ) { + u32Reg[0] = ma35d1pll_freq[2].ctl0_reg; + u32Reg[1] = ma35d1pll_freq[2].ctl1_reg; + u32Reg[2] = ma35d1pll_freq[2].ctl2_reg; + u64PllClk = ma35d1pll_freq[2].freq; + return u64PllClk; + } + + if (u64PllFreq < VSIPLL_FCLKO_MIN_FREQ) { + u64FCLKO = 0; + for (i = 2; i < 8; i++) { + u64tmp = (i * u64PllFreq); + if (u64tmp > VSIPLL_FCLKO_MIN_FREQ) + u64FCLKO = u64tmp; + } + if (u64FCLKO == 0) { + pr_err("Failed to set rate %ld\n", u64PllFreq); + return 0; + } + + } else + u64FCLKO = u64PllFreq; + + u64P = 0; + for (i = 1; i < 8; i++) { + u64tmpP = i * u64FCLKO; + if ((u64tmpP <= VSIPLL_FCLK_MAX_FREQ) && + (u64tmpP >= VSIPLL_FCLK_MIN_FREQ)) { + u64P = i; + break; + } + } + + if (u64P == 0) + return 0; + + u64M = 0; + for (i = 1; i < 64; i++) { + u64tmpM = PllSrcClk / i; + if ((u64tmpM <= VSIPLL_FREFDIVM_MAX_FREQ) && + (u64tmpM >= VSIPLL_FREFDIVM_MIN_FREQ1)) { + u64M = i; + break; + } + } + + if (u64M == 0) + return 0; + + u64tmp = (u64FCLKO * u64P * u64M * 1000) / PllSrcClk; + u64N = u64tmp / 1000; + u64X = u64tmp % 1000; + u32FRAC = ((u64X << 24) + 500) / 1000; + + u64SSRATE = ((PllSrcClk >> 1) / (u32Fmod * 2)) - 1; + u64SLOPE = ((u64tmp * u32SR / u64SSRATE) << 24) / 100 / 1000; + + u64PllClk = (PllSrcClk * u64tmp) / u64P / u64M / 1000; + + u32Reg[0] = (u64SSRATE << VSIPLLCTL0_SSRATE_POS) | (u64M << + VSIPLLCTL0_INDIV_POS) | (u64N); + u32Reg[1] = (u64P << VSIPLLCTL1_OUTDIV_POS) | (u32FRAC << VSIPLLCTL1_FRAC_POS); + u32Reg[2] = u64SLOPE; + return u64PllClk; +} + +unsigned long CLK_SetPLLFreq(struct ma35d1_clk_pll *pll, + unsigned long PllSrcClk, + unsigned long u64PllFreq) +{ + u32 u32Reg[3] = { 0 }, val_ctl0, val_ctl1, val_ctl2; + unsigned long u64PllClk; + + val_ctl0 = __raw_readl(pll->ctl0_base); + val_ctl1 = __raw_readl(pll->ctl1_base); + val_ctl2 = __raw_readl(pll->ctl2_base); + + switch (pll->mode) { + case VSIPLL_INTEGER_MODE: + u64PllClk = CLK_CalPLLFreq_Mode0(PllSrcClk, u64PllFreq, + u32Reg); + val_ctl0 = u32Reg[0] | + (VSIPLL_INTEGER_MODE << VSIPLLCTL0_MODE_POS); + break; + case VSIPLL_FRACTIONAL_MODE: + u64PllClk = CLK_CalPLLFreq_Mode1(PllSrcClk, u64PllFreq, + u32Reg); + val_ctl0 = u32Reg[0] | + (VSIPLL_FRACTIONAL_MODE << VSIPLLCTL0_MODE_POS); + break; + case VSIPLL_SS_MODE: + u64PllClk = CLK_CalPLLFreq_Mode2(PllSrcClk, u64PllFreq, + VSIPLL_MODULATION_FREQ, + VSIPLL_SPREAD_RANGE, u32Reg); + val_ctl0 = u32Reg[0] | + (VSIPLL_SS_MODE << VSIPLLCTL0_MODE_POS); + break; + } + + val_ctl1 = VSIPLLCTL1_PD_MSK | u32Reg[1]; + val_ctl2 = u32Reg[2]; + + __raw_writel(val_ctl0, pll->ctl0_base); + __raw_writel(val_ctl1, pll->ctl1_base); + __raw_writel(val_ctl2, pll->ctl2_base); + return u64PllClk; +} + +unsigned long CLK_GetPLLFreq_VSIPLL(struct ma35d1_clk_pll *pll, + unsigned long PllSrcClk) +{ + u32 u32M, u32N, u32P, u32X, u32SR, u32FMOD; + u32 val_ctl0, val_ctl1, val_ctl2; + unsigned long u64PllClk, u64X; + + val_ctl0 = __raw_readl(pll->ctl0_base); + val_ctl1 = __raw_readl(pll->ctl1_base); + val_ctl2 = __raw_readl(pll->ctl2_base); + + if (val_ctl1 & PLLXCTL1_BP_MSK) { + u64PllClk = PllSrcClk; + return u64PllClk; + } + + if (pll->mode == VSIPLL_INTEGER_MODE) { + u32N = FIELD_GET(PLLXCTL0_FBDIV_MSK, val_ctl0); + u32M = FIELD_GET(PLLXCTL0_INDIV_MSK, val_ctl0); + u32P = FIELD_GET(PLLXCTL1_OUTDIV_MSK, val_ctl1); + + u64PllClk = PllSrcClk * u32N; + do_div(u64PllClk, u32M * u32P); + + } else if (pll->mode == VSIPLL_FRACTIONAL_MODE) { + u32N = FIELD_GET(PLLXCTL0_FBDIV_MSK, val_ctl0); + u32M = FIELD_GET(PLLXCTL0_INDIV_MSK, val_ctl0); + u32P = FIELD_GET(PLLXCTL1_OUTDIV_MSK, val_ctl1); + u32X = FIELD_GET(PLLXCTL1_FRAC_MSK, val_ctl1); + u64X = (u64) u32X; + u64X = (((u64X * 1000) + 500) >> 24); + u64PllClk = (PllSrcClk * ((u32N * 1000) + u64X)) / + 1000 / u32P / u32M; + + } else { + u32N = FIELD_GET(PLLXCTL0_FBDIV_MSK, val_ctl0); + u32M = FIELD_GET(PLLXCTL0_INDIV_MSK, val_ctl0); + u32SR = FIELD_GET(PLLXCTL0_SSRATE_MSK, val_ctl0); + u32P = FIELD_GET(PLLXCTL1_OUTDIV_MSK, val_ctl1); + u32X = FIELD_GET(PLLXCTL1_FRAC_MSK, val_ctl1); + u32FMOD = FIELD_GET(PLLXCTL2_SLOPE_MSK, val_ctl2); + u64X = (u64) u32X; + u64X = ((u64X * 1000) >> 24); + u64PllClk = (PllSrcClk * ((u32N * 1000) + u64X)) / + 1000 / u32P / u32M; + } + return u64PllClk; +} + +static int ma35d1_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct ma35d1_clk_pll *pll = to_ma35d1_clk_pll(hw); + + if ((parent_rate < VSIPLL_FREF_MIN_FREQ) || + (parent_rate > VSIPLL_FREF_MAX_FREQ)) + return 0; + + if ((pll->type == MA35D1_CAPLL) || (pll->type == MA35D1_DDRPLL)) { + pr_warn("Nuvoton MA35D1 CAPLL/DDRPLL is read only.\n"); + return -EACCES; + } + CLK_UnLockReg(pll); + pll->rate = CLK_SetPLLFreq(pll, parent_rate, rate); + CLK_LockReg(pll); + return 0; +} + +static unsigned long ma35d1_clk_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + unsigned long pllfreq; + struct ma35d1_clk_pll *pll = to_ma35d1_clk_pll(hw); + + if ((parent_rate < VSIPLL_FREF_MIN_FREQ) + || (parent_rate > VSIPLL_FREF_MAX_FREQ)) + return 0; + + switch (pll->type) { + case MA35D1_CAPLL: + pllfreq = CLK_GetPLLFreq_SMICPLL(pll, parent_rate); + break; + case MA35D1_DDRPLL: + case MA35D1_APLL: + case MA35D1_EPLL: + case MA35D1_VPLL: + pllfreq = CLK_GetPLLFreq_VSIPLL(pll, parent_rate); + break; + } + + return pllfreq; +} + +static long ma35d1_clk_pll_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + return rate; +} + +static int ma35d1_clk_pll_is_prepared(struct clk_hw *hw) +{ + struct ma35d1_clk_pll *pll = to_ma35d1_clk_pll(hw); + u32 val = __raw_readl(pll->ctl1_base); + + return (val & VSIPLLCTL1_PD_MSK) ? 0 : 1; +} + +static int ma35d1_clk_pll_prepare(struct clk_hw *hw) +{ + struct ma35d1_clk_pll *pll = to_ma35d1_clk_pll(hw); + u32 val; + + if ((pll->type == MA35D1_CAPLL) || (pll->type == MA35D1_DDRPLL)) { + pr_warn("Nuvoton MA35D1 CAPLL/DDRPLL is read only.\n"); + return -EACCES; + } + + CLK_UnLockReg(pll); + val = __raw_readl(pll->ctl1_base); + val &= ~VSIPLLCTL1_PD_MSK; + __raw_writel(val, pll->ctl1_base); + CLK_LockReg(pll); + return 0; +} + +static void ma35d1_clk_pll_unprepare(struct clk_hw *hw) +{ + struct ma35d1_clk_pll *pll = to_ma35d1_clk_pll(hw); + u32 val; + + if ((pll->type == MA35D1_CAPLL) || (pll->type == MA35D1_DDRPLL)) { + pr_warn("Nuvoton MA35D1 CAPLL/DDRPLL is read only.\n"); + } else { + val = __raw_readl(pll->ctl1_base); + val |= VSIPLLCTL1_PD_MSK; + __raw_writel(val, pll->ctl1_base); + } +} + +static const struct clk_ops ma35d1_clk_pll_ops = { + .is_prepared = ma35d1_clk_pll_is_prepared, + .prepare = ma35d1_clk_pll_prepare, + .unprepare = ma35d1_clk_pll_unprepare, + .set_rate = ma35d1_clk_pll_set_rate, + .recalc_rate = ma35d1_clk_pll_recalc_rate, + .round_rate = ma35d1_clk_pll_round_rate, +}; + +struct clk_hw *ma35d1_reg_clk_pll(enum ma35d1_pll_type type, + u8 u8mode, const char *name, + const char *parent, + unsigned long targetFreq, + void __iomem *base, + struct regmap *regmap) +{ + struct ma35d1_clk_pll *pll; + struct clk_hw *hw; + struct clk_init_data init; + int ret; + + pll = kmalloc(sizeof(*pll), GFP_KERNEL); + if (!pll) + return ERR_PTR(-ENOMEM); + + pll->type = type; + pll->mode = u8mode; + pll->rate = targetFreq; + pll->ctl0_base = base + VSIPLL_CTL0; + pll->ctl1_base = base + VSIPLL_CTL1; + pll->ctl2_base = base + VSIPLL_CTL2; + pll->regmap = regmap; + + init.name = name; + init.flags = 0; + init.parent_names = &parent; + init.num_parents = 1; + init.ops = &ma35d1_clk_pll_ops; + pll->hw.init = &init; + hw = &pll->hw; + + ret = clk_hw_register(NULL, hw); + if (ret) { + pr_err("failed to register vsi-pll clock!!!\n"); + kfree(pll); + return ERR_PTR(ret); + } + return hw; +} diff --git a/drivers/clk/nuvoton/clk-ma35d1.c b/drivers/clk/nuvoton/clk-ma35d1.c new file mode 100644 index 000000000000..ac8154458b81 --- /dev/null +++ b/drivers/clk/nuvoton/clk-ma35d1.c @@ -0,0 +1,970 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023 Nuvoton Technology Corp. + * Author: Chi-Fang Li + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "clk-ma35d1.h" + +DEFINE_SPINLOCK(ma35d1_lock); + +static const char *const ca35clk_sel_clks[] = { + "hxt", "capll", "ddrpll", "dummy" +}; + +static const char *const sysclk0_sel_clks[] = { + "epll_div2", "syspll" +}; + +static const char *const sysclk1_sel_clks[] = { + "hxt", "syspll" +}; + +static const char *const axiclk_sel_clks[] = { + "capll_div2", "capll_div4" +}; + +static const char *const ccap_sel_clks[] = { + "hxt", "vpll", "apll", "syspll" +}; + +static const char *const sdh_sel_clks[] = { + "syspll", "apll", "dummy", "dummy" +}; + +static const char *const dcu_sel_clks[] = { + "epll_div2", "syspll" +}; + +static const char *const gfx_sel_clks[] = { + "epll", "syspll" +}; + +static const char *const dbg_sel_clks[] = { + "hirc", "syspll" +}; + +static const char *const timer0_sel_clks[] = { + "hxt", "lxt", "pclk0", "dummy", "dummy", "lirc", "dummy", "hirc" +}; + +static const char *const timer1_sel_clks[] = { + "hxt", "lxt", "pclk0", "dummy", "dummy", "lirc", "dummy", "hirc" +}; + +static const char *const timer2_sel_clks[] = { + "hxt", "lxt", "pclk1", "dummy", "dummy", "lirc", "dummy", "hirc" +}; + +static const char *const timer3_sel_clks[] = { + "hxt", "lxt", "pclk1", "dummy", "dummy", "lirc", "dummy", "hirc" +}; + +static const char *const timer4_sel_clks[] = { + "hxt", "lxt", "pclk2", "dummy", "dummy", "lirc", "dummy", "hirc" +}; + +static const char *const timer5_sel_clks[] = { + "hxt", "lxt", "pclk2", "dummy", "dummy", "lirc", "dummy", "hirc" +}; + +static const char *const timer6_sel_clks[] = { + "hxt", "lxt", "pclk0", "dummy", "dummy", "lirc", "dummy", "hirc" +}; + +static const char *const timer7_sel_clks[] = { + "hxt", "lxt", "pclk0", "dummy", "dummy", "lirc", "dummy", "hirc" +}; + +static const char *const timer8_sel_clks[] = { + "hxt", "lxt", "pclk1", "dummy", "dummy", "lirc", "dummy", "hirc" +}; + +static const char *const timer9_sel_clks[] = { + "hxt", "lxt", "pclk1", "dummy", "dummy", "lirc", "dummy", "hirc" +}; + +static const char *const timer10_sel_clks[] = { + "hxt", "lxt", "pclk2", "dummy", "dummy", "lirc", "dummy", "hirc" +}; + +static const char *const timer11_sel_clks[] = { + "hxt", "lxt", "pclk2", "dummy", "dummy", "lirc", "dummy", "hirc" +}; + +static const char *const uart_sel_clks[] = { + "hxt", "sysclk1_div2", "dummy", "dummy" +}; + +static const char *const wdt0_sel_clks[] = { + "dummy", "lxt", "pclk3_div4096", "lirc" +}; + +static const char *const wdt1_sel_clks[] = { + "dummy", "lxt", "pclk3_div4096", "lirc" +}; + +static const char *const wdt2_sel_clks[] = { + "dummy", "lxt", "pclk4_div4096", "lirc" +}; + +static const char *const wwdt0_sel_clks[] = { + "dummy", "dummy", "pclk3_div4096", "lirc" +}; + +static const char *const wwdt1_sel_clks[] = { + "dummy", "dummy", "pclk3_div4096", "lirc" +}; + +static const char *const wwdt2_sel_clks[] = { + "dummy", "dummy", "pclk4_div4096", "lirc" +}; + +static const char *const spi0_sel_clks[] = { + "pclk1", "apll", "dummy", "dummy" +}; + +static const char *const spi1_sel_clks[] = { + "pclk2", "apll", "dummy", "dummy" +}; + +static const char *const spi2_sel_clks[] = { + "pclk1", "apll", "dummy", "dummy" +}; + +static const char *const spi3_sel_clks[] = { + "pclk2", "apll", "dummy", "dummy" +}; + +static const char *const qspi0_sel_clks[] = { + "pclk0", "apll", "dummy", "dummy" +}; + +static const char *const qspi1_sel_clks[] = { + "pclk0", "apll", "dummy", "dummy" +}; + +static const char *const i2s0_sel_clks[] = { + "apll", "sysclk1_div2", "dummy", "dummy" +}; + +static const char *const i2s1_sel_clks[] = { + "apll", "sysclk1_div2", "dummy", "dummy" +}; + +static const char *const can_sel_clks[] = { + "apll", "vpll" +}; + +static const char *const cko_sel_clks[] = { + "hxt", "lxt", "hirc", "lirc", "capll_div4", "syspll", + "ddrpll", "epll_div2", "apll", "vpll", "dummy", "dummy", + "dummy", "dummy", "dummy", "dummy" +}; + +static const char *const smc_sel_clks[] = { + "hxt", "pclk4" +}; + +static const char *const kpi_sel_clks[] = { + "hxt", "lxt" +}; + +static const struct clk_div_table ip_div_table[] = { + {0, 2}, {1, 4}, {2, 6}, {3, 8}, {4, 10}, + {5, 12}, {6, 14}, {7, 16}, {0, 0}, +}; + +static const struct clk_div_table eadc_div_table[] = { + {0, 2}, {1, 4}, {2, 6}, {3, 8}, {4, 10}, + {5, 12}, {6, 14}, {7, 16}, {8, 18}, + {9, 20}, {10, 22}, {11, 24}, {12, 26}, + {13, 28}, {14, 30}, {15, 32}, {0, 0}, +}; + +static struct clk_hw **hws; +static struct clk_hw_onecell_data *ma35d1_hw_data; + +static int ma35d1_clocks_probe(struct platform_device *pdev) +{ + int ret; + struct device *dev = &pdev->dev; + struct device_node *clk_node = dev->of_node; + void __iomem *clk_base; + struct regmap *regmap; + u32 pllmode[5] = { 0, 0, 0, 0, 0 }; + u32 pllfreq[5] = { 0, 0, 0, 0, 0 }; + + dev_info(&pdev->dev, "Nuvoton MA35D1 Clock Driver\n"); + ma35d1_hw_data = devm_kzalloc(&pdev->dev, struct_size(ma35d1_hw_data, + hws, CLK_MAX_IDX), GFP_KERNEL); + + if (WARN_ON(!ma35d1_hw_data)) + return -ENOMEM; + + ma35d1_hw_data->num = CLK_MAX_IDX; + hws = ma35d1_hw_data->hws; + + clk_node = of_find_compatible_node(NULL, NULL, "nuvoton,ma35d1-clk"); + clk_base = of_iomap(clk_node, 0); + of_node_put(clk_node); + if (!clk_base) { + pr_err("%s: could not map region\n", __func__); + return -ENOMEM; + } + regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, + "nuvoton,sys"); + if (IS_ERR(regmap)) + pr_warn("%s: Unable to get syscon\n", __func__); + + /* clock sources */ + hws[HXT] = ma35d1_clk_fixed("hxt", 24000000); + hws[HXT_GATE] = ma35d1_clk_gate("hxt_gate", "hxt", + clk_base + REG_CLK_PWRCTL, 0); + hws[LXT] = ma35d1_clk_fixed("lxt", 32768); + hws[LXT_GATE] = ma35d1_clk_gate("lxt_gate", "lxt", + clk_base + REG_CLK_PWRCTL, 1); + hws[HIRC] = ma35d1_clk_fixed("hirc", 12000000); + hws[HIRC_GATE] = ma35d1_clk_gate("hirc_gate", "hirc", + clk_base + REG_CLK_PWRCTL, 2); + hws[LIRC] = ma35d1_clk_fixed("lirc", 32000); + hws[LIRC_GATE] = ma35d1_clk_gate("lirc_gate", "lirc", + clk_base + REG_CLK_PWRCTL, 3); + + /* PLL */ + of_property_read_u32_array(clk_node, "clock-pll-mode", pllmode, + ARRAY_SIZE(pllmode)); + of_property_read_u32_array(clk_node, "assigned-clock-rates", pllfreq, + ARRAY_SIZE(pllfreq)); + + /* SMIC PLL */ + hws[CAPLL] = ma35d1_reg_clk_pll(MA35D1_CAPLL, pllmode[0], "capll", + "hxt", pllfreq[0], + clk_base + REG_CLK_PLL0CTL0, regmap); + hws[SYSPLL] = ma35d1_clk_fixed("syspll", 180000000); + + /* VSI PLL */ + hws[DDRPLL] = ma35d1_reg_clk_pll(MA35D1_DDRPLL, pllmode[1], "ddrpll", + "hxt", pllfreq[1], + clk_base + REG_CLK_PLL2CTL0, regmap); + hws[APLL] = ma35d1_reg_clk_pll(MA35D1_APLL, pllmode[2], "apll", "hxt", + pllfreq[2], clk_base + REG_CLK_PLL3CTL0, + regmap); + hws[EPLL] = ma35d1_reg_clk_pll(MA35D1_EPLL, pllmode[3], "epll", "hxt", + pllfreq[3], clk_base + REG_CLK_PLL4CTL0, + regmap); + hws[VPLL] = ma35d1_reg_clk_pll(MA35D1_VPLL, pllmode[4], "vpll", "hxt", + pllfreq[4], clk_base + REG_CLK_PLL5CTL0, + regmap); + hws[EPLL_DIV2] = ma35d1_clk_fixed_factor("epll_div2", "epll", 1, 2); + hws[EPLL_DIV4] = ma35d1_clk_fixed_factor("epll_div4", "epll", 1, 4); + hws[EPLL_DIV8] = ma35d1_clk_fixed_factor("epll_div8", "epll", 1, 8); + + /* CA35 */ + hws[CA35CLK_MUX] = ma35d1_clk_mux("ca35clk_mux", + clk_base + REG_CLK_CLKSEL0, 0, + 2, ca35clk_sel_clks, + ARRAY_SIZE(ca35clk_sel_clks)); + + /* AXI */ + hws[AXICLK_DIV2] = ma35d1_clk_fixed_factor("capll_div2", "ca35clk_mux", + 1, 2); + hws[AXICLK_DIV4] = ma35d1_clk_fixed_factor("capll_div4", "ca35clk_mux", + 1, 4); + hws[AXICLK_MUX] = ma35d1_clk_mux("axiclk_mux", + clk_base + REG_CLK_CLKDIV0, + 26, 1, axiclk_sel_clks, + ARRAY_SIZE(axiclk_sel_clks)); + + /* SYSCLK0 & SYSCLK1 */ + hws[SYSCLK0_MUX] = ma35d1_clk_mux("sysclk0_mux", + clk_base + REG_CLK_CLKSEL0, + 2, 1, sysclk0_sel_clks, + ARRAY_SIZE(sysclk0_sel_clks)); + hws[SYSCLK1_MUX] = ma35d1_clk_mux("sysclk1_mux", + clk_base + REG_CLK_CLKSEL0, + 4, 1, sysclk1_sel_clks, + ARRAY_SIZE(sysclk1_sel_clks)); + hws[SYSCLK1_DIV2] = ma35d1_clk_fixed_factor("sysclk1_div2", + "sysclk1_mux", 1, 2); + + /* HCLK0~3 & PCLK0~4 */ + hws[HCLK0] = ma35d1_clk_fixed_factor("hclk0", "sysclk1_mux", 1, 1); + hws[HCLK1] = ma35d1_clk_fixed_factor("hclk1", "sysclk1_mux", 1, 1); + hws[HCLK2] = ma35d1_clk_fixed_factor("hclk2", "sysclk1_mux", 1, 1); + hws[PCLK0] = ma35d1_clk_fixed_factor("pclk0", "sysclk1_mux", 1, 1); + hws[PCLK1] = ma35d1_clk_fixed_factor("pclk1", "sysclk1_mux", 1, 1); + hws[PCLK2] = ma35d1_clk_fixed_factor("pclk2", "sysclk1_mux", 1, 1); + + hws[HCLK3] = ma35d1_clk_fixed_factor("hclk3", "sysclk1_mux", 1, 2); + hws[PCLK3] = ma35d1_clk_fixed_factor("pclk3", "sysclk1_mux", 1, 2); + hws[PCLK4] = ma35d1_clk_fixed_factor("pclk4", "sysclk1_mux", 1, 2); + + hws[USBPHY0] = ma35d1_clk_fixed("usbphy0", 480000000); + hws[USBPHY1] = ma35d1_clk_fixed("usbphy1", 480000000); + + /* DDR */ + hws[DDR0_GATE] = ma35d1_clk_gate("ddr0_gate", "ddrpll", + clk_base + REG_CLK_SYSCLK0, 4); + hws[DDR6_GATE] = ma35d1_clk_gate("ddr6_gate", "ddrpll", + clk_base + REG_CLK_SYSCLK0, 5); + + /* CAN0 */ + hws[CAN0_MUX] = ma35d1_clk_mux("can0_mux", clk_base + REG_CLK_CLKSEL4, + 16, 1, can_sel_clks, + ARRAY_SIZE(can_sel_clks)); + hws[CAN0_DIV] = ma35d1_clk_divider_table("can0_div", "can0_mux", + clk_base + REG_CLK_CLKDIV0, + 0, 3, ip_div_table); + hws[CAN0_GATE] = ma35d1_clk_gate("can0_gate", "can0_div", + clk_base + REG_CLK_SYSCLK0, 8); + + /* CAN1 */ + hws[CAN1_MUX] = ma35d1_clk_mux("can1_mux", clk_base + REG_CLK_CLKSEL4, + 17, 1, can_sel_clks, + ARRAY_SIZE(can_sel_clks)); + hws[CAN1_DIV] = ma35d1_clk_divider_table("can1_div", "can1_mux", + clk_base + REG_CLK_CLKDIV0, + 4, 3, ip_div_table); + hws[CAN1_GATE] = ma35d1_clk_gate("can1_gate", "can1_div", + clk_base + REG_CLK_SYSCLK0, 9); + + /* CAN2 */ + hws[CAN2_MUX] = ma35d1_clk_mux("can2_mux", clk_base + REG_CLK_CLKSEL4, + 18, 1, can_sel_clks, + ARRAY_SIZE(can_sel_clks)); + hws[CAN2_DIV] = ma35d1_clk_divider_table("can2_div", "can2_mux", + clk_base + REG_CLK_CLKDIV0, + 8, 3, ip_div_table); + hws[CAN2_GATE] = ma35d1_clk_gate("can2_gate", "can2_div", + clk_base + REG_CLK_SYSCLK0, 10); + + /* CAN3 */ + hws[CAN3_MUX] = ma35d1_clk_mux("can3_mux", clk_base + REG_CLK_CLKSEL4, + 19, 1, can_sel_clks, + ARRAY_SIZE(can_sel_clks)); + hws[CAN3_DIV] = ma35d1_clk_divider_table("can3_div", "can3_mux", + clk_base + REG_CLK_CLKDIV0, + 12, 3, ip_div_table); + hws[CAN3_GATE] = ma35d1_clk_gate("can3_gate", "can3_div", + clk_base + REG_CLK_SYSCLK0, 11); + + /* SDH0 */ + hws[SDH0_MUX] = ma35d1_clk_mux("sdh0_mux", clk_base + REG_CLK_CLKSEL0, + 16, 2, sdh_sel_clks, + ARRAY_SIZE(sdh_sel_clks)); + hws[SDH0_GATE] = ma35d1_clk_gate("sdh0_gate", "sdh0_mux", + clk_base + REG_CLK_SYSCLK0, 16); + + /* SDH1 */ + hws[SDH1_MUX] = ma35d1_clk_mux("sdh1_mux", clk_base + REG_CLK_CLKSEL0, + 18, 2, sdh_sel_clks, + ARRAY_SIZE(sdh_sel_clks)); + hws[SDH1_GATE] = ma35d1_clk_gate("sdh1_gate", "sdh1_mux", + clk_base + REG_CLK_SYSCLK0, 17); + + /* NAND */ + hws[NAND_GATE] = ma35d1_clk_gate("nand_gate", "hclk1", + clk_base + REG_CLK_SYSCLK0, 18); + + /* USB */ + hws[USBD_GATE] = ma35d1_clk_gate("usbd_gate", "usbphy0", + clk_base + REG_CLK_SYSCLK0, 19); + hws[USBH_GATE] = ma35d1_clk_gate("usbh_gate", "usbphy0", + clk_base + REG_CLK_SYSCLK0, 20); + hws[HUSBH0_GATE] = ma35d1_clk_gate("husbh0_gate", "usbphy0", + clk_base + REG_CLK_SYSCLK0, 21); + hws[HUSBH1_GATE] = ma35d1_clk_gate("husbh1_gate", "usbphy0", + clk_base + REG_CLK_SYSCLK0, 22); + + /* GFX */ + hws[GFX_MUX] = ma35d1_clk_mux("gfx_mux", clk_base + REG_CLK_CLKSEL0, + 26, 1, gfx_sel_clks, + ARRAY_SIZE(gfx_sel_clks)); + hws[GFX_GATE] = ma35d1_clk_gate("gfx_gate", "gfx_mux", + clk_base + REG_CLK_SYSCLK0, 24); + + /* VC8K */ + hws[VC8K_GATE] = ma35d1_clk_gate("vc8k_gate", "sysclk0_mux", + clk_base + REG_CLK_SYSCLK0, 25); + + /* DCU */ + hws[DCU_MUX] = ma35d1_clk_mux("dcu_mux", clk_base + REG_CLK_CLKSEL0, + 24, 1, dcu_sel_clks, + ARRAY_SIZE(dcu_sel_clks)); + hws[DCU_GATE] = ma35d1_clk_gate("dcu_gate", "dcu_mux", + clk_base + REG_CLK_SYSCLK0, 26); + + /* DCUP */ + hws[DCUP_DIV] = ma35d1_clk_divider_table("dcup_div", "vpll", + clk_base + REG_CLK_CLKDIV0, + 16, 3, ip_div_table); + + /* EMAC0 */ + hws[EMAC0_GATE] = ma35d1_clk_gate("emac0_gate", "epll_div2", + clk_base + REG_CLK_SYSCLK0, 27); + + /* EMAC1 */ + hws[EMAC1_GATE] = ma35d1_clk_gate("emac1_gate", "epll_div2", + clk_base + REG_CLK_SYSCLK0, 28); + + /* CCAP0 */ + hws[CCAP0_MUX] = ma35d1_clk_mux("ccap0_mux", + clk_base + REG_CLK_CLKSEL0, + 12, 1, ccap_sel_clks, + ARRAY_SIZE(ccap_sel_clks)); + hws[CCAP0_DIV] = ma35d1_clk_divider("ccap0_div", "ccap0_mux", + clk_base + REG_CLK_CLKDIV1, 8, 4); + hws[CCAP0_GATE] = ma35d1_clk_gate("ccap0_gate", "ccap0_div", + clk_base + REG_CLK_SYSCLK0, 29); + + /* CCAP1 */ + hws[CCAP1_MUX] = ma35d1_clk_mux("ccap1_mux", + clk_base + REG_CLK_CLKSEL0, + 14, 1, ccap_sel_clks, + ARRAY_SIZE(ccap_sel_clks)); + hws[CCAP1_DIV] = ma35d1_clk_divider("ccap1_div", "ccap1_mux", + clk_base + REG_CLK_CLKDIV1, + 12, 4); + hws[CCAP1_GATE] = ma35d1_clk_gate("ccap1_gate", "ccap1_div", + clk_base + REG_CLK_SYSCLK0, 30); + + /* PDMA0~3 */ + hws[PDMA0_GATE] = ma35d1_clk_gate("pdma0_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 0); + hws[PDMA1_GATE] = ma35d1_clk_gate("pdma1_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 1); + hws[PDMA2_GATE] = ma35d1_clk_gate("pdma2_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 2); + hws[PDMA3_GATE] = ma35d1_clk_gate("pdma3_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 3); + + /* WH0~1 */ + hws[WH0_GATE] = ma35d1_clk_gate("wh0_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 4); + hws[WH1_GATE] = ma35d1_clk_gate("wh1_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 5); + + /* HWS */ + hws[HWS_GATE] = ma35d1_clk_gate("hws_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 6); + + /* EBI */ + hws[EBI_GATE] = ma35d1_clk_gate("ebi_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 7); + + /* SRAM0~1 */ + hws[SRAM0_GATE] = ma35d1_clk_gate("sram0_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 8); + hws[SRAM1_GATE] = ma35d1_clk_gate("sram1_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 9); + + /* ROM */ + hws[ROM_GATE] = ma35d1_clk_gate("rom_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 10); + + /* TRA */ + hws[TRA_GATE] = ma35d1_clk_gate("tra_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 11); + + /* DBG */ + hws[DBG_MUX] = ma35d1_clk_mux("dbg_mux", clk_base + REG_CLK_CLKSEL0, + 27, 1, dbg_sel_clks, + ARRAY_SIZE(dbg_sel_clks)); + hws[DBG_GATE] = ma35d1_clk_gate("dbg_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 12); + + /* CLKO */ + hws[CKO_MUX] = ma35d1_clk_mux("cko_mux", clk_base + REG_CLK_CLKSEL4, + 24, 4, cko_sel_clks, + ARRAY_SIZE(cko_sel_clks)); + hws[CKO_DIV] = ma35d1_clk_divider_pow2("cko_div", "cko_mux", + clk_base + REG_CLK_CLKOCTL, + 0, 4); + hws[CKO_GATE] = ma35d1_clk_gate("cko_gate", "cko_div", + clk_base + REG_CLK_SYSCLK1, 13); + + /* GTMR */ + hws[GTMR_GATE] = ma35d1_clk_gate("gtmr_gate", "hirc", + clk_base + REG_CLK_SYSCLK1, 14); + + /* GPIO */ + hws[GPA_GATE] = ma35d1_clk_gate("gpa_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 16); + hws[GPB_GATE] = ma35d1_clk_gate("gpb_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 17); + hws[GPC_GATE] = ma35d1_clk_gate("gpc_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 18); + hws[GPD_GATE] = ma35d1_clk_gate("gpd_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 19); + hws[GPE_GATE] = ma35d1_clk_gate("gpe_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 20); + hws[GPF_GATE] = ma35d1_clk_gate("gpf_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 21); + hws[GPG_GATE] = ma35d1_clk_gate("gpg_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 22); + hws[GPH_GATE] = ma35d1_clk_gate("gph_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 23); + hws[GPI_GATE] = ma35d1_clk_gate("gpi_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 24); + hws[GPJ_GATE] = ma35d1_clk_gate("gpj_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 25); + hws[GPK_GATE] = ma35d1_clk_gate("gpk_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 26); + hws[GPL_GATE] = ma35d1_clk_gate("gpl_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 27); + hws[GPM_GATE] = ma35d1_clk_gate("gpm_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 28); + hws[GPN_GATE] = ma35d1_clk_gate("gpn_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 29); + + /* TIMER0~11 */ + hws[TMR0_MUX] = ma35d1_clk_mux("tmr0_mux", clk_base + REG_CLK_CLKSEL1, + 0, 3, timer0_sel_clks, + ARRAY_SIZE(timer0_sel_clks)); + hws[TMR0_GATE] = ma35d1_clk_gate("tmr0_gate", "tmr0_mux", + clk_base + REG_CLK_APBCLK0, 0); + hws[TMR1_MUX] = ma35d1_clk_mux("tmr1_mux", clk_base + REG_CLK_CLKSEL1, + 4, 3, timer1_sel_clks, + ARRAY_SIZE(timer1_sel_clks)); + hws[TMR1_GATE] = ma35d1_clk_gate("tmr1_gate", "tmr1_mux", + clk_base + REG_CLK_APBCLK0, 1); + hws[TMR2_MUX] = ma35d1_clk_mux("tmr2_mux", clk_base + REG_CLK_CLKSEL1, + 8, 3, timer2_sel_clks, + ARRAY_SIZE(timer2_sel_clks)); + hws[TMR2_GATE] = ma35d1_clk_gate("tmr2_gate", "tmr2_mux", + clk_base + REG_CLK_APBCLK0, 2); + hws[TMR3_MUX] = ma35d1_clk_mux("tmr3_mux", clk_base + REG_CLK_CLKSEL1, + 12, 3, timer3_sel_clks, + ARRAY_SIZE(timer3_sel_clks)); + hws[TMR3_GATE] = ma35d1_clk_gate("tmr3_gate", "tmr3_mux", + clk_base + REG_CLK_APBCLK0, 3); + hws[TMR4_MUX] = ma35d1_clk_mux("tmr4_mux", clk_base + REG_CLK_CLKSEL1, + 16, 3, timer4_sel_clks, + ARRAY_SIZE(timer4_sel_clks)); + hws[TMR4_GATE] = ma35d1_clk_gate("tmr4_gate", "tmr4_mux", + clk_base + REG_CLK_APBCLK0, 4); + hws[TMR5_MUX] = ma35d1_clk_mux("tmr5_mux", clk_base + REG_CLK_CLKSEL1, + 20, 3, timer5_sel_clks, + ARRAY_SIZE(timer5_sel_clks)); + hws[TMR5_GATE] = ma35d1_clk_gate("tmr5_gate", "tmr5_mux", + clk_base + REG_CLK_APBCLK0, 5); + hws[TMR6_MUX] = ma35d1_clk_mux("tmr6_mux", clk_base + REG_CLK_CLKSEL1, + 24, 3, timer6_sel_clks, + ARRAY_SIZE(timer6_sel_clks)); + hws[TMR6_GATE] = ma35d1_clk_gate("tmr6_gate", "tmr6_mux", + clk_base + REG_CLK_APBCLK0, 6); + hws[TMR7_MUX] = ma35d1_clk_mux("tmr7_mux", clk_base + REG_CLK_CLKSEL1, + 28, 3, timer7_sel_clks, + ARRAY_SIZE(timer7_sel_clks)); + hws[TMR7_GATE] = ma35d1_clk_gate("tmr7_gate", "tmr7_mux", + clk_base + REG_CLK_APBCLK0, 7); + hws[TMR8_MUX] = ma35d1_clk_mux("tmr8_mux", clk_base + REG_CLK_CLKSEL2, + 0, 3, timer8_sel_clks, + ARRAY_SIZE(timer8_sel_clks)); + hws[TMR8_GATE] = ma35d1_clk_gate("tmr8_gate", "tmr8_mux", + clk_base + REG_CLK_APBCLK0, 8); + hws[TMR9_MUX] = ma35d1_clk_mux("tmr9_mux", clk_base + REG_CLK_CLKSEL2, + 4, 3, timer9_sel_clks, + ARRAY_SIZE(timer9_sel_clks)); + hws[TMR9_GATE] = ma35d1_clk_gate("tmr9_gate", "tmr9_mux", + clk_base + REG_CLK_APBCLK0, 9); + hws[TMR10_MUX] = ma35d1_clk_mux("tmr10_mux", + clk_base + REG_CLK_CLKSEL2, + 8, 3, timer10_sel_clks, + ARRAY_SIZE(timer10_sel_clks)); + hws[TMR10_GATE] = ma35d1_clk_gate("tmr10_gate", "tmr10_mux", + clk_base + REG_CLK_APBCLK0, 10); + hws[TMR11_MUX] = ma35d1_clk_mux("tmr11_mux", + clk_base + REG_CLK_CLKSEL2, + 12, 3, timer11_sel_clks, + ARRAY_SIZE(timer11_sel_clks)); + hws[TMR11_GATE] = ma35d1_clk_gate("tmr11_gate", "tmr11_mux", + clk_base + REG_CLK_APBCLK0, 11); + + /* UART0~16 */ + hws[UART0_MUX] = ma35d1_clk_mux("uart0_mux", + clk_base + REG_CLK_CLKSEL2, + 16, 2, uart_sel_clks, + ARRAY_SIZE(uart_sel_clks)); + hws[UART0_DIV] = ma35d1_clk_divider("uart0_div", "uart0_mux", + clk_base + REG_CLK_CLKDIV1, + 16, 4); + hws[UART0_GATE] = ma35d1_clk_gate("uart0_gate", "uart0_div", + clk_base + REG_CLK_APBCLK0, 12); + hws[UART1_MUX] = ma35d1_clk_mux("uart1_mux", + clk_base + REG_CLK_CLKSEL2, + 18, 2, uart_sel_clks, + ARRAY_SIZE(uart_sel_clks)); + hws[UART1_DIV] = ma35d1_clk_divider("uart1_div", "uart1_mux", + clk_base + REG_CLK_CLKDIV1, + 20, 4); + hws[UART1_GATE] = ma35d1_clk_gate("uart1_gate", "uart1_div", + clk_base + REG_CLK_APBCLK0, 13); + hws[UART2_MUX] = ma35d1_clk_mux("uart2_mux", + clk_base + REG_CLK_CLKSEL2, + 20, 2, uart_sel_clks, + ARRAY_SIZE(uart_sel_clks)); + hws[UART2_DIV] = ma35d1_clk_divider("uart2_div", "uart2_mux", + clk_base + REG_CLK_CLKDIV1, + 24, 4); + hws[UART2_GATE] = ma35d1_clk_gate("uart2_gate", "uart2_div", + clk_base + REG_CLK_APBCLK0, 14); + hws[UART3_MUX] = ma35d1_clk_mux("uart3_mux", + clk_base + REG_CLK_CLKSEL2, + 22, 2, uart_sel_clks, + ARRAY_SIZE(uart_sel_clks)); + hws[UART3_DIV] = ma35d1_clk_divider("uart3_div", "uart3_mux", + clk_base + REG_CLK_CLKDIV1, + 28, 4); + hws[UART3_GATE] = ma35d1_clk_gate("uart3_gate", "uart3_div", + clk_base + REG_CLK_APBCLK0, 15); + hws[UART4_MUX] = ma35d1_clk_mux("uart4_mux", + clk_base + REG_CLK_CLKSEL2, + 24, 2, uart_sel_clks, + ARRAY_SIZE(uart_sel_clks)); + hws[UART4_DIV] = ma35d1_clk_divider("uart4_div", "uart4_mux", + clk_base + REG_CLK_CLKDIV2, + 0, 4); + hws[UART4_GATE] = ma35d1_clk_gate("uart4_gate", "uart4_div", + clk_base + REG_CLK_APBCLK0, 16); + hws[UART5_MUX] = ma35d1_clk_mux("uart5_mux", + clk_base + REG_CLK_CLKSEL2, + 26, 2, uart_sel_clks, + ARRAY_SIZE(uart_sel_clks)); + hws[UART5_DIV] = ma35d1_clk_divider("uart5_div", "uart5_mux", + clk_base + REG_CLK_CLKDIV2, + 4, 4); + hws[UART5_GATE] = ma35d1_clk_gate("uart5_gate", "uart5_div", + clk_base + REG_CLK_APBCLK0, 17); + hws[UART6_MUX] = ma35d1_clk_mux("uart6_mux", + clk_base + REG_CLK_CLKSEL2, + 28, 2, uart_sel_clks, + ARRAY_SIZE(uart_sel_clks)); + hws[UART6_DIV] = ma35d1_clk_divider("uart6_div", "uart6_mux", + clk_base + REG_CLK_CLKDIV2, + 8, 4); + hws[UART6_GATE] = ma35d1_clk_gate("uart6_gate", "uart6_div", + clk_base + REG_CLK_APBCLK0, 18); + hws[UART7_MUX] = ma35d1_clk_mux("uart7_mux", + clk_base + REG_CLK_CLKSEL2, + 30, 2, uart_sel_clks, + ARRAY_SIZE(uart_sel_clks)); + hws[UART7_DIV] = ma35d1_clk_divider("uart7_div", "uart7_mux", + clk_base + REG_CLK_CLKDIV2, + 12, 4); + hws[UART7_GATE] = ma35d1_clk_gate("uart7_gate", "uart7_div", + clk_base + REG_CLK_APBCLK0, 19); + hws[UART8_MUX] = ma35d1_clk_mux("uart8_mux", + clk_base + REG_CLK_CLKSEL3, + 0, 2, uart_sel_clks, + ARRAY_SIZE(uart_sel_clks)); + hws[UART8_DIV] = ma35d1_clk_divider("uart8_div", "uart8_mux", + clk_base + REG_CLK_CLKDIV2, + 16, 4); + hws[UART8_GATE] = ma35d1_clk_gate("uart8_gate", "uart8_div", + clk_base + REG_CLK_APBCLK0, 20); + hws[UART9_MUX] = ma35d1_clk_mux("uart9_mux", + clk_base + REG_CLK_CLKSEL3, + 2, 2, uart_sel_clks, + ARRAY_SIZE(uart_sel_clks)); + hws[UART9_DIV] = ma35d1_clk_divider("uart9_div", "uart9_mux", + clk_base + REG_CLK_CLKDIV2, + 20, 4); + hws[UART9_GATE] = ma35d1_clk_gate("uart9_gate", "uart9_div", + clk_base + REG_CLK_APBCLK0, 21); + hws[UART10_MUX] = ma35d1_clk_mux("uart10_mux", + clk_base + REG_CLK_CLKSEL3, + 4, 2, uart_sel_clks, + ARRAY_SIZE(uart_sel_clks)); + hws[UART10_DIV] = ma35d1_clk_divider("uart10_div", "uart10_mux", + clk_base + REG_CLK_CLKDIV2, + 24, 4); + hws[UART10_GATE] = ma35d1_clk_gate("uart10_gate", "uart10_div", + clk_base + REG_CLK_APBCLK0, 22); + hws[UART11_MUX] = ma35d1_clk_mux("uart11_mux", + clk_base + REG_CLK_CLKSEL3, + 6, 2, uart_sel_clks, + ARRAY_SIZE(uart_sel_clks)); + hws[UART11_DIV] = ma35d1_clk_divider("uart11_div", "uart11_mux", + clk_base + REG_CLK_CLKDIV2, + 28, 4); + hws[UART11_GATE] = ma35d1_clk_gate("uart11_gate", "uart11_div", + clk_base + REG_CLK_APBCLK0, 23); + hws[UART12_MUX] = ma35d1_clk_mux("uart12_mux", + clk_base + REG_CLK_CLKSEL3, + 8, 2, uart_sel_clks, + ARRAY_SIZE(uart_sel_clks)); + hws[UART12_DIV] = ma35d1_clk_divider("uart12_div", "uart12_mux", + clk_base + REG_CLK_CLKDIV3, + 0, 4); + hws[UART12_GATE] = ma35d1_clk_gate("uart12_gate", "uart12_div", + clk_base + REG_CLK_APBCLK0, 24); + hws[UART13_MUX] = ma35d1_clk_mux("uart13_mux", + clk_base + REG_CLK_CLKSEL3, + 10, 2, uart_sel_clks, + ARRAY_SIZE(uart_sel_clks)); + hws[UART13_DIV] = ma35d1_clk_divider("uart13_div", "uart13_mux", + clk_base + REG_CLK_CLKDIV3, + 4, 4); + hws[UART13_GATE] = ma35d1_clk_gate("uart13_gate", "uart13_div", + clk_base + REG_CLK_APBCLK0, 25); + hws[UART14_MUX] = ma35d1_clk_mux("uart14_mux", + clk_base + REG_CLK_CLKSEL3, + 12, 2, uart_sel_clks, + ARRAY_SIZE(uart_sel_clks)); + hws[UART14_DIV] = ma35d1_clk_divider("uart14_div", "uart14_mux", + clk_base + REG_CLK_CLKDIV3, + 8, 4); + hws[UART14_GATE] = ma35d1_clk_gate("uart14_gate", "uart14_div", + clk_base + REG_CLK_APBCLK0, 26); + hws[UART15_MUX] = ma35d1_clk_mux("uart15_mux", + clk_base + REG_CLK_CLKSEL3, + 14, 2, uart_sel_clks, + ARRAY_SIZE(uart_sel_clks)); + hws[UART15_DIV] = ma35d1_clk_divider("uart15_div", "uart15_mux", + clk_base + REG_CLK_CLKDIV3, + 12, 4); + hws[UART15_GATE] = ma35d1_clk_gate("uart15_gate", "uart15_div", + clk_base + REG_CLK_APBCLK0, 27); + hws[UART16_MUX] = ma35d1_clk_mux("uart16_mux", + clk_base + REG_CLK_CLKSEL3, + 16, 2, uart_sel_clks, + ARRAY_SIZE(uart_sel_clks)); + hws[UART16_DIV] = ma35d1_clk_divider("uart16_div", "uart16_mux", + clk_base + REG_CLK_CLKDIV3, + 16, 4); + hws[UART16_GATE] = ma35d1_clk_gate("uart16_gate", "uart16_div", + clk_base + REG_CLK_APBCLK0, 28); + + /* RTC */ + hws[RTC_GATE] = ma35d1_clk_gate("rtc_gate", "lxt", + clk_base + REG_CLK_APBCLK0, 29); + + /* DDRP */ + hws[DDR_GATE] = ma35d1_clk_gate("ddr_gate", "ddrpll", + clk_base + REG_CLK_APBCLK0, 30); + + /* KPI */ + hws[KPI_MUX] = ma35d1_clk_mux("kpi_mux", clk_base + REG_CLK_CLKSEL4, + 30, 1, kpi_sel_clks, + ARRAY_SIZE(kpi_sel_clks)); + hws[KPI_DIV] = ma35d1_clk_divider("kpi_div", "kpi_mux", + clk_base + REG_CLK_CLKDIV4, + 24, 8); + hws[KPI_GATE] = ma35d1_clk_gate("kpi_gate", "kpi_div", + clk_base + REG_CLK_APBCLK0, 31); + + /* I2C0~5 */ + hws[I2C0_GATE] = ma35d1_clk_gate("i2c0_gate", "pclk0", + clk_base + REG_CLK_APBCLK1, 0); + hws[I2C1_GATE] = ma35d1_clk_gate("i2c1_gate", "pclk1", + clk_base + REG_CLK_APBCLK1, 1); + hws[I2C2_GATE] = ma35d1_clk_gate("i2c2_gate", "pclk2", + clk_base + REG_CLK_APBCLK1, 2); + hws[I2C3_GATE] = ma35d1_clk_gate("i2c3_gate", "pclk0", + clk_base + REG_CLK_APBCLK1, 3); + hws[I2C4_GATE] = ma35d1_clk_gate("i2c4_gate", "pclk1", + clk_base + REG_CLK_APBCLK1, 4); + hws[I2C5_GATE] = ma35d1_clk_gate("i2c5_gate", "pclk2", + clk_base + REG_CLK_APBCLK1, 5); + + /* QSPI0~1 */ + hws[QSPI0_MUX] = ma35d1_clk_mux("qspi0_mux", + clk_base + REG_CLK_CLKSEL4, + 8, 2, qspi0_sel_clks, + ARRAY_SIZE(qspi0_sel_clks)); + hws[QSPI0_GATE] = ma35d1_clk_gate("qspi0_gate", "qspi0_mux", + clk_base + REG_CLK_APBCLK1, 6); + hws[QSPI1_MUX] = ma35d1_clk_mux("qspi1_mux", + clk_base + REG_CLK_CLKSEL4, + 10, 2, qspi1_sel_clks, + ARRAY_SIZE(qspi1_sel_clks)); + hws[QSPI1_GATE] = ma35d1_clk_gate("qspi1_gate", "qspi1_mux", + clk_base + REG_CLK_APBCLK1, 7); + + /* SMC0~1 */ + hws[SMC0_MUX] = ma35d1_clk_mux("smc0_mux", + clk_base + REG_CLK_CLKSEL4, + 28, 1, smc_sel_clks, + ARRAY_SIZE(smc_sel_clks)); + hws[SMC0_DIV] = ma35d1_clk_divider("smc0_div", "smc0_mux", + clk_base + REG_CLK_CLKDIV1, + 0, 4); + hws[SMC0_GATE] = ma35d1_clk_gate("smc0_gate", "smc0_div", + clk_base + REG_CLK_APBCLK1, 12); + + hws[SMC1_MUX] = ma35d1_clk_mux("smc1_mux", + clk_base + REG_CLK_CLKSEL4, + 29, 1, smc_sel_clks, + ARRAY_SIZE(smc_sel_clks)); + hws[SMC1_DIV] = ma35d1_clk_divider("smc1_div", "smc1_mux", + clk_base + REG_CLK_CLKDIV1, + 4, 4); + hws[SMC1_GATE] = ma35d1_clk_gate("smc1_gate", "smc1_div", + clk_base + REG_CLK_APBCLK1, 13); + + /* WDT0~2 */ + hws[WDT0_MUX] = ma35d1_clk_mux("wdt0_mux", + clk_base + REG_CLK_CLKSEL3, + 20, 2, wdt0_sel_clks, + ARRAY_SIZE(wdt0_sel_clks)); + hws[WDT0_GATE] = ma35d1_clk_gate("wdt0_gate", "wdt0_mux", + clk_base + REG_CLK_APBCLK1, 16); + hws[WDT1_MUX] = ma35d1_clk_mux("wdt1_mux", + clk_base + REG_CLK_CLKSEL3, + 24, 2, wdt1_sel_clks, + ARRAY_SIZE(wdt1_sel_clks)); + hws[WDT1_GATE] = ma35d1_clk_gate("wdt1_gate", "wdt1_mux", + clk_base + REG_CLK_APBCLK1, 17); + hws[WDT2_MUX] = ma35d1_clk_mux("wdt2_mux", + clk_base + REG_CLK_CLKSEL3, + 28, 2, wdt2_sel_clks, + ARRAY_SIZE(wdt2_sel_clks)); + hws[WDT2_GATE] = ma35d1_clk_gate("wdt2_gate", "wdt2_mux", + clk_base + REG_CLK_APBCLK1, 18); + + /* WWDT0~2 */ + hws[WWDT0_MUX] = ma35d1_clk_mux("wwdt0_mux", + clk_base + REG_CLK_CLKSEL3, + 22, 2, wwdt0_sel_clks, + ARRAY_SIZE(wwdt0_sel_clks)); + hws[WWDT1_MUX] = ma35d1_clk_mux("wwdt1_mux", + clk_base + REG_CLK_CLKSEL3, + 26, 2, wwdt1_sel_clks, + ARRAY_SIZE(wwdt1_sel_clks)); + hws[WWDT2_MUX] = ma35d1_clk_mux("wwdt2_mux", + clk_base + REG_CLK_CLKSEL3, + 30, 2, wwdt2_sel_clks, + ARRAY_SIZE(wwdt2_sel_clks)); + + /* EPWM0~2 */ + hws[EPWM0_GATE] = ma35d1_clk_gate("epwm0_gate", "pclk1", + clk_base + REG_CLK_APBCLK1, 24); + hws[EPWM1_GATE] = ma35d1_clk_gate("epwm1_gate", "pclk2", + clk_base + REG_CLK_APBCLK1, 25); + hws[EPWM2_GATE] = ma35d1_clk_gate("epwm2_gate", "pclk1", + clk_base + REG_CLK_APBCLK1, 26); + + /* I2S0~1 */ + hws[I2S0_MUX] = ma35d1_clk_mux("i2s0_mux", + clk_base + REG_CLK_CLKSEL4, + 12, 2, i2s0_sel_clks, + ARRAY_SIZE(i2s0_sel_clks)); + hws[I2S0_GATE] = ma35d1_clk_gate("i2s0_gate", "i2s0_mux", + clk_base + REG_CLK_APBCLK2, 0); + hws[I2S1_MUX] = ma35d1_clk_mux("i2s1_mux", + clk_base + REG_CLK_CLKSEL4, + 14, 2, i2s1_sel_clks, + ARRAY_SIZE(i2s1_sel_clks)); + hws[I2S1_GATE] = ma35d1_clk_gate("i2s1_gate", "i2s1_mux", + clk_base + REG_CLK_APBCLK2, 1); + + /* SSMCC */ + hws[SSMCC_GATE] = ma35d1_clk_gate("ssmcc_gate", "pclk3", + clk_base + REG_CLK_APBCLK2, 2); + + /* SSPCC */ + hws[SSPCC_GATE] = ma35d1_clk_gate("sspcc_gate", "pclk3", + clk_base + REG_CLK_APBCLK2, 3); + + /* SPI0~3 */ + hws[SPI0_MUX] = ma35d1_clk_mux("spi0_mux", + clk_base + REG_CLK_CLKSEL4, + 0, 2, spi0_sel_clks, + ARRAY_SIZE(spi0_sel_clks)); + hws[SPI0_GATE] = ma35d1_clk_gate("spi0_gate", "spi0_mux", + clk_base + REG_CLK_APBCLK2, 4); + hws[SPI1_MUX] = ma35d1_clk_mux("spi1_mux", + clk_base + REG_CLK_CLKSEL4, + 2, 2, spi1_sel_clks, + ARRAY_SIZE(spi1_sel_clks)); + hws[SPI1_GATE] = ma35d1_clk_gate("spi1_gate", "spi1_mux", + clk_base + REG_CLK_APBCLK2, 5); + hws[SPI2_MUX] = ma35d1_clk_mux("spi2_mux", + clk_base + REG_CLK_CLKSEL4, + 4, 2, spi2_sel_clks, + ARRAY_SIZE(spi2_sel_clks)); + hws[SPI2_GATE] = ma35d1_clk_gate("spi2_gate", "spi2_mux", + clk_base + REG_CLK_APBCLK2, 6); + hws[SPI3_MUX] = ma35d1_clk_mux("spi3_mux", + clk_base + REG_CLK_CLKSEL4, + 6, 2, spi3_sel_clks, + ARRAY_SIZE(spi3_sel_clks)); + hws[SPI3_GATE] = ma35d1_clk_gate("spi3_gate", "spi3_mux", + clk_base + REG_CLK_APBCLK2, 7); + + /* ECAP0~2 */ + hws[ECAP0_GATE] = ma35d1_clk_gate("ecap0_gate", "pclk1", + clk_base + REG_CLK_APBCLK2, 8); + hws[ECAP1_GATE] = ma35d1_clk_gate("ecap1_gate", "pclk2", + clk_base + REG_CLK_APBCLK2, 9); + hws[ECAP2_GATE] = ma35d1_clk_gate("ecap2_gate", "pclk1", + clk_base + REG_CLK_APBCLK2, 10); + + /* QEI0~2 */ + hws[QEI0_GATE] = ma35d1_clk_gate("qei0_gate", "pclk1", + clk_base + REG_CLK_APBCLK2, 12); + hws[QEI1_GATE] = ma35d1_clk_gate("qei1_gate", "pclk2", + clk_base + REG_CLK_APBCLK2, 13); + hws[QEI2_GATE] = ma35d1_clk_gate("qei2_gate", "pclk1", + clk_base + REG_CLK_APBCLK2, 14); + + /* ADC */ + hws[ADC_DIV] = ma35d1_reg_adc_clkdiv(dev, "adc_div", "pclk0", 0, + clk_base + REG_CLK_CLKDIV4, + 4, 17, 0x1ffff); + hws[ADC_GATE] = ma35d1_clk_gate("adc_gate", "adc_div", + clk_base + REG_CLK_APBCLK2, 24); + + /* EADC */ + hws[EADC_DIV] = ma35d1_clk_divider_table("eadc_div", "pclk2", + clk_base + REG_CLK_CLKDIV4, + 0, 4, eadc_div_table); + hws[EADC_GATE] = ma35d1_clk_gate("eadc_gate", "eadc_div", + clk_base + REG_CLK_APBCLK2, 25); + + ret = of_clk_add_hw_provider(clk_node, of_clk_hw_onecell_get, + ma35d1_hw_data); + if (ret < 0) { + dev_err(dev, "failed to register hws for MA35D1\n"); + iounmap(clk_base); + } + return ret; +} + +static const struct of_device_id ma35d1_clk_of_match[] = { + { .compatible = "nuvoton,ma35d1-clk" }, + { }, +}; +MODULE_DEVICE_TABLE(of, ma35d1_clk_of_match); + +static struct platform_driver ma35d1_clk_driver = { + .probe = ma35d1_clocks_probe, + .driver = { + .name = "ma35d1-clk", + .of_match_table = ma35d1_clk_of_match, + }, +}; + +static int __init ma35d1_clocks_init(void) +{ + return platform_driver_register(&ma35d1_clk_driver); +} + +postcore_initcall(ma35d1_clocks_init); + +MODULE_AUTHOR("Chi-Fang Li"); +MODULE_DESCRIPTION("NUVOTON MA35D1 Clock Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/clk/nuvoton/clk-ma35d1.h b/drivers/clk/nuvoton/clk-ma35d1.h new file mode 100644 index 000000000000..faae5a17e425 --- /dev/null +++ b/drivers/clk/nuvoton/clk-ma35d1.h @@ -0,0 +1,198 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2023 Nuvoton Technology Corp. + * Author: Chi-Fang Li + */ + +#ifndef __DRV_CLK_NUVOTON_MA35D1_H +#define __DRV_CLK_NUVOTON_MA35D1_H + +#include +#include +#include +#include +#include +#include +#include + +enum ma35d1_pll_type { + MA35D1_CAPLL, + MA35D1_DDRPLL, + MA35D1_APLL, + MA35D1_EPLL, + MA35D1_VPLL, +}; + +enum ma35d1_pll_mode { + VSIPLL_INTEGER_MODE, + VSIPLL_FRACTIONAL_MODE, + VSIPLL_SS_MODE, +}; + +/* VSI-PLL CTL0~2 */ +#define VSIPLL_CTL0 0x0 +#define VSIPLL_CTL1 0x4 +#define VSIPLL_CTL2 0x8 + +/* VSI-PLL Specification limits */ +#define VSIPLL_FREF_MAX_FREQ 200000000UL +#define VSIPLL_FREF_MIN_FREQ 1000000UL +#define VSIPLL_FREFDIVM_MAX_FREQ 40000000UL +#define VSIPLL_FREFDIVM_MIN_FREQ0 1000000UL +#define VSIPLL_FREFDIVM_MIN_FREQ1 10000000UL +#define VSIPLL_FCLK_MAX_FREQ 2400000000UL +#define VSIPLL_FCLK_MIN_FREQ 600000000UL +#define VSIPLL_FCLKO_MAX_FREQ 2400000000UL +#define VSIPLL_FCLKO_MIN_FREQ 85700000UL +#define VSIPLL_SPREAD_RANGE 194 +#define VSIPLL_MODULATION_FREQ 50000 + +/* Clock Control Registers Offset */ +#define REG_CLK_PWRCTL (0x00) +#define REG_CLK_SYSCLK0 (0x04) +#define REG_CLK_SYSCLK1 (0x08) +#define REG_CLK_APBCLK0 (0x0C) +#define REG_CLK_APBCLK1 (0x10) +#define REG_CLK_APBCLK2 (0x14) +#define REG_CLK_CLKSEL0 (0x18) +#define REG_CLK_CLKSEL1 (0x1C) +#define REG_CLK_CLKSEL2 (0x20) +#define REG_CLK_CLKSEL3 (0x24) +#define REG_CLK_CLKSEL4 (0x28) +#define REG_CLK_CLKDIV0 (0x2C) +#define REG_CLK_CLKDIV1 (0x30) +#define REG_CLK_CLKDIV2 (0x34) +#define REG_CLK_CLKDIV3 (0x38) +#define REG_CLK_CLKDIV4 (0x3C) +#define REG_CLK_CLKOCTL (0x40) +#define REG_CLK_STATUS (0x50) +#define REG_CLK_PLL0CTL0 (0x60) +#define REG_CLK_PLL2CTL0 (0x80) +#define REG_CLK_PLL2CTL1 (0x84) +#define REG_CLK_PLL2CTL2 (0x88) +#define REG_CLK_PLL3CTL0 (0x90) +#define REG_CLK_PLL3CTL1 (0x94) +#define REG_CLK_PLL3CTL2 (0x98) +#define REG_CLK_PLL4CTL0 (0xA0) +#define REG_CLK_PLL4CTL1 (0xA4) +#define REG_CLK_PLL4CTL2 (0xA8) +#define REG_CLK_PLL5CTL0 (0xB0) +#define REG_CLK_PLL5CTL1 (0xB4) +#define REG_CLK_PLL5CTL2 (0xB8) +#define REG_CLK_CLKDCTL (0xC0) +#define REG_CLK_CLKDSTS (0xC4) +#define REG_CLK_CDUPB (0xC8) +#define REG_CLK_CDLOWB (0xCC) +#define REG_CLK_CKFLTRCTL (0xD0) +#define REG_CLK_TESTCLK (0xF0) +#define REG_CLK_PLLCTL (0x40) + +/* Constant Definitions for Clock Controller */ +#define SMICPLLCTL0_FBDIV_POS (0) +#define SMICPLLCTL0_FBDIV_MSK (0xfful << SMICPLLCTL0_FBDIV_POS) +#define SMICPLLCTL0_INDIV_POS (8) +#define SMICPLLCTL0_INDIV_MSK (0xful << SMICPLLCTL0_INDIV_POS) +#define SMICPLLCTL0_OUTDIV_POS (12) +#define SMICPLLCTL0_OUTDIV_MSK (0x3ul << SMICPLLCTL0_OUTDIV_POS) +#define SMICPLLCTL0_PD_POS (16) +#define SMICPLLCTL0_PD_MSK (0x1ul << SMICPLLCTL0_PD_POS) +#define SMICPLLCTL0_BP_POS (17) +#define SMICPLLCTL0_BP_MSK (0x1ul << SMICPLLCTL0_BP_POS) +#define VSIPLLCTL0_FBDIV_POS (0) +#define VSIPLLCTL0_FBDIV_MSK (0x7fful << VSIPLLCTL0_FBDIV_POS) +#define VSIPLLCTL0_INDIV_POS (12) +#define VSIPLLCTL0_INDIV_MSK (0x3ful << VSIPLLCTL0_INDIV_POS) +#define VSIPLLCTL0_MODE_POS (18) +#define VSIPLLCTL0_MODE_MSK (0x3ul << VSIPLLCTL0_MODE_POS) +#define VSIPLLCTL0_SSRATE_POS (20) +#define VSIPLLCTL0_SSRATE_MSK (0x7fful << VSIPLLCTL0_SSRATE_POS) +#define VSIPLLCTL1_PD_POS (0) +#define VSIPLLCTL1_PD_MSK (0x1ul << VSIPLLCTL1_PD_POS) +#define VSIPLLCTL1_BP_POS (1) +#define VSIPLLCTL1_BP_MSK (0x1ul << VSIPLLCTL1_BP_POS) +#define VSIPLLCTL1_OUTDIV_POS (4) +#define VSIPLLCTL1_OUTDIV_MSK (0x7ul << VSIPLLCTL1_OUTDIV_POS) +#define VSIPLLCTL1_FRAC_POS (8) +#define VSIPLLCTL1_FRAC_MSK (0xfffffful << VSIPLLCTL1_FRAC_POS) +#define VSIPLLCTL2_SLOPE_POS (0) +#define VSIPLLCTL2_SLOPE_MSK (0xfffffful << VSIPLLCTL2_SLOPE_POS) + +struct clk_hw *ma35d1_reg_clk_pll(enum ma35d1_pll_type type, u8 u8mode, + const char *name, const char *parent, + unsigned long targetFreq, + void __iomem *base, + struct regmap *regmap); + +struct clk_hw *ma35d1_reg_adc_clkdiv(struct device *dev, + const char *name, + const char *parent_name, + unsigned long flags, + void __iomem *reg, u8 shift, + u8 width, u32 mask_bit); + +extern spinlock_t ma35d1_lock; + +static inline struct clk_hw *ma35d1_clk_fixed(const char *name, int rate) +{ + return clk_hw_register_fixed_rate(NULL, name, NULL, 0, rate); +} + +static inline struct clk_hw *ma35d1_clk_mux(const char *name, + void __iomem *reg, u8 shift, + u8 width, + const char *const *parents, + int num_parents) +{ + return clk_hw_register_mux(NULL, name, parents, num_parents, + CLK_SET_RATE_NO_REPARENT, reg, shift, + width, 0, &ma35d1_lock); +} + +static inline struct clk_hw *ma35d1_clk_divider(const char *name, + const char *parent, + void __iomem *reg, u8 shift, + u8 width) +{ + return clk_hw_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT, + reg, shift, width, 0, &ma35d1_lock); +} + +static inline struct clk_hw *ma35d1_clk_divider_pow2(const char *name, + const char *parent, + void __iomem *reg, + u8 shift, u8 width) +{ + return clk_hw_register_divider(NULL, name, parent, + CLK_DIVIDER_POWER_OF_TWO, reg, shift, + width, 0, &ma35d1_lock); +} + +static inline struct clk_hw *ma35d1_clk_divider_table(const char *name, + const char *parent, + void __iomem *reg, + u8 shift, u8 width, + const struct clk_div_table *table) +{ + return clk_hw_register_divider_table(NULL, name, parent, 0, + reg, shift, width, 0, table, + &ma35d1_lock); +} + +static inline struct clk_hw *ma35d1_clk_fixed_factor(const char *name, + const char *parent, + unsigned int mult, + unsigned int div) +{ + return clk_hw_register_fixed_factor(NULL, name, parent, + CLK_SET_RATE_PARENT, mult, div); +} + +static inline struct clk_hw *ma35d1_clk_gate(const char *name, + const char *parent, + void __iomem *reg, u8 shift) +{ + return clk_hw_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, + reg, shift, 0, &ma35d1_lock); +} + +#endif /* __DRV_CLK_NUVOTON_MA35D1_H */ From patchwork Wed Mar 15 07:29:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jacky Huang X-Patchwork-Id: 663633 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 50A9AC7618E for ; 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[60.250.192.107]) by smtp.gmail.com with ESMTPSA id kz11-20020a170902f9cb00b001a0667822c8sm2740003plb.94.2023.03.15.00.29.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Mar 2023 00:29:41 -0700 (PDT) From: Jacky Huang To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, gregkh@linuxfoundation.org, jirislaby@kernel.org Cc: devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, schung@nuvoton.com, Jacky Huang Subject: [PATCH 13/15] reset: Add Nuvoton ma35d1 reset driver support Date: Wed, 15 Mar 2023 07:29:00 +0000 Message-Id: <20230315072902.9298-14-ychuang570808@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230315072902.9298-1-ychuang570808@gmail.com> References: <20230315072902.9298-1-ychuang570808@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Jacky Huang This driver supports individual IP reset for ma35d1. The reset control registers is a subset of system control registers. Signed-off-by: Jacky Huang --- drivers/reset/Kconfig | 6 ++ drivers/reset/Makefile | 1 + drivers/reset/reset-ma35d1.c | 152 +++++++++++++++++++++++++++++++++++ 3 files changed, 159 insertions(+) create mode 100644 drivers/reset/reset-ma35d1.c diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 2a52c990d4fe..47671060d259 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -143,6 +143,12 @@ config RESET_NPCM This enables the reset controller driver for Nuvoton NPCM BMC SoCs. +config RESET_NUVOTON_MA35D1 + bool "Nuvton MA35D1 Reset Driver" + default ARCH_NUVOTON + help + This enables the reset controller driver for Nuvoton MA35D1 SoC. + config RESET_OXNAS bool diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 3e7e5fd633a8..fd52dcf66a99 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -20,6 +20,7 @@ obj-$(CONFIG_RESET_MCHP_SPARX5) += reset-microchip-sparx5.o obj-$(CONFIG_RESET_MESON) += reset-meson.o obj-$(CONFIG_RESET_MESON_AUDIO_ARB) += reset-meson-audio-arb.o obj-$(CONFIG_RESET_NPCM) += reset-npcm.o +obj-$(CONFIG_RESET_NUVOTON_MA35D1) += reset-ma35d1.o obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o obj-$(CONFIG_RESET_POLARFIRE_SOC) += reset-mpfs.o diff --git a/drivers/reset/reset-ma35d1.c b/drivers/reset/reset-ma35d1.c new file mode 100644 index 000000000000..bdd39483ca4e --- /dev/null +++ b/drivers/reset/reset-ma35d1.c @@ -0,0 +1,152 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023 Nuvoton Technology Corp. + * Author: Chi-Fang Li + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define RST_PRE_REG 32 + +struct ma35d1_reset_data { + struct reset_controller_dev rcdev; + struct regmap *regmap; +}; + +struct ma35d1_reboot_data { + struct notifier_block restart_handler; + struct regmap *regmap; +}; + +static int ma35d1_restart_handler(struct notifier_block *this, + unsigned long mode, void *cmd) +{ + struct ma35d1_reboot_data *data = + container_of(this, struct ma35d1_reboot_data, + restart_handler); + regmap_write(data->regmap, REG_SYS_IPRST0, 1 << MA35D1_RESET_CHIP); + return -EAGAIN; +} + +static int ma35d1_reset_update(struct reset_controller_dev *rcdev, + unsigned long id, bool assert) +{ + int reg; + int offset = (id / RST_PRE_REG) * 4; + struct ma35d1_reset_data *data = + container_of(rcdev, struct ma35d1_reset_data, rcdev); + + regmap_read(data->regmap, REG_SYS_IPRST0 + offset, ®); + if (assert) + reg |= 1 << (id % RST_PRE_REG); + else + reg &= ~(1 << (id % RST_PRE_REG)); + + regmap_write(data->regmap, REG_SYS_IPRST0 + offset, reg); + return 0; +} + +static int ma35d1_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return ma35d1_reset_update(rcdev, id, true); +} + +static int ma35d1_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return ma35d1_reset_update(rcdev, id, false); +} + +static int ma35d1_reset_status(struct reset_controller_dev *rcdev, + unsigned long id) +{ + int reg; + int offset = id / RST_PRE_REG; + struct ma35d1_reset_data *data = + container_of(rcdev, struct ma35d1_reset_data, rcdev); + + regmap_read(data->regmap, REG_SYS_IPRST0 + offset, ®); + return !!(reg & BIT(id % RST_PRE_REG)); +} + +static const struct reset_control_ops ma35d1_reset_ops = { + .assert = ma35d1_reset_assert, + .deassert = ma35d1_reset_deassert, + .status = ma35d1_reset_status, +}; + +static const struct of_device_id ma35d1_reset_dt_ids[] = { + { .compatible = "nuvoton,ma35d1-reset" }, + { }, +}; + +static int ma35d1_reset_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct ma35d1_reset_data *reset_data; + struct ma35d1_reboot_data *reboot_data; + int err; + + if (!pdev->dev.of_node) { + dev_err(&pdev->dev, "Device tree node not found\n"); + return -EINVAL; + } + + reset_data = devm_kzalloc(dev, sizeof(*reset_data), GFP_KERNEL); + if (!reset_data) + return -ENOMEM; + + reboot_data = devm_kzalloc(dev, sizeof(*reboot_data), GFP_KERNEL); + if (!reboot_data) { + devm_kfree(dev, reset_data); + return -ENOMEM; + } + + reset_data->regmap = syscon_regmap_lookup_by_phandle( + pdev->dev.of_node, "regmap"); + if (IS_ERR(reset_data->regmap)) { + dev_err(&pdev->dev, "Failed to get SYS register base\n"); + err = PTR_ERR(reset_data->regmap); + goto err_out; + } + reset_data->rcdev.owner = THIS_MODULE; + reset_data->rcdev.nr_resets = MA35D1_RESET_COUNT; + reset_data->rcdev.ops = &ma35d1_reset_ops; + reset_data->rcdev.of_node = dev->of_node; + + reboot_data->regmap = reset_data->regmap; + reboot_data->restart_handler.notifier_call = ma35d1_restart_handler; + reboot_data->restart_handler.priority = 192; + + err = register_restart_handler(&reboot_data->restart_handler); + if (err) + dev_warn(&pdev->dev, "failed to register restart handler\n"); + + return devm_reset_controller_register(dev, &reset_data->rcdev); + +err_out: + devm_kfree(dev, reset_data); + devm_kfree(dev, reboot_data); + return err; +} + +static struct platform_driver ma35d1_reset_driver = { + .probe = ma35d1_reset_probe, + .driver = { + .name = "ma35d1-reset", + .of_match_table = ma35d1_reset_dt_ids, + }, +}; + +builtin_platform_driver(ma35d1_reset_driver); From patchwork Wed Mar 15 07:29:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jacky Huang X-Patchwork-Id: 664301 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CCFC1C76195 for ; Wed, 15 Mar 2023 07:32:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231815AbjCOHcm (ORCPT ); Wed, 15 Mar 2023 03:32:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38814 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230018AbjCOHa7 (ORCPT ); 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[60.250.192.107]) by smtp.gmail.com with ESMTPSA id kz11-20020a170902f9cb00b001a0667822c8sm2740003plb.94.2023.03.15.00.29.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Mar 2023 00:29:43 -0700 (PDT) From: Jacky Huang To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, gregkh@linuxfoundation.org, jirislaby@kernel.org Cc: devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, schung@nuvoton.com, Jacky Huang Subject: [PATCH 14/15] tty: serial: Add Nuvoton ma35d1 serial driver support Date: Wed, 15 Mar 2023 07:29:01 +0000 Message-Id: <20230315072902.9298-15-ychuang570808@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230315072902.9298-1-ychuang570808@gmail.com> References: <20230315072902.9298-1-ychuang570808@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Jacky Huang This adds UART and console driver for Nuvoton ma35d1 Soc. MA35D1 SoC provides up to 17 UART controllers, each with one uart port. The ma35d1 uart controller is not compatible with 8250. The uart controller supports: - Full-duplex asynchronous communications - Separates tx and tx 32/32 bytes entry FIFO for data payloads - Hardware auto-flow control - Programmable rx buffer trigger level (1/4/8/14/30 bytes) - Individual programmable baud rate generator for each channel - Supports nCTS, incoming data, rx FIFO reached threshold and RS-485 Address Match (AAD mode) wake-up function - Supports 8-bit rx buffer time-out detection function - Programmable tx data delay time - Supports Auto-Baud Rate measurement and baud rate compensation - Supports break error, frame error, parity error and rx/tx buffer overflow detection function – Programmable number of data bit, 5-, 6-, 7-, 8- bit character – Programmable parity bit, even, odd, no parity or stick parity bit generation and detection – Programmable stop bit, 1, 1.5, or 2 stop bit generation - Supports IrDA SIR function mode - Supports RS-485 function mode – Supports RS-485 9-bit mode – Supports hardware or software enables to program nRTS pin to control RS-485 transmission direction - Supports PDMA transfer function - Support Single-wire function mode. Signed-off-by: Jacky Huang --- drivers/tty/serial/Kconfig | 18 + drivers/tty/serial/Makefile | 1 + drivers/tty/serial/ma35d1_serial.c | 842 +++++++++++++++++++++++++++++ drivers/tty/serial/ma35d1_serial.h | 93 ++++ include/uapi/linux/serial_core.h | 3 + 5 files changed, 957 insertions(+) create mode 100644 drivers/tty/serial/ma35d1_serial.c create mode 100644 drivers/tty/serial/ma35d1_serial.h diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig index 625358f44419..cb47fe804595 100644 --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig @@ -1562,6 +1562,24 @@ config SERIAL_SUNPLUS_CONSOLE you can alter that using a kernel command line option such as "console=ttySUPx". +config SERIAL_NUVOTON_MA35D1 + tristate "Nuvoton MA35D1 family UART support" + depends on ARCH_NUVOTON || COMPILE_TEST + select SERIAL_CORE + help + This driver supports Nuvoton MA35D1 family UART ports. If you would + like to use them, you must answer Y or M to this option. Note that + for use as console, it must be included in kernel and not as a + module + +config SERIAL_NUVOTON_MA35D1_CONSOLE + bool "Console on a Nuvotn MA35D1 family UART port" + depends on SERIAL_NUVOTON_MA35D1=y + select SERIAL_CORE_CONSOLE + help + Select this options if you'd like to use the UART port0 of the + Nuvoton MA35D1 family as a console. + endmenu config SERIAL_MCTRL_GPIO diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile index cd9afd9e3018..71ebeba06ff2 100644 --- a/drivers/tty/serial/Makefile +++ b/drivers/tty/serial/Makefile @@ -93,3 +93,4 @@ obj-$(CONFIG_SERIAL_MCTRL_GPIO) += serial_mctrl_gpio.o obj-$(CONFIG_SERIAL_KGDB_NMI) += kgdb_nmi.o obj-$(CONFIG_KGDB_SERIAL_CONSOLE) += kgdboc.o +obj-$(CONFIG_SERIAL_NUVOTON_MA35D1) += ma35d1_serial.o diff --git a/drivers/tty/serial/ma35d1_serial.c b/drivers/tty/serial/ma35d1_serial.c new file mode 100644 index 000000000000..8940d07c3777 --- /dev/null +++ b/drivers/tty/serial/ma35d1_serial.c @@ -0,0 +1,842 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * MA35D1 serial driver + * Copyright (C) 2023 Nuvoton Technology Corp. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "ma35d1_serial.h" + +#define UART_NR 17 + +static struct uart_driver ma35d1serial_reg; +struct clk *clk; + +struct uart_ma35d1_port { + struct uart_port port; + u16 capabilities; /* port capabilities */ + u8 ier; + u8 lcr; + u8 mcr; + u8 mcr_mask; /* mask of user bits */ + u8 mcr_force; /* mask of forced bits */ + struct serial_rs485 rs485; /* rs485 settings */ + u32 baud_rate; + int rx_count; + u32 console_baud_rate; + u32 console_line; + u32 console_int; +}; + +static struct device_node *ma35d1serial_uart_nodes[UART_NR]; +static struct uart_ma35d1_port ma35d1serial_ports[UART_NR] = { 0 }; +static void __stop_tx(struct uart_ma35d1_port *p); +static void transmit_chars(struct uart_ma35d1_port *up); + +static struct uart_ma35d1_port *to_ma35d1_uart_port(struct uart_port *uart) +{ + return container_of(uart, struct uart_ma35d1_port, port); +} + +static u32 serial_in(struct uart_ma35d1_port *p, int offset) +{ + return __raw_readl(p->port.membase + offset); +} + +static void serial_out(struct uart_ma35d1_port *p, int offset, int value) +{ + __raw_writel(value, p->port.membase + offset); +} + +static void __stop_tx(struct uart_ma35d1_port *p) +{ + u32 ier; + + ier = serial_in(p, UART_REG_IER); + if (ier & THRE_IEN) + serial_out(p, UART_REG_IER, ier & ~THRE_IEN); +} + +static void ma35d1serial_stop_tx(struct uart_port *port) +{ + struct uart_ma35d1_port *up = (struct uart_ma35d1_port *)port; + + __stop_tx(up); +} + +static void ma35d1serial_start_tx(struct uart_port *port) +{ + struct uart_ma35d1_port *up = (struct uart_ma35d1_port *)port; + u32 ier; + struct circ_buf *xmit = &up->port.state->xmit; + + ier = serial_in(up, UART_REG_IER); + serial_out(up, UART_REG_IER, ier & ~THRE_IEN); + if (uart_circ_chars_pending(xmit) < + (16 - ((serial_in(up, UART_REG_FSR) >> 16) & 0x3F))) + transmit_chars(up); + serial_out(up, UART_REG_IER, ier | THRE_IEN); +} + +static void ma35d1serial_stop_rx(struct uart_port *port) +{ + struct uart_ma35d1_port *up = (struct uart_ma35d1_port *)port; + + serial_out(up, UART_REG_IER, serial_in(up, UART_REG_IER) & ~RDA_IEN); +} + +static void +receive_chars(struct uart_ma35d1_port *up) +{ + u8 ch; + u32 fsr; + u32 isr; + u32 dcnt; + char flag; + + isr = serial_in(up, UART_REG_ISR); + fsr = serial_in(up, UART_REG_FSR); + + while (!(fsr & RX_EMPTY)) { + flag = TTY_NORMAL; + up->port.icount.rx++; + + if (unlikely(fsr & (BIF | FEF | PEF | RX_OVER_IF))) { + if (fsr & BIF) { + serial_out(up, UART_REG_FSR, BIF); + up->port.icount.brk++; + if (uart_handle_break(&up->port)) + continue; + } + if (fsr & FEF) { + serial_out(up, UART_REG_FSR, FEF); + up->port.icount.frame++; + } + if (fsr & PEF) { + serial_out(up, UART_REG_FSR, PEF); + up->port.icount.parity++; + } + if (fsr & RX_OVER_IF) { + serial_out(up, UART_REG_FSR, RX_OVER_IF); + up->port.icount.overrun++; + } + if (fsr & BIF) + flag = TTY_BREAK; + if (fsr & PEF) + flag = TTY_PARITY; + if (fsr & FEF) + flag = TTY_FRAME; + } + ch = (u8)serial_in(up, UART_REG_RBR); + if (uart_handle_sysrq_char(&up->port, ch)) + continue; + + uart_insert_char(&up->port, fsr, RX_OVER_IF, ch, flag); + up->rx_count++; + dcnt = (serial_in(up, UART_REG_FSR) >> 8) & 0x3f; + if (up->rx_count > 1023) { + spin_lock(&up->port.lock); + tty_flip_buffer_push(&up->port.state->port); + spin_unlock(&up->port.lock); + up->rx_count = 0; + if ((isr & RXTO_IF) && (dcnt == 0)) + goto tout_end; + } + if (isr & RDA_IF) { + if (dcnt == 1) + return; + } + fsr = serial_in(up, UART_REG_FSR); + } + spin_lock(&up->port.lock); + tty_flip_buffer_push(&up->port.state->port); + spin_unlock(&up->port.lock); +tout_end: + up->rx_count = 0; +} + +static void transmit_chars(struct uart_ma35d1_port *up) +{ + struct circ_buf *xmit = &up->port.state->xmit; + int count = 16 - ((serial_in(up, UART_REG_FSR) >> 16) & 0xF); + + if (serial_in(up, UART_REG_FSR) & TX_FULL) + count = 0; + if (up->port.x_char) { + serial_out(up, UART_REG_THR, up->port.x_char); + up->port.icount.tx++; + up->port.x_char = 0; + return; + } + if (uart_tx_stopped(&up->port)) { + ma35d1serial_stop_tx(&up->port); + return; + } + if (uart_circ_empty(xmit)) { + __stop_tx(up); + return; + } + while (count > 0) { + serial_out(up, UART_REG_THR, xmit->buf[xmit->tail]); + xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); + up->port.icount.tx++; + count--; + if (uart_circ_empty(xmit)) + break; + } + if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) + uart_write_wakeup(&up->port); + if (uart_circ_empty(xmit)) + __stop_tx(up); +} + +static irqreturn_t ma35d1serial_interrupt(int irq, void *dev_id) +{ + struct uart_ma35d1_port *up = (struct uart_ma35d1_port *)dev_id; + u32 isr, fsr; + + isr = serial_in(up, UART_REG_ISR); + fsr = serial_in(up, UART_REG_FSR); + if (isr & (RDA_IF | RXTO_IF)) + receive_chars(up); + if (isr & THRE_INT) + transmit_chars(up); + if (fsr & (BIF | FEF | PEF | RX_OVER_IF | TX_OVER_IF)) + serial_out(up, UART_REG_FSR, + (BIF | FEF | PEF | RX_OVER_IF | TX_OVER_IF)); + + return IRQ_HANDLED; +} + +static u32 ma35d1serial_tx_empty(struct uart_port *port) +{ + struct uart_ma35d1_port *up = (struct uart_ma35d1_port *)port; + u32 fsr; + + fsr = serial_in(up, UART_REG_FSR); + return (fsr & (TE_FLAG | TX_EMPTY)) == (TE_FLAG | TX_EMPTY) ? + TIOCSER_TEMT : 0; +} + +static u32 ma35d1serial_get_mctrl(struct uart_port *port) +{ + struct uart_ma35d1_port *up = (struct uart_ma35d1_port *)port; + u32 status; + u32 ret = 0; + + status = serial_in(up, UART_REG_MSR); + if (!(status & 0x10)) + ret |= TIOCM_CTS; + return ret; +} + +static void ma35d1serial_set_mctrl(struct uart_port *port, u32 mctrl) +{ + struct uart_ma35d1_port *up = (struct uart_ma35d1_port *)port; + u32 mcr = 0; + u32 ier = 0; + + if (mctrl & TIOCM_RTS) { + /* set RTS high level trigger */ + mcr = serial_in(up, UART_REG_MCR); + mcr |= 0x200; + mcr &= ~(0x2); + } + if (up->mcr & UART_MCR_AFE) { + /* set RTS high level trigger */ + mcr = serial_in(up, UART_REG_MCR); + mcr |= 0x200; + mcr &= ~(0x2); + + /* enable CTS/RTS auto-flow control */ + serial_out(up, UART_REG_IER, + (serial_in(up, UART_REG_IER) | (0x3000))); + + /* Set hardware flow control */ + up->port.flags |= UPF_HARD_FLOW; + } else { + /* disable CTS/RTS auto-flow control */ + ier = serial_in(up, UART_REG_IER); + ier &= ~(0x3000); + serial_out(up, UART_REG_IER, ier); + + /* un-set hardware flow control */ + up->port.flags &= ~UPF_HARD_FLOW; + } + + /* set CTS high level trigger */ + serial_out(up, UART_REG_MSR, (serial_in(up, UART_REG_MSR) | (0x100))); + serial_out(up, UART_REG_MCR, mcr); +} + +static void ma35d1serial_break_ctl(struct uart_port *port, int break_state) +{ + struct uart_ma35d1_port *up = (struct uart_ma35d1_port *)port; + unsigned long flags; + u32 lcr; + + spin_lock_irqsave(&up->port.lock, flags); + lcr = serial_in(up, UART_REG_LCR); + if (break_state != 0) + lcr |= BCB; /* set break */ + else + lcr &= ~BCB; /* clr break */ + serial_out(up, UART_REG_LCR, lcr); + spin_unlock_irqrestore(&up->port.lock, flags); +} + +static int ma35d1serial_startup(struct uart_port *port) +{ + struct uart_ma35d1_port *up = (struct uart_ma35d1_port *)port; + struct tty_struct *tty = port->state->port.tty; + int retval; + + /* Reset FIFO */ + serial_out(up, UART_REG_FCR, TFR | RFR /* | RX_DIS */); + + /* Clear pending interrupts */ + serial_out(up, UART_REG_ISR, 0xFFFFFFFF); + + retval = request_irq(port->irq, ma35d1serial_interrupt, 0, + tty ? tty->name : "ma35d1_serial", port); + if (retval) { + dev_err(up->port.dev, "request irq failed.\n"); + return retval; + } + + /* Now, initialize the UART */ + /* FIFO trigger level 4 byte */ + /* RTS trigger level 8 bytes */ + serial_out(up, UART_REG_FCR, + serial_in(up, UART_REG_FCR) | 0x10 | 0x20000); + serial_out(up, UART_REG_LCR, 0x7); /* 8 bit */ + serial_out(up, UART_REG_TOR, 0x40); + serial_out(up, UART_REG_IER, + RTO_IEN | RDA_IEN | TIME_OUT_EN | BUFERR_IEN); + return 0; +} + +static void ma35d1serial_shutdown(struct uart_port *port) +{ + struct uart_ma35d1_port *up = (struct uart_ma35d1_port *)port; + + free_irq(port->irq, port); + + /* Disable interrupts from this port */ + serial_out(up, UART_REG_IER, 0); +} + +static u32 ma35d1serial_get_divisor(struct uart_port *port, u32 baud) +{ + u32 quot; + + quot = (port->uartclk / baud) - 2; + return quot; +} + +static void ma35d1serial_set_termios(struct uart_port *port, + struct ktermios *termios, + const struct ktermios *old) +{ + struct uart_ma35d1_port *up = (struct uart_ma35d1_port *)port; + u32 lcr = 0; + unsigned long flags; + u32 baud, quot; + + switch (termios->c_cflag & CSIZE) { + case CS5: + lcr = 0; + break; + case CS6: + lcr |= 1; + break; + case CS7: + lcr |= 2; + break; + case CS8: + default: + lcr |= 3; + break; + } + + if (termios->c_cflag & CSTOPB) + lcr |= NSB; + if (termios->c_cflag & PARENB) + lcr |= PBE; + if (!(termios->c_cflag & PARODD)) + lcr |= EPE; + if (termios->c_cflag & CMSPAR) + lcr |= SPE; + + baud = uart_get_baud_rate(port, termios, old, port->uartclk / 0xffff, + port->uartclk / 11); + + quot = ma35d1serial_get_divisor(port, baud); + + /* + * Ok, we're now changing the port state. Do it with + * interrupts disabled. + */ + spin_lock_irqsave(&up->port.lock, flags); + + up->port.read_status_mask = RX_OVER_IF; + if (termios->c_iflag & INPCK) + up->port.read_status_mask |= FEF | PEF; + if (termios->c_iflag & (BRKINT | PARMRK)) + up->port.read_status_mask |= BIF; + + /* + * Characteres to ignore + */ + up->port.ignore_status_mask = 0; + if (termios->c_iflag & IGNPAR) + up->port.ignore_status_mask |= FEF | PEF; + if (termios->c_iflag & IGNBRK) { + up->port.ignore_status_mask |= BIF; + /* + * If we're ignoring parity and break indicators, + * ignore overruns too (for real raw support). + */ + if (termios->c_iflag & IGNPAR) + up->port.ignore_status_mask |= RX_OVER_IF; + } + if (termios->c_cflag & CRTSCTS) + up->mcr |= UART_MCR_AFE; + else + up->mcr &= ~UART_MCR_AFE; + + ma35d1serial_set_mctrl(&up->port, up->port.mctrl); + serial_out(up, UART_REG_BAUD, quot | 0x30000000); + serial_out(up, UART_REG_LCR, lcr); + spin_unlock_irqrestore(&up->port.lock, flags); +} + +static void ma35d1serial_release_port(struct uart_port *port) +{ + iounmap(port->membase); + port->membase = NULL; +} + +static int ma35d1serial_request_port(struct uart_port *port) +{ + return 0; +} + +static void ma35d1serial_config_port(struct uart_port *port, int flags) +{ + int ret; + + /* + * Find the region that we can probe for. This in turn + * tells us whether we can probe for the type of port. + */ + ret = ma35d1serial_request_port(port); + if (ret < 0) + return; + port->type = PORT_MA35D1; +} + +static int ma35d1serial_verify_port(struct uart_port *port, + struct serial_struct *ser) +{ + if (ser->type != PORT_UNKNOWN && ser->type != PORT_MA35D1) + return -EINVAL; + return 0; +} + +static const char *ma35d1serial_type(struct uart_port *port) +{ + return (port->type == PORT_MA35D1) ? "MA35D1" : NULL; +} + +/* Enable or disable the rs485 support */ +static int ma35d1serial_config_rs485(struct uart_port *port, + struct ktermios *termios, + struct serial_rs485 *rs485conf) +{ + struct uart_ma35d1_port *p = to_ma35d1_uart_port(port); + + p->rs485 = *rs485conf; + + if (p->rs485.delay_rts_before_send >= 1000) + p->rs485.delay_rts_before_send = 1000; + + serial_out(p, UART_FUN_SEL, + (serial_in(p, UART_FUN_SEL) & ~FUN_SEL_MASK)); + + if (rs485conf->flags & SER_RS485_ENABLED) { + serial_out(p, UART_FUN_SEL, + (serial_in(p, UART_FUN_SEL) | FUN_SEL_RS485)); + + if (rs485conf->flags & SER_RS485_RTS_ON_SEND) + serial_out(p, UART_REG_MCR, + (serial_in(p, UART_REG_MCR) & ~0x200)); + else + serial_out(p, UART_REG_MCR, + (serial_in(p, UART_REG_MCR) | 0x200)); + + /* set auto direction mode */ + serial_out(p, UART_REG_ALT_CSR, + (serial_in(p, UART_REG_ALT_CSR) | (1 << 10))); + } + return 0; +} + +static int ma35d1serial_ioctl(struct uart_port *port, u32 cmd, unsigned long arg) +{ + switch (cmd) { + default: + return -ENOIOCTLCMD; + } + return 0; +} + +static const struct uart_ops ma35d1serial_ops = { + .tx_empty = ma35d1serial_tx_empty, + .set_mctrl = ma35d1serial_set_mctrl, + .get_mctrl = ma35d1serial_get_mctrl, + .stop_tx = ma35d1serial_stop_tx, + .start_tx = ma35d1serial_start_tx, + .stop_rx = ma35d1serial_stop_rx, + .break_ctl = ma35d1serial_break_ctl, + .startup = ma35d1serial_startup, + .shutdown = ma35d1serial_shutdown, + .set_termios = ma35d1serial_set_termios, + .type = ma35d1serial_type, + .release_port = ma35d1serial_release_port, + .request_port = ma35d1serial_request_port, + .config_port = ma35d1serial_config_port, + .verify_port = ma35d1serial_verify_port, + .ioctl = ma35d1serial_ioctl, +}; + +static const struct of_device_id ma35d1_serial_of_match[] = { + { .compatible = "nuvoton,ma35d1-uart" }, + {}, +}; +MODULE_DEVICE_TABLE(of, ma35d1_serial_of_match); + +#ifdef CONFIG_SERIAL_NUVOTON_MA35D1_CONSOLE + +static void ma35d1serial_console_putchar(struct uart_port *port, + unsigned char ch) +{ + struct uart_ma35d1_port *up = (struct uart_ma35d1_port *)port; + + do { + } while ((serial_in(up, UART_REG_FSR) & TX_FULL)); + serial_out(up, UART_REG_THR, ch); +} + +/* + * Print a string to the serial port trying not to disturb + * any possible real use of the port... + * + * The console_lock must be held when we get here. + */ +static void ma35d1serial_console_write(struct console *co, + const char *s, u32 count) +{ + struct uart_ma35d1_port *up = &ma35d1serial_ports[co->index]; + unsigned long flags; + u32 ier; + + local_irq_save(flags); + + /* + * First save the IER then disable the interrupts + */ + ier = serial_in(up, UART_REG_IER); + serial_out(up, UART_REG_IER, 0); + + uart_console_write(&up->port, s, count, ma35d1serial_console_putchar); + + /* + * Finally, wait for transmitter to become empty + * and restore the IER + */ + do { + } while (!(serial_in(up, UART_REG_FSR) & TX_EMPTY)); + serial_out(up, UART_REG_IER, ier); + local_irq_restore(flags); +} + +static int __init ma35d1serial_console_setup(struct console *co, + char *options) +{ + struct device_node *np = ma35d1serial_uart_nodes[co->index]; + struct uart_ma35d1_port *p = &ma35d1serial_ports[co->index]; + u32 val32[4]; + struct uart_port *port; + int baud = 115200; + int bits = 8; + int parity = 'n'; + int flow = 'n'; + + /* + * Check whether an invalid uart number has been specified, and + * if so, search for the first available port that does have + * console support. + */ + if ((co->index < 0) || (co->index >= UART_NR)) { + pr_debug("Console Port%x out of range\n", co->index); + return -EINVAL; + } + + if (of_property_read_u32_array(np, "reg", val32, 4) != 0) + return -EINVAL; + p->port.iobase = val32[1]; + p->port.membase = ioremap(p->port.iobase, 0x10000); + p->port.ops = &ma35d1serial_ops; + p->port.line = 0; + p->port.uartclk = 24000000; + + port = &ma35d1serial_ports[co->index].port; + return uart_set_options(port, co, baud, parity, bits, flow); +} + +static struct console ma35d1serial_console = { + .name = "ttyS", + .write = ma35d1serial_console_write, + .device = uart_console_device, + .setup = ma35d1serial_console_setup, + .flags = CON_PRINTBUFFER | CON_ENABLED, + .index = -1, + .data = &ma35d1serial_reg, +}; + +static void +ma35d1serial_console_init_port(void) +{ + int i = 0; + struct device_node *np; + + for_each_matching_node(np, ma35d1_serial_of_match) { + if (ma35d1serial_uart_nodes[i] == NULL) { + ma35d1serial_uart_nodes[i] = np; + i++; + } + } +} + +static int __init ma35d1serial_console_init(void) +{ + ma35d1serial_console_init_port(); + register_console(&ma35d1serial_console); + return 0; +} +console_initcall(ma35d1serial_console_init); + +#define MA35D1SERIAL_CONSOLE (&ma35d1serial_console) +#else +#define MA35D1SERIAL_CONSOLE NULL +#endif + +static struct uart_driver ma35d1serial_reg = { + .owner = THIS_MODULE, + .driver_name = "serial", + .dev_name = "ttyS", + .major = TTY_MAJOR, + .minor = 64, + .cons = MA35D1SERIAL_CONSOLE, + .nr = UART_NR, +}; + +/** + * Suspend one serial port. + */ +void ma35d1serial_suspend_port(int line) +{ + uart_suspend_port(&ma35d1serial_reg, &ma35d1serial_ports[line].port); +} +EXPORT_SYMBOL(ma35d1serial_suspend_port); + +/** + * Resume one serial port. + */ +void ma35d1serial_resume_port(int line) +{ + struct uart_ma35d1_port *up = &ma35d1serial_ports[line]; + + uart_resume_port(&ma35d1serial_reg, &up->port); +} +EXPORT_SYMBOL(ma35d1serial_resume_port); + +/* + * Register a set of serial devices attached to a platform device. + * The list is terminated with a zero flags entry, which means we expect + * all entries to have at least UPF_BOOT_AUTOCONF set. + */ +static int ma35d1serial_probe(struct platform_device *pdev) +{ + struct resource *res_mem; + struct uart_ma35d1_port *up; + int ret; + struct clk *clk; + int err; + + if (pdev->dev.of_node) { + ret = of_alias_get_id(pdev->dev.of_node, "serial"); + if (ret < 0) { + dev_err(&pdev->dev, + "failed to get alias/pdev id, errno %d\n", + ret); + return ret; + } + } + up = &ma35d1serial_ports[ret]; + up->port.line = ret; + res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res_mem) + return -ENODEV; + + up->port.iobase = res_mem->start; + up->port.membase = ioremap(up->port.iobase, 0x10000); + up->port.ops = &ma35d1serial_ops; + + spin_lock_init(&up->port.lock); + + clk = of_clk_get(pdev->dev.of_node, 0); + if (IS_ERR(clk)) { + err = PTR_ERR(clk); + dev_err(&pdev->dev, "failed to get core clk: %d\n", err); + return -ENOENT; + } + err = clk_prepare_enable(clk); + if (err) + return -ENOENT; + + if (up->port.line != 0) + up->port.uartclk = clk_get_rate(clk); + up->port.irq = platform_get_irq(pdev, 0); + up->port.dev = &pdev->dev; + up->port.flags = UPF_BOOT_AUTOCONF; + up->port.rs485_config = ma35d1serial_config_rs485; + ret = uart_add_one_port(&ma35d1serial_reg, &up->port); + platform_set_drvdata(pdev, up); + return 0; +} + +/* + * Remove serial ports registered against a platform device. + */ +static int ma35d1serial_remove(struct platform_device *dev) +{ + int i; + struct uart_port *port = platform_get_drvdata(dev); + + free_irq(port->irq, port); + for (i = 0; i < UART_NR; i++) { + struct uart_ma35d1_port *up = &ma35d1serial_ports[i]; + + if (up->port.dev == &dev->dev) + uart_remove_one_port(&ma35d1serial_reg, &up->port); + } + return 0; +} + +static int ma35d1serial_suspend(struct platform_device *dev, + pm_message_t state) +{ + int i; + struct uart_ma35d1_port *up; + + if (dev->dev.of_node) + i = of_alias_get_id(dev->dev.of_node, "serial"); + if (i < 0) { + dev_err(&dev->dev, "failed to get alias/pdev id, errno %d\n", + i); + return i; + } + up = &ma35d1serial_ports[i]; + if (i == 0) { + up->console_baud_rate = serial_in(up, UART_REG_BAUD); + up->console_line = serial_in(up, UART_REG_LCR); + up->console_int = serial_in(up, UART_REG_IER); + } + return 0; +} + +static int ma35d1serial_resume(struct platform_device *dev) +{ + int i; + struct uart_ma35d1_port *up; + + if (dev->dev.of_node) + i = of_alias_get_id(dev->dev.of_node, "serial"); + if (i < 0) { + dev_err(&dev->dev, "failed to get alias/pdev id, errno %d\n", + i); + return i; + } + up = &ma35d1serial_ports[i]; + if (i == 0) { + serial_out(up, UART_REG_BAUD, up->console_baud_rate); + serial_out(up, UART_REG_LCR, up->console_line); + serial_out(up, UART_REG_IER, up->console_int); + } + return 0; +} + +static struct platform_driver ma35d1serial_driver = { + .probe = ma35d1serial_probe, + .remove = ma35d1serial_remove, + .suspend = ma35d1serial_suspend, + .resume = ma35d1serial_resume, + .driver = { + .name = "ma35d1-uart", + .owner = THIS_MODULE, + .of_match_table = of_match_ptr(ma35d1_serial_of_match), + }, +}; + +static int __init ma35d1serial_init(void) +{ + int ret; + + ret = uart_register_driver(&ma35d1serial_reg); + if (ret) + return ret; + ret = platform_driver_register(&ma35d1serial_driver); + if (ret) + uart_unregister_driver(&ma35d1serial_reg); + return ret; +} + +static void __exit ma35d1serial_exit(void) +{ + platform_driver_unregister(&ma35d1serial_driver); + uart_unregister_driver(&ma35d1serial_reg); +} + +module_init(ma35d1serial_init); +module_exit(ma35d1serial_exit); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("MA35D1 serial driver"); +MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR); + diff --git a/drivers/tty/serial/ma35d1_serial.h b/drivers/tty/serial/ma35d1_serial.h new file mode 100644 index 000000000000..5fd845c31b29 --- /dev/null +++ b/drivers/tty/serial/ma35d1_serial.h @@ -0,0 +1,93 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * MA35D1 serial driver header file + * Copyright (C) 2023 Nuvoton Technology Corp. + */ +#ifndef __MA35D1_SERIAL_H__ +#define __MA35D1_SERIAL_H__ + +/* UART Receive/Transmit Buffer Register */ +#define UART_REG_RBR 0x00 +#define UART_REG_THR 0x00 + +/* UART Interrupt Enable Register */ +#define UART_REG_IER 0x04 +#define RDA_IEN 0x00000001 /* RBR Available Interrupt Enable */ +#define THRE_IEN 0x00000002 /* THR Empty Interrupt Enable */ +#define RLS_IEN 0x00000004 /* RX Line Status Interrupt Enable */ +#define RTO_IEN 0x00000010 /* RX Time-out Interrupt Enable */ +#define BUFERR_IEN 0x00000020 /* Buffer Error Interrupt Enable */ +#define TIME_OUT_EN 0x00000800 /* RX Buffer Time-out Counter Enable */ + +/* UART FIFO Control Register */ +#define UART_REG_FCR 0x08 +#define RFR 0x00000002 /* RX Field Software Reset */ +#define TFR 0x00000004 /* TX Field Software Reset */ + +/* UART Line Control Register */ +#define UART_REG_LCR 0x0C +#define NSB 0x00000004 /* Number of “STOP Bit” */ +#define PBE 0x00000008 /* Parity Bit Enable */ +#define EPE 0x00000010 /* Even Parity Enable */ +#define SPE 0x00000020 /* Stick Parity Enable */ +#define BCB 0x00000040 /* Break Control */ + +/* UART Modem Control Register */ +#define UART_REG_MCR 0x10 +#define RTS 0x00000020 /* nRTS Signal Control */ +#define RTSACTLV 0x00000200 /* nRTS Pin Active Level */ +#define RTSSTS 0x00002000 /* nRTS Pin Status (Read Only) */ + +/* UART Modem Status Register */ +#define UART_REG_MSR 0x14 +#define CTSDETF 0x00000001 /* Detect nCTS State Change Flag */ +#define CTSSTS 0x00000010 /* nCTS Pin Status (Read Only) */ +#define CTSACTLV 0x00000100 /* nCTS Pin Active Level */ + +/* UART FIFO Status Register */ +#define UART_REG_FSR 0x18 +#define RX_OVER_IF 0x00000001 /* RX Overflow Error Interrupt Flag */ +#define PEF 0x00000010 /* Parity Error Flag*/ +#define FEF 0x00000020 /* Framing Error Flag */ +#define BIF 0x00000040 /* Break Interrupt Flag */ +#define RX_EMPTY 0x00004000 /* Receiver FIFO Empty (Read Only) */ +#define RX_FULL 0x00008000 /* Receiver FIFO Full (Read Only) */ +#define TX_EMPTY 0x00400000 /* Transmitter FIFO Empty (Read Only) */ +#define TX_FULL 0x00800000 /* Transmitter FIFO Full (Read Only) */ +#define TX_OVER_IF 0x01000000 /* TX Overflow Error Interrupt Flag */ +#define TE_FLAG 0x10000000 /* Transmitter Empty Flag (Read Only) */ + +/* UART Interrupt Status Register */ +#define UART_REG_ISR 0x1C +#define RDA_IF 0x00000001 /* RBR Available Interrupt Flag */ +#define THRE_IF 0x00000002 /* THR Empty Interrupt Flag */ +#define RLSIF 0x00000004 /* Receive Line Interrupt Flag */ +#define MODEMIF 0x00000008 /* MODEM Interrupt Flag */ +#define RXTO_IF 0x00000010 /* RX Time-out Interrupt Flag */ +#define BUFEIF 0x00000020 /* Buffer Error Interrupt Flag */ +#define WK_IF 0x00000040 /* UART Wake-up Interrupt Flag */ +#define RDAINT 0x00000100 /* RBR Available Interrupt Indicator */ +#define THRE_INT 0x00000200 /* THR Empty Interrupt Indicator */ + +/* UART Time-out Register */ +#define UART_REG_TOR 0x20 + +/* UART Baud Rate Divider Register */ +#define UART_REG_BAUD 0x24 + +/* UART Alternate Control/Status Register */ +#define UART_REG_ALT_CSR 0x2C + +/* UART Function Select Register */ +#define UART_FUN_SEL 0x30 +#define FUN_SEL_UART 0x00000000 +#define FUN_SEL_RS485 0x00000003 +#define FUN_SEL_MASK 0x00000007 + +/* UART Wake-up Control Register */ +#define UART_REG_WKCTL 0x40 + +/* UART Wake-up Status Register */ +#define UART_REG_WKSTS 0x44 + +#endif /* __MA35D1_SERIAL_H__ */ diff --git a/include/uapi/linux/serial_core.h b/include/uapi/linux/serial_core.h index 281fa286555c..c6d53db17042 100644 --- a/include/uapi/linux/serial_core.h +++ b/include/uapi/linux/serial_core.h @@ -279,4 +279,7 @@ /* Sunplus UART */ #define PORT_SUNPLUS 123 +/* Nuvoton MA35D1 UART */ +#define PORT_MA35D1 124 + #endif /* _UAPILINUX_SERIAL_CORE_H */ From patchwork Wed Mar 15 07:29:02 2023 Content-Type: text/plain; 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[60.250.192.107]) by smtp.gmail.com with ESMTPSA id kz11-20020a170902f9cb00b001a0667822c8sm2740003plb.94.2023.03.15.00.29.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Mar 2023 00:29:46 -0700 (PDT) From: Jacky Huang To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, gregkh@linuxfoundation.org, jirislaby@kernel.org Cc: devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, schung@nuvoton.com, Jacky Huang Subject: [PATCH 15/15] MAINTAINERS: Add entry for NUVOTON MA35 Date: Wed, 15 Mar 2023 07:29:02 +0000 Message-Id: <20230315072902.9298-16-ychuang570808@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230315072902.9298-1-ychuang570808@gmail.com> References: <20230315072902.9298-1-ychuang570808@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Jacky Huang Add entry for Nuvton ma35d1 maintainer and files Signed-off-by: Jacky Huang --- MAINTAINERS | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index ec57c42ed544..b42d5c052863 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2535,6 +2535,18 @@ F: arch/arm/mach-npcm/wpcm450.c F: drivers/*/*/*wpcm* F: drivers/*/*wpcm* +ARM/NUVOTON MA35 ARCHITECTURE +M: Jacky Huang +M: Shan-Chun Hung +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +S: Supported +F: Documentation/devicetree/bindings/*/*nuvoton* +F: arch/arm64/boot/dts/nuvoton/ +F: drivers/*/*/*ma35d1* +F: drivers/*/*ma35d1* +F: include/dt-bindings/*/*ma35d1* +F: include/linux/mfd/ma35d1-sys.h + ARM/NXP S32G ARCHITECTURE M: Chester Lin R: Andreas Färber