From patchwork Wed Mar 15 21:10:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 663565 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BA409C61DA4 for ; Wed, 15 Mar 2023 21:11:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232153AbjCOVLE (ORCPT ); Wed, 15 Mar 2023 17:11:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51232 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232424AbjCOVLD (ORCPT ); Wed, 15 Mar 2023 17:11:03 -0400 Received: from mail-ed1-x52f.google.com (mail-ed1-x52f.google.com [IPv6:2a00:1450:4864:20::52f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9D25A2B2AD for ; Wed, 15 Mar 2023 14:11:01 -0700 (PDT) Received: by mail-ed1-x52f.google.com with SMTP id fd5so46819146edb.7 for ; Wed, 15 Mar 2023 14:11:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1678914660; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WuawNslRJtsC33cN3DASsrMzq8m1GQBJdWGYFmYOzJw=; b=Hm4Jn73YCvnNFAAptrzyqMve7nU/PmLdlqQ0AVEJwPboIH0zEKaOnv8wO7gglsKXcx WX8I0FXCivA8E6ZCRvj+ONY+7poyRpgTsW+HbDAZQ+6NOPq95YIOlhSQrkcTNWzzqR7j VOEeIGZSGElSdKcekINhcDP7tY65lziwvVfrI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678914660; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WuawNslRJtsC33cN3DASsrMzq8m1GQBJdWGYFmYOzJw=; b=ImlKBzA388HfYC0X3RPK/bkVa/yhGzGbqJp6zvM31uTF+Io5Sx10JxFUNj0Mwp3/sn RvKQ4ERf4y0bXT7PrmsCmMlJYcQXKbDsacK+7W/yx9v5GzNEEOa+6qxmPXC+E2JgoEQX kKGYOMmWu++ZM1dySF+AeXCJxsP21MKqVUeT0aSl8U/YDw1G1vZ6Ilmy8t6om0597Vp9 TYSUddMG+1e/5DL6rIkrcAmxt2NNuPNa0tEpeuH6PJdZOlrPNWy3ftvzgb42/oN9rski 0toL5VHA5oIWCU7JHAXJMsHc3JFOP0BO1+yFT+wr5OcQ8trlUjW9K/NEpGDojKDaPzjK duHw== X-Gm-Message-State: AO0yUKXntOrcjN9eh8ZKYfSFpXrTyqkFDT4W20MTVzx6/kj0/dNrMV+C riF92v3LZ3Vv8K0cMbMBsQyiFA== X-Google-Smtp-Source: AK7set/HsncufAKHkG0YqxX7s7PSud+PvzcNbyfIIX8XKDKEbQVS95BgIh70VhfY/KPT2TYhLvUVEw== X-Received: by 2002:a17:907:742:b0:92e:b1dd:cff2 with SMTP id xc2-20020a170907074200b0092eb1ddcff2mr5202283ejb.28.1678914659863; Wed, 15 Mar 2023 14:10:59 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-87-0-96-89.retail.telecomitalia.it. [87.0.96.89]) by smtp.gmail.com with ESMTPSA id o15-20020a170906600f00b0092b5384d6desm2965366ejj.153.2023.03.15.14.10.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Mar 2023 14:10:59 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski , Amarula patchwork , Vincent Mailhol , Alexandre Torgue , michael@amarulasolutions.com, Rob Herring , Marc Kleine-Budde , Dario Binacchi , Christophe Roullier , Krzysztof Kozlowski , Mark Brown , Maxime Coquelin , Rob Herring , Sebastian Reichel , Viresh Kumar , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [RESEND PATCH v7 1/5] dt-bindings: arm: stm32: add compatible for syscon gcan node Date: Wed, 15 Mar 2023 22:10:36 +0100 Message-Id: <20230315211040.2455855-2-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20230315211040.2455855-1-dario.binacchi@amarulasolutions.com> References: <20230315211040.2455855-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Since commit ad440432d1f9 ("dt-bindings: mfd: Ensure 'syscon' has a more specific compatible") It is required to provide at least 2 compatibles string for syscon node. This patch documents the new compatible for stm32f4 SoC to support global/shared CAN registers access for bxCAN controllers. Signed-off-by: Dario Binacchi Acked-by: Rob Herring --- (no changes since v5) Changes in v5: - Add Rob Herring's Acked-by tag. .../devicetree/bindings/arm/stm32/st,stm32-syscon.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml index b2b156cc160a..ad8e51aa01b0 100644 --- a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml @@ -20,6 +20,7 @@ properties: - st,stm32-syscfg - st,stm32-power-config - st,stm32-tamp + - st,stm32f4-gcan - const: syscon - items: - const: st,stm32-tamp @@ -42,6 +43,7 @@ if: contains: enum: - st,stm32mp157-syscfg + - st,stm32f4-gcan then: required: - clocks From patchwork Wed Mar 15 21:10:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 664232 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 69FC4C61DA4 for ; Wed, 15 Mar 2023 21:11:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232891AbjCOVLQ (ORCPT ); Wed, 15 Mar 2023 17:11:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51332 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232822AbjCOVLF (ORCPT ); Wed, 15 Mar 2023 17:11:05 -0400 Received: from mail-ed1-x52c.google.com (mail-ed1-x52c.google.com [IPv6:2a00:1450:4864:20::52c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4D28F301A1 for ; Wed, 15 Mar 2023 14:11:03 -0700 (PDT) Received: by mail-ed1-x52c.google.com with SMTP id o12so80692088edb.9 for ; Wed, 15 Mar 2023 14:11:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1678914661; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Kod5siM2bcM+dDVpz/GqL4BGUBIqfHoecSZkZ5xWujI=; b=OcTQbnJsEFByoCuJ3P6wqVfwXlZxux+7GzvH/tEr5Qa9R77NpeKH3nIk4w0v54c2bZ uOVuPgHUHf9O2YEPkPorbOgGNbxgxegNPuAo1qZ8PBwgEB1vJuueTx7V6wyw44etHP22 jxHV8XLENwlNdab2K4WffBqUxLx3mbmx3o9/o= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678914661; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Kod5siM2bcM+dDVpz/GqL4BGUBIqfHoecSZkZ5xWujI=; b=2EDXQtk7OHoxtWRUN7ztFATrpO8Zj0snGdRfvj13yeJrDjwK7itOUin1gEdPjxYBt9 uP2okbWvd8IvcJD+dU0IeTGU/s90tPvXCeN6TGeTvoCs2OUxsgoNTfn2VWFlxIDOHK6/ W2qoAYO7ZW+xbtTMO0xv5VSqVfi//xGMa/3DVQ27Hlc2WJFw0vjLf6sR1s+Hf1K5Zd/O A1ohF8D2FpIK+CkFUV7AKyhAGarG2UnojdC5Xxq1MIvawUnu8oj69PQlKe/zyK0P2Sv3 JBHGZ72N4Bu+XjTFFoI5j2hXKKGf6igwA+AEtTgLKhMsaQnCmqjxhYiT/n2dH6V/61Ke C4RA== X-Gm-Message-State: AO0yUKV7+i07sKE3ELNxT2N6Thfz84qnOfg6RVpyUGAFSY7OnlHuUMGF tJ03ygWoFvn70jIfVBevdAVt2g== X-Google-Smtp-Source: AK7set/SFU8Ve/CtpZXZI7aa0yyeCXwHleMpdiWNQkU2o/KMWqOAGCXqcjSa+wtXFHJGorKy0q0C7Q== X-Received: by 2002:a17:906:8609:b0:8b2:8876:2a11 with SMTP id o9-20020a170906860900b008b288762a11mr6862160ejx.28.1678914661511; Wed, 15 Mar 2023 14:11:01 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-87-0-96-89.retail.telecomitalia.it. [87.0.96.89]) by smtp.gmail.com with ESMTPSA id o15-20020a170906600f00b0092b5384d6desm2965366ejj.153.2023.03.15.14.11.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Mar 2023 14:11:01 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski , Amarula patchwork , Vincent Mailhol , Alexandre Torgue , michael@amarulasolutions.com, Rob Herring , Marc Kleine-Budde , Dario Binacchi , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Krzysztof Kozlowski , Maxime Coquelin , Paolo Abeni , Rob Herring , Wolfgang Grandegger , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-can@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, netdev@vger.kernel.org Subject: [RESEND PATCH v7 2/5] dt-bindings: net: can: add STM32 bxcan DT bindings Date: Wed, 15 Mar 2023 22:10:37 +0100 Message-Id: <20230315211040.2455855-3-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20230315211040.2455855-1-dario.binacchi@amarulasolutions.com> References: <20230315211040.2455855-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add documentation of device tree bindings for the STM32 basic extended CAN (bxcan) controller. Signed-off-by: Dario Binacchi Reviewed-by: Rob Herring --- (no changes since v5) Changes in v5: - Add Rob Herring's Reviewed-by tag. Changes in v4: - Remove "st,stm32f4-bxcan-core" compatible. In this way the can nodes (compatible "st,stm32f4-bxcan") are no longer children of a parent node with compatible "st,stm32f4-bxcan-core". - Add the "st,gcan" property (global can memory) to can nodes which references a "syscon" node containing the shared clock and memory addresses. Changes in v3: - Remove 'Dario Binacchi ' SOB. - Add description to the parent of the two child nodes. - Move "patterProperties:" after "properties: in top level before "required". - Add "clocks" to the "required:" list of the child nodes. Changes in v2: - Change the file name into 'st,stm32-bxcan-core.yaml'. - Rename compatibles: - st,stm32-bxcan-core -> st,stm32f4-bxcan-core - st,stm32-bxcan -> st,stm32f4-bxcan - Rename master property to st,can-master. - Remove the status property from the example. - Put the node child properties as required. .../bindings/net/can/st,stm32-bxcan.yaml | 83 +++++++++++++++++++ 1 file changed, 83 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/can/st,stm32-bxcan.yaml diff --git a/Documentation/devicetree/bindings/net/can/st,stm32-bxcan.yaml b/Documentation/devicetree/bindings/net/can/st,stm32-bxcan.yaml new file mode 100644 index 000000000000..c9194345d202 --- /dev/null +++ b/Documentation/devicetree/bindings/net/can/st,stm32-bxcan.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/can/st,stm32-bxcan.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics bxCAN controller + +description: STMicroelectronics BxCAN controller for CAN bus + +maintainers: + - Dario Binacchi + +allOf: + - $ref: can-controller.yaml# + +properties: + compatible: + enum: + - st,stm32f4-bxcan + + st,can-master: + description: + Master and slave mode of the bxCAN peripheral is only relevant + if the chip has two CAN peripherals. In that case they share + some of the required logic. + type: boolean + + reg: + maxItems: 1 + + interrupts: + items: + - description: transmit interrupt + - description: FIFO 0 receive interrupt + - description: FIFO 1 receive interrupt + - description: status change error interrupt + + interrupt-names: + items: + - const: tx + - const: rx0 + - const: rx1 + - const: sce + + resets: + maxItems: 1 + + clocks: + maxItems: 1 + + st,gcan: + $ref: "/schemas/types.yaml#/definitions/phandle-array" + description: + The phandle to the gcan node which allows to access the 512-bytes + SRAM memory shared by the two bxCAN cells (CAN1 master and CAN2 + slave) in dual CAN peripheral configuration. + +required: + - compatible + - reg + - interrupts + - resets + - clocks + - st,gcan + +additionalProperties: false + +examples: + - | + #include + #include + + can1: can@40006400 { + compatible = "st,stm32f4-bxcan"; + reg = <0x40006400 0x200>; + interrupts = <19>, <20>, <21>, <22>; + interrupt-names = "tx", "rx0", "rx1", "sce"; + resets = <&rcc STM32F4_APB1_RESET(CAN1)>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>; + st,can-master; + st,gcan = <&gcan>; + }; From patchwork Wed Mar 15 21:10:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 663564 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6AE80C7618A for ; Wed, 15 Mar 2023 21:11:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232986AbjCOVLS (ORCPT ); Wed, 15 Mar 2023 17:11:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51856 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232791AbjCOVLQ (ORCPT ); Wed, 15 Mar 2023 17:11:16 -0400 Received: from mail-ed1-x535.google.com (mail-ed1-x535.google.com [IPv6:2a00:1450:4864:20::535]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A7E9A3402D for ; Wed, 15 Mar 2023 14:11:04 -0700 (PDT) Received: by mail-ed1-x535.google.com with SMTP id eg48so21474939edb.13 for ; Wed, 15 Mar 2023 14:11:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1678914663; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=90w47meUN1AAVQio6KlRg3XgdW53vJW4u/H89twTllI=; b=MsegcRcehzpSfT5JL7t9qBs5Z3LzXzq0kKxWEXzGvwAeNH052yuBvC5uly3NyO9c5K GiYXtHo0nZt4qmquwRQ3nhbLkvf74B4x1pnXLKn7ofcjD0MmmSqti2Fujsb12xizNztg rDW2bikIcpwXUxQGPbagyiFzDWd3jpvTtT1ts= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678914663; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=90w47meUN1AAVQio6KlRg3XgdW53vJW4u/H89twTllI=; b=MyyCqdp9+byomDEm0m6cC7pvCh/jmX9X9ZoyuTyaJayBOZPkeR8UP69ZXPdovUBXIz ylGMLGuX6u0b0E4w3f7a/CjvHJ3HxQshDEHxoRp9U+a4mRKdw3BVUkrSzkGcWTpKDkQe tPYqbIyizPV/J+N5FEdv0LSOOPAZPxOTk8q5TU66UUsEiLQoQV6sC8A3ulz4zmq8ErnB WRT9cmrq007hJNnfr2VYuQyauBl6QOkAW7+a+kQAEidJdrWcTnFyVTr/rhOr5zGc9xID Gl8YvOcc14YcfEgJ8zULPakVPG27D+33m4zPH7B2tCK2ZFIGKj/kuUhSa2qJwrqlOVgD CkBQ== X-Gm-Message-State: AO0yUKVyMUaIgAc/XndpIh3+hu3i4PzMvJy3ep9nuTJ67wYJAvmxWPwt trWcQSl2DoiFIfvaBg33J8u9SA== X-Google-Smtp-Source: AK7set/6gZCgZuysHt4eIbR8wps4ZYsDjM2t04rbduqEPsWRQRNIUfAvDR4zTQM9gyudtep7KGqQ1A== X-Received: by 2002:a17:906:fc0a:b0:91f:c56a:4dd2 with SMTP id ov10-20020a170906fc0a00b0091fc56a4dd2mr7906865ejb.62.1678914662947; Wed, 15 Mar 2023 14:11:02 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-87-0-96-89.retail.telecomitalia.it. [87.0.96.89]) by smtp.gmail.com with ESMTPSA id o15-20020a170906600f00b0092b5384d6desm2965366ejj.153.2023.03.15.14.11.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Mar 2023 14:11:02 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski , Amarula patchwork , Vincent Mailhol , Alexandre Torgue , michael@amarulasolutions.com, Rob Herring , Marc Kleine-Budde , Dario Binacchi , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [RESEND PATCH v7 3/5] ARM: dts: stm32: add CAN support on stm32f429 Date: Wed, 15 Mar 2023 22:10:38 +0100 Message-Id: <20230315211040.2455855-4-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20230315211040.2455855-1-dario.binacchi@amarulasolutions.com> References: <20230315211040.2455855-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add support for bxcan (Basic eXtended CAN controller) to STM32F429. The chip contains two CAN peripherals, CAN1 the master and CAN2 the slave, that share some of the required logic like clock and filters. This means that the slave CAN can't be used without the master CAN. Signed-off-by: Dario Binacchi --- (no changes since v6) Changes in v6: - move can1 node before gcan to keep ordering by address. Changes in v4: - Replace the node can@40006400 (compatible "st,stm32f4-bxcan-core") with the gcan@40006600 node ("sysnode" compatible). The gcan node contains clocks and memory addresses shared by the two can nodes of which it's no longer the parent. - Add to can nodes the "st,gcan" property (global can memory) which references the gcan@40006600 node ("sysnode compatibble). Changes in v3: - Remove 'Dario Binacchi ' SOB. - Add "clocks" to can@0 node. arch/arm/boot/dts/stm32f429.dtsi | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi index c31ceb821231..809b2842ded9 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -362,6 +362,35 @@ i2c3: i2c@40005c00 { status = "disabled"; }; + can1: can@40006400 { + compatible = "st,stm32f4-bxcan"; + reg = <0x40006400 0x200>; + interrupts = <19>, <20>, <21>, <22>; + interrupt-names = "tx", "rx0", "rx1", "sce"; + resets = <&rcc STM32F4_APB1_RESET(CAN1)>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>; + st,can-master; + st,gcan = <&gcan>; + status = "disabled"; + }; + + gcan: gcan@40006600 { + compatible = "st,stm32f4-gcan", "syscon"; + reg = <0x40006600 0x200>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>; + }; + + can2: can@40006800 { + compatible = "st,stm32f4-bxcan"; + reg = <0x40006800 0x200>; + interrupts = <63>, <64>, <65>, <66>; + interrupt-names = "tx", "rx0", "rx1", "sce"; + resets = <&rcc STM32F4_APB1_RESET(CAN2)>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN2)>; + st,gcan = <&gcan>; + status = "disabled"; + }; + dac: dac@40007400 { compatible = "st,stm32f4-dac-core"; reg = <0x40007400 0x400>; From patchwork Wed Mar 15 21:10:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 664231 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 193EAC76196 for ; Wed, 15 Mar 2023 21:11:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230504AbjCOVLU (ORCPT ); Wed, 15 Mar 2023 17:11:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51886 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232921AbjCOVLR (ORCPT ); Wed, 15 Mar 2023 17:11:17 -0400 Received: from mail-ed1-x52f.google.com (mail-ed1-x52f.google.com [IPv6:2a00:1450:4864:20::52f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 991AC35278 for ; Wed, 15 Mar 2023 14:11:07 -0700 (PDT) Received: by mail-ed1-x52f.google.com with SMTP id cn21so50532363edb.0 for ; Wed, 15 Mar 2023 14:11:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1678914666; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QV3iGa8KiUlr1LClhXl1D1BGw0maVF3hcUmABXx2qKM=; b=ohOAJfTr7KdZGoWacsyDi1q2g6iQWcxDkyS31OPkkLXWzu65VmmNVOAW2rrfOba+OK nZKj634RL1nZLy3BUnbpqDGxSIiO1KiFLIoFwqDfXRBVtiG3pbeoJW5R341asYxjydba HbJ/YHH9KBOMgap+SHjm8iAaiFMqZ+Ufz8pPw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678914666; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QV3iGa8KiUlr1LClhXl1D1BGw0maVF3hcUmABXx2qKM=; b=iW/HNychxZluoqODAKHFVLxQJD25FwvYLXm2PvgXEvuhBVuty7FxJJE3ORwO+PTT4Z A0BeQEN/XJb4p9hOIa+1E71wrgMzCuzwnPMUHJKRsHrn3cp9cnfkvAeTtZ00Xti4z+Es oTaP8PybdKiMZN8yUnfp4aZFIZZDuDh0BIb/kjmcj4X3qYnG9YLNUk2H5MvagzP2Mcp4 Cscjl+MBjdw91aqBtbzQ38OtCy25V8l9oYDAi91OBiZOkd6w8SrV1hCC21I8GeOtgzmW MHNyrgQy+wZXrBptSlU+b0vV9NFD41gQfvGZrxUIz6Z/EQh2z9uRdPPQBaKtaDP5KGiN nVxA== X-Gm-Message-State: AO0yUKVwAzxQSHspvDilurzPAbOuDGZ+nesGcdhM19tHeLXO5pDfMA6c ClPZqoL/2ta9PKxc8lze74x9pQ== X-Google-Smtp-Source: AK7set+7qbhTZf0gnRIKNdrZ64AhZR6PoCD9a/ttHDAz8LZ5/kkhFKxcBjVJTkOpXjg9hsXiTU+qog== X-Received: by 2002:a17:907:b021:b0:92f:b8d0:746c with SMTP id fu33-20020a170907b02100b0092fb8d0746cmr1467931ejc.20.1678914666235; Wed, 15 Mar 2023 14:11:06 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-87-0-96-89.retail.telecomitalia.it. [87.0.96.89]) by smtp.gmail.com with ESMTPSA id o15-20020a170906600f00b0092b5384d6desm2965366ejj.153.2023.03.15.14.11.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Mar 2023 14:11:06 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski , Amarula patchwork , Vincent Mailhol , Alexandre Torgue , michael@amarulasolutions.com, Rob Herring , Marc Kleine-Budde , Dario Binacchi , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [RESEND PATCH v7 4/5] ARM: dts: stm32: add pin map for CAN controller on stm32f4 Date: Wed, 15 Mar 2023 22:10:39 +0100 Message-Id: <20230315211040.2455855-5-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20230315211040.2455855-1-dario.binacchi@amarulasolutions.com> References: <20230315211040.2455855-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add pin configurations for using CAN controller on stm32f469-disco board. They are located on the Arduino compatible connector CN5 (CAN1) and on the extension connector CN12 (CAN2). Signed-off-by: Dario Binacchi --- (no changes since v3) Changes in v3: - Remove 'Dario Binacchi ' SOB. - Remove a blank line. Changes in v2: - Remove a blank line. arch/arm/boot/dts/stm32f4-pinctrl.dtsi | 30 ++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi index 4523c63475e4..3bb812d6399e 100644 --- a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi @@ -447,6 +447,36 @@ pins2 { slew-rate = <2>; }; }; + + can1_pins_a: can1-0 { + pins1 { + pinmux = ; /* CAN1_TX */ + }; + pins2 { + pinmux = ; /* CAN1_RX */ + bias-pull-up; + }; + }; + + can2_pins_a: can2-0 { + pins1 { + pinmux = ; /* CAN2_TX */ + }; + pins2 { + pinmux = ; /* CAN2_RX */ + bias-pull-up; + }; + }; + + can2_pins_b: can2-1 { + pins1 { + pinmux = ; /* CAN2_TX */ + }; + pins2 { + pinmux = ; /* CAN2_RX */ + bias-pull-up; + }; + }; }; }; };