From patchwork Tue Mar 14 13:46:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chester Lin X-Patchwork-Id: 663157 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2BD33C6FD1C for ; Tue, 14 Mar 2023 13:50:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231432AbjCNNup (ORCPT ); Tue, 14 Mar 2023 09:50:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34630 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231524AbjCNNuK (ORCPT ); Tue, 14 Mar 2023 09:50:10 -0400 Received: from EUR03-VI1-obe.outbound.protection.outlook.com (mail-vi1eur03on2056.outbound.protection.outlook.com [40.107.103.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 66BD2198; Tue, 14 Mar 2023 06:47:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=WpugFDuq3XQuCeB2Pl0Inu5xHvAHBZ8hfB0Q3RtjqV1hBzflumI1KO6CGIsJAX+KyxYaCg5/IL9mIV/CMQgvjNyt8yPT6w71m/u2ePPkGj4ybYfMD9aqMXF7BUX8rq+hSbFHhW+3QMwnxvOS5Y7m0MtBWP6t3kqzvlEbad8wXpKkjc7I2D8rZ5hJaNfMq60CZs+WrNC/KxxTIA5E/uE1Nj/PfJ2sFdfEnUx2ETLw0ZQoOyTbGUSymsmzbET/eKyafW1xI10zNVZwtTZ8M3d1PKtrpwhCtWGpxZRUQE7YmDu3yKHIXSkIrYo2lGxh1gWUVl/mbIbsQoB5xbmyPLKvLg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=fqm/XdSR62KN5aS9i0BteRN+t8gdhBVkWJEuNnB/Fm0=; b=L20cAyPJnmnFJKJnpqHablj9PN0YknTF9bRG9qKrGBFsDtXXMYFIf2AA94wTYQP+clhTXRm5AwWMvq/gth+erNu7+kj4DkgIYyg0IofKN5JfJJx6lWLhnMZ/wQ5Afs84mr50fxGvjD7n5kNnquU0sK6kPiR2viFRp8Vbu5VclD7b0ji5RP74OIj8CTWqN9EitIh4eP7OOXakwS32jUH+y9Y5vuQJ9070iHMhwrBK85BCh4PgOqd3FrKmSXoMe93x/h+YW+8u8YmWJkRFhS6aG8R0cp+4quQPOQ5WOKkrR7HXHMs+XaOfAG/r0hndYp1hvv2485WUNG83F7QPh+lVYQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=suse.com; dmarc=pass action=none header.from=suse.com; dkim=pass header.d=suse.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=fqm/XdSR62KN5aS9i0BteRN+t8gdhBVkWJEuNnB/Fm0=; b=ArKLAnBZj3a9oiUoo8XsQ67gDvANDzhS6PRdxgd7NjN2oyLft1wj9mR4Dm04iDAso+zv4ESP7ZiRs42ZKYe28Ns274NAh3AMvPG9S1Fw4BCH7hRo3JJ8y2tauSGx4WmBnhR7xytRH9xlg8No898Z1Rcr4XS3ZqrcxP3pCcMTFt1AF+Vvax8WMXjs0YMW5PP7BGAUa4BfcMYzZA1yNlW71AsiA+Ji1UnSuxyXmXe9sPif29plQ9hAmdnCSnlecKoLsoxCPfK7Xprl3xacbdeOb8MYOnQCACtTLyl6ManFpHQG7U4d3nn4aYEmRmf5LpHDMBnIKa1iQabeI6FNBvvh+Q== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=suse.com; Received: from AM0PR0402MB3428.eurprd04.prod.outlook.com (2603:10a6:208:1a::25) by AS5PR04MB9895.eurprd04.prod.outlook.com (2603:10a6:20b:651::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6178.26; Tue, 14 Mar 2023 13:47:00 +0000 Received: from AM0PR0402MB3428.eurprd04.prod.outlook.com ([fe80::2b1f:7e5:94d0:3ba9]) by AM0PR0402MB3428.eurprd04.prod.outlook.com ([fe80::2b1f:7e5:94d0:3ba9%3]) with mapi id 15.20.6178.026; Tue, 14 Mar 2023 13:47:00 +0000 From: Chester Lin To: Linus Walleij , Andy Shevchenko Cc: Chester Lin , NXP S32 Linux Team , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Ghennadi Procopciuc , Andrei Stefanescu , Radu Pirea , =?utf-8?q?Andreas_F=C3=A4rber?= , Matthias Brugger Subject: [PATCH 1/3] pinctrl: s32: refine error/return/config checks and simplify driver codes Date: Tue, 14 Mar 2023 21:46:40 +0800 Message-Id: <20230314134642.21535-2-clin@suse.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20230314134642.21535-1-clin@suse.com> References: <20230314134642.21535-1-clin@suse.com> X-ClientProxiedBy: FR0P281CA0115.DEUP281.PROD.OUTLOOK.COM (2603:10a6:d10:a8::14) To AM0PR0402MB3428.eurprd04.prod.outlook.com (2603:10a6:208:1a::25) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM0PR0402MB3428:EE_|AS5PR04MB9895:EE_ X-MS-Office365-Filtering-Correlation-Id: e1037569-3b47-43c5-6054-08db24929626 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 8zCt/ZhMxq4cJ/NaYGxrUlW/wGFZRbZ++kjPBts8irhVTLSTDlPmrHXqFVYiXrLqm0k3G3FJVOYj1s6QjTGENw9n0La/ipPD2ckJzOAviyIJINEPTV7pzCorR5lUS0SHv5kOBeDpVCKeI9EKPPfGKJiJ64A8KMtQpLomux0GYS33sI5PZnEhvmz0jrbSQHI8ltVwBHzz383RPNwi0pl9B0PbpST6q9gUfGC/CtnTkYI7ktR3Ou5CB1LeiEPD97sTud576Yt8WZnzy0JHX0qPBKaYcMtJsjydPezCzfs7NUA0qE+s1Xw6ZYzM/c4rhuxfzO6iSiHU7dG4djSWo1Jk9Y+3O4+QoYfGTA/LlL0Ls5QoPVs/hQ25H/INPctODweX6q79vFlSVylvletYkNLG3psU6US51nKMTqtERnElpawxNlHqX7zlDpnGM+J+aaWi0x4iJJ1mZmlIYDrXRvWVJI7et+LqvftRXX+9A2GxXApLuTvFLlxiw4IzlwdQ50bdHXdKaZwczikOLAGelSLEmSemmy6tvXIqncnZ2Ia1D8oAyY/OYOGRHnwhEAJiq8eDipo24PG8hcH/K3G3b8Kq73nUuxlCpAlpyw7LlmcARpsSzDN0eNAP4Mb6dZT4KZgcgHJbL+Y7vsM8Sjk3GRNAfw== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM0PR0402MB3428.eurprd04.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230025)(39860400002)(396003)(346002)(366004)(136003)(376002)(451199018)(8936002)(36756003)(54906003)(478600001)(110136005)(316002)(66476007)(8676002)(66946007)(4326008)(66556008)(7416002)(41300700001)(30864003)(2906002)(5660300002)(86362001)(6486002)(6512007)(6506007)(1076003)(26005)(6666004)(107886003)(186003)(2616005)(38100700002)(83380400001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 9vTYAusktNGHsfoSZy3U7fXha/N0GEBFWopT+DT3DyGkb+T0IxUGI1wBTi6i9TRjLrPbReyI4OvbkJ4QUDWwWop2hrmR/0yOvl8JapmJcWjd8Pm5TY0UBg4h8FbgzBoQ3vEJMZVOSa/I/jhgv6ugT/7ELXU566GJd2+eDbTkcUj6AdXavc0uJJDBUb/bxAW3hjBXgQjhPIAqpdzIpwAEoN34tiXRGWHmaAdgBXAedV6aHPCbVYgcIaF16t1GgJm4dN9VuICBp++OWYW7U5RYj0pNoGjnMw0uFoYNlLi9Poqy74DmJtx+1eM4r+2Q6VgTSWGt2McGV9yjQuOWBRlP/j8sQaYggKBfOpQHdonrKPtDAowTC59/1eoiU+DWD0guz7qZhQjOZ9S2umfba9dxaMahvpniYi4YrfdqJZ9tRllVPby7Fx4Iw8J8xqwDM8TrLrK3tyTIs67Sb1muK9Wc57QbPQ9yIteMXVpH94v6chYbSX7kmrzvLD8Bd79yAWkdUj47MNJOSZWvoXfdDj+o/7zmyD2yO7tScQRxT3WfrQjypaPnLWEb1gOophXqjMLuxHmWsKEhv0qRr3tiIwprOWO8t1evsZ7uuf+JTcn2inwKnsJgUJKUjkSNj77NKvfMwLVtDgtLLditg40P2rkteol5YP7DFISzRmm+D0eUifLtCoeLHfSA9CWDPMlc8dZwF8q2THmU9Lxi8ecia0M8EHcZjPPM9f5T3Z7GGwZiuqpFdKQj/g6aLSai538PGBT2a9h6rjxARsrvneV7T9H97b12ssTS4bUqsEn5wck5nzz7HPg7KM3cAxF3EGcXUZqg6HErzfB71+paGQ8t/Wy2c+C/+qDr0oK4knmisaqNIFgHGaiUWhZX8E0OEJFogxcblTIr0T1S2PKPlRNhCTXXtNLOytp+EMkPMCN5S0IiR2u8Q7zBXBXx49imWQOK+kUATSEmMusrEqXfJFJe/IzsU3qHcPsOd3hqB0Fmy5Q3o4uGe1ggQMPy9ZRN72180Unn4uZSQuCP2o/K0Gt7pNVyNC2s0WgspOJdhwaQTDPJC7nl968lqI9a2k1Jwr5f19/GiezOeUx2PV9sBSWEyq4oSP2ohFuvtF5t/C+X+pIe3z5ZIZZ5NTkBYslbIW2K5JTm6bzm5jKfnr0sghFDKs1vpgi8m+T0Hyk/CBbIo1Q/k0XIMj6Vub1t0WK4RcOfIOKLJch3fvOfrnDZ0pEbpdJIkLXvFB+DjoJp5rXsqLfd/G+th2VshiRQeCLDVASytn3xVPSzRxmtwDZ+06MKyWi/uMRjMsCKVXXNfZtbsoX4c4rUCif7RNHqYFfocXIRAaKpqQ/uT9f5qeRZ2B+b6suuoG4UaT8YPzU03w9N/FdnQ/DWRGByczOf3YBikhqE2HpIiMemj6+HXu4GGxC2P/CDr101Qp4f8LiivewY7leMAyRS+hM4O2RU3pKLefl/mGFzP8GaMJdb3Q6vvzDeL8u7JpBPey/nCvzL1i+ohX0mz55XGTgu4vkQDoIMxQtVuRfNx52gl/hsqadQaUX/v5vdollxSmFOk29hr4+0cC0pOl0= X-OriginatorOrg: suse.com X-MS-Exchange-CrossTenant-Network-Message-Id: e1037569-3b47-43c5-6054-08db24929626 X-MS-Exchange-CrossTenant-AuthSource: AM0PR0402MB3428.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Mar 2023 13:47:00.8323 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f7a17af6-1c5c-4a36-aa8b-f5be247aa4ba X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: PZo7yKPgtoa7djKHQE4yZOxnuEaV3Pt9FqhbNcZp7PVUrJ9x9g0jTHDDJuUO3DN8 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS5PR04MB9895 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Improve error/return code handlings and config checks in order to have better reliability and simplify driver codes such as removing/changing improper macros, blanks, print formats and helper calls. Signed-off-by: Chester Lin Reviewed-by: Andy Shevchenko --- drivers/pinctrl/nxp/pinctrl-s32cc.c | 141 +++++++++++++++------------- drivers/pinctrl/nxp/pinctrl-s32g2.c | 8 +- 2 files changed, 78 insertions(+), 71 deletions(-) diff --git a/drivers/pinctrl/nxp/pinctrl-s32cc.c b/drivers/pinctrl/nxp/pinctrl-s32cc.c index e1da332433a3..7a38e3216b0c 100644 --- a/drivers/pinctrl/nxp/pinctrl-s32cc.c +++ b/drivers/pinctrl/nxp/pinctrl-s32cc.c @@ -28,7 +28,8 @@ #include "../pinctrl-utils.h" #include "pinctrl-s32.h" -#define S32_PIN_ID_MASK GENMASK(31, 4) +#define S32_PIN_ID_SHIFT 4 +#define S32_PIN_ID_MASK GENMASK(31, S32_PIN_ID_SHIFT) #define S32_MSCR_SSS_MASK GENMASK(2, 0) #define S32_MSCR_PUS BIT(12) @@ -46,7 +47,7 @@ static struct regmap_config s32_regmap_config = { static u32 get_pin_no(u32 pinmux) { - return (pinmux & S32_PIN_ID_MASK) >> __ffs(S32_PIN_ID_MASK); + return (pinmux & S32_PIN_ID_MASK) >> S32_PIN_ID_SHIFT; } static u32 get_pin_func(u32 pinmux) @@ -108,7 +109,7 @@ s32_get_region(struct pinctrl_dev *pctldev, unsigned int pin) unsigned int mem_regions = ipctl->info->mem_regions; unsigned int i; - for (i = 0; i < mem_regions; ++i) { + for (i = 0; i < mem_regions; i++) { pin_range = ipctl->regions[i].pin_range; if (pin >= pin_range->start && pin <= pin_range->end) return &ipctl->regions[i]; @@ -224,8 +225,7 @@ static int s32_dt_group_node_to_map(struct pinctrl_dev *pctldev, n_pins = of_property_count_elems_of_size(np, "pinmux", sizeof(u32)); if (n_pins < 0) { - dev_warn(dev, "Unable to find 'pinmux' property in node %s.\n", - np->name); + dev_warn(dev, "Can't find 'pinmux' property in node %pOFn\n", np); } else if (!n_pins) { return -EINVAL; } @@ -317,20 +317,25 @@ static int s32_pmx_set(struct pinctrl_dev *pctldev, unsigned int selector, info->functions[selector].name, grp->name); /* Check beforehand so we don't have a partial config. */ - for (i = 0; i < grp->npins; ++i) { + for (i = 0; i < grp->npins; i++) { if (s32_check_pin(pctldev, grp->pin_ids[i]) != 0) { - dev_err(info->dev, "invalid pin: %d in group: %d\n", + dev_err(info->dev, "invalid pin: %u in group: %u\n", grp->pin_ids[i], group); return -EINVAL; } } - for (i = 0, ret = 0; i < grp->npins && !ret; ++i) { + for (i = 0, ret = 0; i < grp->npins && !ret; i++) { ret = s32_regmap_update(pctldev, grp->pin_ids[i], S32_MSCR_SSS_MASK, grp->pin_sss[i]); + if (ret) { + dev_err(info->dev, "Failed to set pin %u\n", + grp->pin_ids[i]); + return ret; + } } - return ret; + return 0; } static int s32_pmx_get_funcs_count(struct pinctrl_dev *pctldev) @@ -375,8 +380,8 @@ static int s32_pmx_gpio_request_enable(struct pinctrl_dev *pctldev, int ret; ret = s32_regmap_read(pctldev, offset, &config); - if (ret != 0) - return -EINVAL; + if (ret) + return ret; /* Save current configuration */ gpio_pin = kmalloc(sizeof(*gpio_pin), GFP_KERNEL); @@ -387,7 +392,7 @@ static int s32_pmx_gpio_request_enable(struct pinctrl_dev *pctldev, gpio_pin->config = config; spin_lock_irqsave(&ipctl->gpio_configs_lock, flags); - list_add(&(gpio_pin->list), &(ipctl->gpio_configs)); + list_add(&gpio_pin->list, &ipctl->gpio_configs); spin_unlock_irqrestore(&ipctl->gpio_configs_lock, flags); /* GPIO pin means SSS = 0 */ @@ -401,15 +406,13 @@ static void s32_pmx_gpio_disable_free(struct pinctrl_dev *pctldev, unsigned int offset) { struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); - struct list_head *pos, *tmp; - struct gpio_pin_config *gpio_pin; + struct gpio_pin_config *gpio_pin, *tmp; unsigned long flags; int ret; spin_lock_irqsave(&ipctl->gpio_configs_lock, flags); - list_for_each_safe(pos, tmp, &ipctl->gpio_configs) { - gpio_pin = list_entry(pos, struct gpio_pin_config, list); + list_for_each_entry_safe(gpio_pin, tmp, &ipctl->gpio_configs, list) { if (gpio_pin->pin_id == offset) { ret = s32_regmap_write(pctldev, gpio_pin->pin_id, @@ -417,7 +420,7 @@ static void s32_pmx_gpio_disable_free(struct pinctrl_dev *pctldev, if (ret != 0) goto unlock; - list_del(pos); + list_del(&gpio_pin->list); kfree(gpio_pin); break; } @@ -461,7 +464,8 @@ static const int support_slew[] = {208, -1, -1, -1, 166, 150, 133, 83}; static int s32_get_slew_regval(int arg) { - int i; + unsigned int i; + /* Translate a real slew rate (MHz) to a register value */ for (i = 0; i < ARRAY_SIZE(support_slew); i++) { if (arg == support_slew[i]) @@ -542,10 +546,11 @@ static int s32_pinconf_mscr_update(struct pinctrl_dev *pctldev, unsigned int config = 0, mask = 0; int i, ret; - if (s32_check_pin(pctldev, pin_id) != 0) - return -EINVAL; + ret = s32_check_pin(pctldev, pin_id); + if (ret) + return ret; - dev_dbg(ipctl->dev, "pinconf set pin %s with %d configs\n", + dev_dbg(ipctl->dev, "pinconf set pin %s with %u configs\n", pin_get_name(pctldev, pin_id), num_configs); for (i = 0; i < num_configs; i++) { @@ -559,11 +564,9 @@ static int s32_pinconf_mscr_update(struct pinctrl_dev *pctldev, if (!config && !mask) return 0; - ret = s32_regmap_update(pctldev, pin_id, mask, config); - - dev_dbg(ipctl->dev, "update: pin %d cfg 0x%x\n", pin_id, config); + dev_dbg(ipctl->dev, "update: pin %u cfg 0x%x\n", pin_id, config); - return ret; + return s32_regmap_update(pctldev, pin_id, mask, config); } static int s32_pinconf_get(struct pinctrl_dev *pctldev, @@ -604,10 +607,13 @@ static void s32_pinconf_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, unsigned int pin_id) { unsigned int config; - int ret = s32_regmap_read(pctldev, pin_id, &config); + int ret; + + ret = s32_regmap_read(pctldev, pin_id, &config); + if (ret) + return; - if (!ret) - seq_printf(s, "0x%x", config); + seq_printf(s, "0x%x", config); } static void s32_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, @@ -710,7 +716,7 @@ int s32_pinctrl_resume(struct device *dev) } #endif -static void s32_pinctrl_parse_groups(struct device_node *np, +static int s32_pinctrl_parse_groups(struct device_node *np, struct s32_pin_group *grp, struct s32_pinctrl_soc_info *info) { @@ -722,21 +728,20 @@ static void s32_pinctrl_parse_groups(struct device_node *np, dev = info->dev; - dev_dbg(dev, "group: %s\n", np->name); + dev_dbg(dev, "group: %pOFn\n", np); /* Initialise group */ grp->name = np->name; npins = of_property_count_elems_of_size(np, "pinmux", sizeof(u32)); - if (npins < 0) { dev_err(dev, "Failed to read 'pinmux' property in node %s.\n", - np->name); - return; + grp->name); + return -EINVAL; } if (!npins) { - dev_err(dev, "The group %s has no pins.\n", np->name); - return; + dev_err(dev, "The group %s has no pins.\n", grp->name); + return -EINVAL; } grp->npins = npins; @@ -745,12 +750,8 @@ static void s32_pinctrl_parse_groups(struct device_node *np, sizeof(unsigned int), GFP_KERNEL); grp->pin_sss = devm_kcalloc(info->dev, grp->npins, sizeof(unsigned int), GFP_KERNEL); - - if (!grp->pin_ids || !grp->pin_sss) { - dev_err(dev, "Failed to allocate memory for the group %s.\n", - np->name); - return; - } + if (!grp->pin_ids || !grp->pin_sss) + return -ENOMEM; i = 0; of_property_for_each_u32(np, "pinmux", prop, p, pinmux) { @@ -761,9 +762,11 @@ static void s32_pinctrl_parse_groups(struct device_node *np, grp->pin_ids[i], grp->pin_sss[i]); i++; } + + return 0; } -static void s32_pinctrl_parse_functions(struct device_node *np, +static int s32_pinctrl_parse_functions(struct device_node *np, struct s32_pinctrl_soc_info *info, u32 index) { @@ -771,8 +774,9 @@ static void s32_pinctrl_parse_functions(struct device_node *np, struct s32_pmx_func *func; struct s32_pin_group *grp; u32 i = 0; + int ret = 0; - dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name); + dev_dbg(info->dev, "parse function(%u): %pOFn\n", index, np); func = &info->functions[index]; @@ -780,18 +784,24 @@ static void s32_pinctrl_parse_functions(struct device_node *np, func->name = np->name; func->num_groups = of_get_child_count(np); if (func->num_groups == 0) { - dev_err(info->dev, "no groups defined in %s\n", np->full_name); - return; + dev_err(info->dev, "no groups defined in %pOF\n", np); + return -EINVAL; } - func->groups = devm_kzalloc(info->dev, - func->num_groups * sizeof(char *), GFP_KERNEL); + func->groups = devm_kcalloc(info->dev, func->num_groups, + sizeof(char *), GFP_KERNEL); + if (!func->groups) + return -ENOMEM; for_each_child_of_node(np, child) { func->groups[i] = child->name; grp = &info->groups[info->grp_index++]; - s32_pinctrl_parse_groups(child, grp, info); + ret = s32_pinctrl_parse_groups(child, grp, info); + if (ret) + return ret; i++; } + + return 0; } static int s32_pinctrl_probe_dt(struct platform_device *pdev, @@ -804,6 +814,7 @@ static int s32_pinctrl_probe_dt(struct platform_device *pdev, struct regmap *map; void __iomem *base; int mem_regions = info->mem_regions; + int ret; u32 nfuncs = 0; u32 i = 0; @@ -815,13 +826,12 @@ static int s32_pinctrl_probe_dt(struct platform_device *pdev, return -EINVAL; } - ipctl->regions = devm_kzalloc(&pdev->dev, - mem_regions * sizeof(*(ipctl->regions)), - GFP_KERNEL); + ipctl->regions = devm_kcalloc(&pdev->dev, mem_regions, + sizeof(*(ipctl->regions)), GFP_KERNEL); if (!ipctl->regions) return -ENOMEM; - for (i = 0; i < mem_regions; ++i) { + for (i = 0; i < mem_regions; i++) { base = devm_platform_get_and_ioremap_resource(pdev, i, &res); if (IS_ERR(base)) return PTR_ERR(base); @@ -851,24 +861,26 @@ static int s32_pinctrl_probe_dt(struct platform_device *pdev, } info->nfunctions = nfuncs; - info->functions = devm_kzalloc(&pdev->dev, - nfuncs * sizeof(struct s32_pmx_func), - GFP_KERNEL); + info->functions = devm_kcalloc(&pdev->dev, nfuncs, + sizeof(struct s32_pmx_func), GFP_KERNEL); if (!info->functions) return -ENOMEM; info->ngroups = 0; for_each_child_of_node(np, child) info->ngroups += of_get_child_count(child); - info->groups = devm_kzalloc(&pdev->dev, - info->ngroups * sizeof(struct s32_pin_group), - GFP_KERNEL); + + info->groups = devm_kcalloc(&pdev->dev, info->ngroups, + sizeof(struct s32_pin_group), GFP_KERNEL); if (!info->groups) return -ENOMEM; i = 0; - for_each_child_of_node(np, child) - s32_pinctrl_parse_functions(child, info, i++); + for_each_child_of_node(np, child) { + ret = s32_pinctrl_parse_functions(child, info, i++); + if (ret) + return ret; + } return 0; } @@ -923,12 +935,9 @@ int s32_pinctrl_probe(struct platform_device *pdev, ipctl->pctl = devm_pinctrl_register(&pdev->dev, s32_pinctrl_desc, ipctl); - - if (IS_ERR(ipctl->pctl)) { - dev_err(&pdev->dev, "could not register s32 pinctrl driver\n"); - return PTR_ERR(ipctl->pctl); - } - + if (IS_ERR(ipctl->pctl)) + return dev_err_probe(&pdev->dev, PTR_ERR(ipctl->pctl), + "could not register s32 pinctrl driver\n"); #ifdef CONFIG_PM_SLEEP saved_context = &ipctl->saved_context; saved_context->pads = diff --git a/drivers/pinctrl/nxp/pinctrl-s32g2.c b/drivers/pinctrl/nxp/pinctrl-s32g2.c index 5028f4adc389..0b0b06f12b8a 100644 --- a/drivers/pinctrl/nxp/pinctrl-s32g2.c +++ b/drivers/pinctrl/nxp/pinctrl-s32g2.c @@ -746,8 +746,8 @@ static int s32g_pinctrl_probe(struct platform_device *pdev) if (!of_id) return -ENODEV; - return s32_pinctrl_probe - (pdev, (struct s32_pinctrl_soc_info *) of_id->data); + return s32_pinctrl_probe(pdev, + (struct s32_pinctrl_soc_info *) of_id->data); } static const struct dev_pm_ops s32g_pinctrl_pm_ops = { @@ -757,14 +757,12 @@ static const struct dev_pm_ops s32g_pinctrl_pm_ops = { static struct platform_driver s32g_pinctrl_driver = { .driver = { .name = "s32g-siul2-pinctrl", - .owner = THIS_MODULE, .of_match_table = s32_pinctrl_of_match, - .pm = &s32g_pinctrl_pm_ops, + .pm = pm_sleep_ptr(&s32g_pinctrl_pm_ops), .suppress_bind_attrs = true, }, .probe = s32g_pinctrl_probe, }; - builtin_platform_driver(s32g_pinctrl_driver); MODULE_AUTHOR("Matthew Nunez "); From patchwork Tue Mar 14 13:46:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chester Lin X-Patchwork-Id: 665117 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9BD98C74A5B for ; Tue, 14 Mar 2023 13:50:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231764AbjCNNuv (ORCPT ); Tue, 14 Mar 2023 09:50:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44760 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231897AbjCNNuP (ORCPT ); Tue, 14 Mar 2023 09:50:15 -0400 Received: from EUR03-VI1-obe.outbound.protection.outlook.com (mail-vi1eur03on2056.outbound.protection.outlook.com [40.107.103.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 028BB618A4; Tue, 14 Mar 2023 06:47:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=j/mRhNIkkji5QUcgOnhdcRr9SSFtl7BHiMGULB9mIpJ0HAd6xF/n9CyVXqwijR9bJyBvGG7y9dmmr0xxcH1FfWIpwzdCBr4ve0JXPKjfHzWzqBlWZ4e2BV6D3W8Wq8R6//vsNuDL7T91oQ45OgEYkpx3NbZwm6EabeJeV8EB69uKyTSFfgDUAZ+zjf8YFDe/g/MvdatAA7sUJxpxTdsVc9vDU1Zc+3kleTotFx49TTQzrNM2BIYJNu2cHdNJuw+O4XQFdhudZ5pcalskRDQo1pUDL+XFcojvPTGmZOiintedGXK1bLXtlVXxcXHi0Z6dVmE40UUfX2NmLxari/xh5Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=xfjqW5GlwrTKSJhwwHNfS58Vv86TZipLBF+s2WS+ke0=; b=R62NMDaE0bYWAfGd+PrJqQtl+QXnKdScVGYZFfVseVS05crbY3dwTd9UwJrgB7O9FtLzyQkz+cfifkMYCIaAju84Fn3KsAvl+yk9U5Cr62enuud7WLNgQ3xdYt4s7fLsNiGe6A8dydWbQyhnPAgBiga+Yog75S1W9qhbe/xufSbNKEapzHaQzziiiqSV0x5+FEV4+wnEWcuFy0J//QRI6Eag4i4PWH7vUT8OSPJgJUwBkoM96o0dbdKgukEoYVuRP3Fv9va5Txm4MMWQdJx/ck2D4X8L0YpxWTwyJ3kMCS43t9HBBZ9tBZNKd0B5kEcLzdSXibX3pMFA+8hYquqnvw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=suse.com; dmarc=pass action=none header.from=suse.com; dkim=pass header.d=suse.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=xfjqW5GlwrTKSJhwwHNfS58Vv86TZipLBF+s2WS+ke0=; b=GiIiiMmpITB/qHF/y7A2w+hy0ug32WXMU8uw8MB38U0YIl8uj+S94i6CjblexGtsfVQ/aSMc0ljscUDBM3ohVT++CzKLQDugyNmNPaep0aNnLKY534nVOJOrG105B7liq4sEVeHwgB+8HWoRNEE1WrdRgOX/4cWVWjNM9J27CrCJ5RVaRGyv8ppQUCDaC8n+lnDELcDfMHYd3h+rkD/DsHMAWOdXtClHG/ETJfStBz6F67XJs9IXtIrLS7rQOkxhOFQDWi+SEjsbcyh5Fjs8cTROmIEn9iRJsVrKB5t/V81IHP/LXdG+o2dM6hc0jXaJSrR9vGQAlZN/lLs9EpxJwQ== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=suse.com; Received: from AM0PR0402MB3428.eurprd04.prod.outlook.com (2603:10a6:208:1a::25) by AS5PR04MB9895.eurprd04.prod.outlook.com (2603:10a6:20b:651::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6178.26; Tue, 14 Mar 2023 13:47:04 +0000 Received: from AM0PR0402MB3428.eurprd04.prod.outlook.com ([fe80::2b1f:7e5:94d0:3ba9]) by AM0PR0402MB3428.eurprd04.prod.outlook.com ([fe80::2b1f:7e5:94d0:3ba9%3]) with mapi id 15.20.6178.026; Tue, 14 Mar 2023 13:47:04 +0000 From: Chester Lin To: Linus Walleij , Andy Shevchenko Cc: Chester Lin , NXP S32 Linux Team , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Ghennadi Procopciuc , Andrei Stefanescu , Radu Pirea , =?utf-8?q?Andreas_F=C3=A4rber?= , Matthias Brugger Subject: [PATCH 2/3] pinctrl: s32cc: refactor pin config parsing Date: Tue, 14 Mar 2023 21:46:41 +0800 Message-Id: <20230314134642.21535-3-clin@suse.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20230314134642.21535-1-clin@suse.com> References: <20230314134642.21535-1-clin@suse.com> X-ClientProxiedBy: FR0P281CA0120.DEUP281.PROD.OUTLOOK.COM (2603:10a6:d10:a8::10) To AM0PR0402MB3428.eurprd04.prod.outlook.com (2603:10a6:208:1a::25) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM0PR0402MB3428:EE_|AS5PR04MB9895:EE_ X-MS-Office365-Filtering-Correlation-Id: 8fa5ca3a-a43a-4796-c3da-08db2492987c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: jg6pGDevBvNR/VgJz7nwflECvS2rYsqx9NKZmHudggkuvUt9Xv7gHbhcvAJMfvwHkN+74FbLprctU2DKuPna/d7Xxj6YcFsrSR0apAmCGrv1eGYp+sBeGh7o39E7ip3Do/cQWI1viCsaccxNBNnKcniJqRfqM9cFre1+8VRTbaOJu2zYQir3nmECdwN3aI+23aQ+DQ6/prbHNzx77qcEZs4H/EX4miczWolkv2y+ExS0S3egFkGRtDiYnC+UsiTVZVJ/Ra7zUcp5GZAWyMKgPMm4ZcfuJDzaS2EztD0l7lRirXt01oAanIsDm5PUtDeWSsV8WKKbPVwPPlxaaTcLYbO0j0/8t0D6mihZkCfc8Shv28OwcE1l+/QjCwVV9xPn3sheAJKo6p8o+BtLlW0ss7p/b6wRVfIVvZthy8iw17tpS7vxRDRvSbzXHEEUPiCBcBiBlPZG7HJpAmJ0U4Ejzz4RqQ6xZUPubCSPUqzNGVQViV/WqELPDO+U7pe5BaEt3wFrLh0M9Rv8jrdLyvDCgsd5YzgFutm+Gnl2xdRcnpWeCmqcnNZ79BcL91z7MT/Au+pHqcBdovYEI01pUNGxCnZmm2T/icUH54bLsn232Ie+dQ+6V1Wk/Gi4/Yy17c0xK9KyHukZ6yZHx2qHXLjRTA== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM0PR0402MB3428.eurprd04.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230025)(39860400002)(396003)(346002)(366004)(136003)(376002)(451199018)(8936002)(36756003)(54906003)(478600001)(110136005)(316002)(66476007)(8676002)(66946007)(4326008)(66556008)(7416002)(41300700001)(2906002)(5660300002)(86362001)(6486002)(6512007)(6506007)(1076003)(26005)(6666004)(107886003)(186003)(2616005)(38100700002)(83380400001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: o4rnbE4ZN7B4KrT5UDRrECFxxXErchxqA+yWUIXJfHoiZxLUtpQAz4csbJAN7IrSGKOIMU1cYsMko77hZ9FTk/5ndtE1gdPxigo5J+pp80CkcId08jTRW9dtc1UQ2J0PKikuNc5sK+w0HbUP8r9syrPBx5/poVyxYFUk/eqBaRlvlPoWfohkXicfjeY+hRJpibqdZpmIFStluB29QpqyqQU5MutoQjiHP69G2exz5nZhZugh5ACxNKm4r2T8qSOQUifKTVJRmo5UzaHH+zVUkgwiVOUgHOKItWtbbMMu2F+c+DtKJu/F+7i0m2EOEFqaXEN2rvB5EbA5h00yEznOgS5vnV1+eW+RKC/cPuULCMmtjL11bJejd/TDTOxnPMhFvX7SDek1El/j1pV5YXGEQjFRuGvqX8tthD6UiTDiYAdi2k4gvO+NyA+idTkQBBuUs3t/baVpq9rY98E0XPjPk+XUCCAmuzSi8sO/I1Svu+h5HP6CLzQcWbVYOe0Fi+36HMiYZpz9RCyUxl3cjglHmnPhAMLPj0UB752iSblg9WyHRHxrws/pxaEt0Ly0EmF2xyZiSOSYMNlLHL7Mxr/Q9MMWxLPcoqaa0HTD0NzBkvPJedfLc/yKffv7AOVB6G2iZ5CaxpP+9+mq2SyNjoi+aJx8ObmKXFdgxw67fahuBJ69ukgNXpfv9wcOqQkOeIq1LDcj6Fo1L7eeN3k0WepeBtcvdeLOU2XTmUYlO+BKsMFV9o4Y4QTL3OUjaejWSOz81t/jT6m/1FyNfVoDipNwjQS2yOp3ZcI3IvVNE9PY6WcD+pj9bwx/A8b24Mh+0lP7sZWahrhqMIwOR8JMmyL3GSG47nV0Y/+5Kzw2lgmZ09/8XlC/v/e411iktKsMvMd92u9Rb/oiZtiGYdwxP3y0jbYxTpx4JOyJ7C1XWbHDOmRq4LWOxKcQY3VHFCoeh88KJhl1d2tL1yXrc1kZH6/f7s4PlV6bDDCCUeEkWQJAicwIzY90CHcktoY1cd7tuOTXZD7njv+dCSSGkHRNdnCFzU8yuVljTJ7S3gZmMQD9znowaWdR5gzlyoOQBLwzXuwzarso0Xlqdjibqtz1AyPLupy9lV7SdjWqYRZM0XKTAvsR7g/DO9OZG8XvJ0SqFyN8AvbroVijyo8M1ClP3mbecc+mg5Z6ZLXuUm2A5QP5cTxCuRHCas2rIqz0vMZGtuUT6tojp08o3XyJ2lO/6PgijXx9XKQF0FYd5kgN9rlRINZEv2v4vMQqsNFRxYU8s+roFbU0l/bX8QmyiThg/dPvfZTwyou0foy3ZX/tmyOGbyBUuDsMj97x0Rjzi1hAdVM09z3nvkdVZt1I5pNJEVXapfwNPVOtmZLNS5W7DjKdUW7uw4eYy1V7ph5abA0WNT3GvrflnY8brYvOB/cYN5LynPV8kyfBAs37opdnd9d0lHpZr0FywDprvw9a56a/4Dlrs+re6zC5f5SPawl4QQ7E8g5aeP9Ep5jJejJu8G8VrBl3dbZ/a5HcJJMQROGuA2GrZ0VFt8Q0fGDtpTMYhnOWHd4CNyuZ+YH1bcCbyWcYG6Y= X-OriginatorOrg: suse.com X-MS-Exchange-CrossTenant-Network-Message-Id: 8fa5ca3a-a43a-4796-c3da-08db2492987c X-MS-Exchange-CrossTenant-AuthSource: AM0PR0402MB3428.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Mar 2023 13:47:04.8164 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f7a17af6-1c5c-4a36-aa8b-f5be247aa4ba X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: lQzKEncIBrUvtXc8S5hloaL3Ffxv3M42cYTsFa7l84FuK92FUcfV1VBLJ9OnVgy6 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS5PR04MB9895 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Move common codes into smaller inline functions and remove some argument handlings that are not actually used by either S32 MSCR register or generic config params. Signed-off-by: Chester Lin --- drivers/pinctrl/nxp/pinctrl-s32cc.c | 82 ++++++++++++++++++----------- 1 file changed, 50 insertions(+), 32 deletions(-) diff --git a/drivers/pinctrl/nxp/pinctrl-s32cc.c b/drivers/pinctrl/nxp/pinctrl-s32cc.c index 7a38e3216b0c..9508fc1e9a90 100644 --- a/drivers/pinctrl/nxp/pinctrl-s32cc.c +++ b/drivers/pinctrl/nxp/pinctrl-s32cc.c @@ -39,6 +39,9 @@ #define S32_MSCR_ODE BIT(20) #define S32_MSCR_OBE BIT(21) +#define S32_CFG_SET true +#define S32_CFG_CLR false + static struct regmap_config s32_regmap_config = { .reg_bits = 32, .val_bits = 32, @@ -475,32 +478,57 @@ static int s32_get_slew_regval(int arg) return -EINVAL; } -static int s32_get_pin_conf(enum pin_config_param param, u32 arg, - unsigned int *mask, unsigned int *config) +static inline void s32_pin_config(unsigned int *mask, unsigned int *config, + unsigned int bits, bool set) +{ + if (set) + *config |= bits; + else + *config &= ~bits; + *mask |= bits; +} + +static inline void s32_pull_enable(enum pin_config_param param, + unsigned int *mask, unsigned int *config) +{ + + if (param == PIN_CONFIG_BIAS_PULL_UP) { + s32_pin_config(mask, config, S32_MSCR_PUS | S32_MSCR_PUE, + S32_CFG_SET); + } else if (param == PIN_CONFIG_BIAS_PULL_DOWN) { + *config &= ~S32_MSCR_PUS; + *config |= S32_MSCR_PUE; + *mask |= S32_MSCR_PUS | S32_MSCR_PUE; + } +} + +static inline void s32_pull_disable(unsigned int *mask, unsigned int *config) +{ + s32_pin_config(mask, config, S32_MSCR_PUS | S32_MSCR_PUE, S32_CFG_CLR); +} + +static int s32_parse_pincfg(unsigned long pincfg, unsigned int *mask, + unsigned int *config) { + enum pin_config_param param; + u32 arg; int ret; + param = pinconf_to_config_param(pincfg); + arg = pinconf_to_config_argument(pincfg); + switch (param) { /* All pins are persistent over suspend */ case PIN_CONFIG_PERSIST_STATE: return 0; case PIN_CONFIG_DRIVE_OPEN_DRAIN: - *config |= S32_MSCR_ODE; - *mask |= S32_MSCR_ODE; + s32_pin_config(mask, config, S32_MSCR_ODE, S32_CFG_SET); break; case PIN_CONFIG_OUTPUT_ENABLE: - if (arg) - *config |= S32_MSCR_OBE; - else - *config &= ~S32_MSCR_OBE; - *mask |= S32_MSCR_OBE; + s32_pin_config(mask, config, S32_MSCR_OBE, S32_CFG_SET); break; case PIN_CONFIG_INPUT_ENABLE: - if (arg) - *config |= S32_MSCR_IBE; - else - *config &= ~S32_MSCR_IBE; - *mask |= S32_MSCR_IBE; + s32_pin_config(mask, config, S32_MSCR_IBE, S32_CFG_SET); break; case PIN_CONFIG_SLEW_RATE: ret = s32_get_slew_regval(arg); @@ -510,25 +538,17 @@ static int s32_get_pin_conf(enum pin_config_param param, u32 arg, *mask |= S32_MSCR_SRE(~0); break; case PIN_CONFIG_BIAS_PULL_UP: - if (arg) - *config |= S32_MSCR_PUS; - else - *config &= ~S32_MSCR_PUS; - fallthrough; case PIN_CONFIG_BIAS_PULL_DOWN: - if (arg) - *config |= S32_MSCR_PUE; - else - *config &= ~S32_MSCR_PUE; - *mask |= S32_MSCR_PUE | S32_MSCR_PUS; + s32_pull_enable(param, mask, config); break; case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: - *config &= ~(S32_MSCR_ODE | S32_MSCR_OBE | S32_MSCR_IBE); - *mask |= S32_MSCR_ODE | S32_MSCR_OBE | S32_MSCR_IBE; - fallthrough; + s32_pin_config(mask, config, + S32_MSCR_ODE | S32_MSCR_OBE | S32_MSCR_IBE, + S32_CFG_CLR); + s32_pull_disable(mask, config); + break; case PIN_CONFIG_BIAS_DISABLE: - *config &= ~(S32_MSCR_PUS | S32_MSCR_PUE); - *mask |= S32_MSCR_PUS | S32_MSCR_PUE; + s32_pull_disable(mask, config); break; default: return -EOPNOTSUPP; @@ -554,9 +574,7 @@ static int s32_pinconf_mscr_update(struct pinctrl_dev *pctldev, pin_get_name(pctldev, pin_id), num_configs); for (i = 0; i < num_configs; i++) { - ret = s32_get_pin_conf(pinconf_to_config_param(configs[i]), - pinconf_to_config_argument(configs[i]), - &mask, &config); + ret = s32_parse_pincfg(configs[i], &mask, &config); if (ret) return ret; } From patchwork Tue Mar 14 13:46:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chester Lin X-Patchwork-Id: 663156 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DBA0FC74A5B for ; Tue, 14 Mar 2023 13:50:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232413AbjCNNu4 (ORCPT ); Tue, 14 Mar 2023 09:50:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35342 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232296AbjCNNuh (ORCPT ); Tue, 14 Mar 2023 09:50:37 -0400 Received: from EUR03-VI1-obe.outbound.protection.outlook.com (mail-vi1eur03on2056.outbound.protection.outlook.com [40.107.103.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DF860A76A4; Tue, 14 Mar 2023 06:47:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=IV3p5P/OO7lG/AntuNPiSbORA5D31GM+QvJguwvL4Xkta4EYnRu47XaLOPGZ29RBdsiZQcKbJDDtranMBITX4YJo9YpSx4C4Of9EDFD2IBO8/Rf9WaALF6C+BMXiOnIhUYVSYnuDhbh5pk8DLSxZ452WsORLjRwtgaHELfmDJbMGrv2Lbp/g4WVY3aJ3Dtv0o8jKRtBzNYf21uN1ZTtMXnwEDhS4h5GFNMSciQHtYqHQnbDdMHDksbwsKj32VpoY1OBK50kY/hiVpsRWhvXo3EZidIrgn4kbgVND3hnMCNojewmUBeWRc4AtTaEf+PH/d+jcEnQpO1oRFDduK6OqrQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=QSYhHwEHCj4GgUa37gwyrn0krmirMvAhFzjeijjhJcM=; b=OULt/lWi53OZTbKE3m+PlEQplfBiLRfLjjG92KLwnjfJy1mVme3TKv93FYT4Mt1E/1DLzzX6TU72eIjeD++H2qvY5fYsQRJEbiqXCltqceoaAAowuOPQpcnt9NvRY1Iw7CWoPZzDZvpMATSo2cgmO0vVuheG2fHW6I2j3P+xgkXujJ8exJcZjA/xhfB8mdwKhPfWxFw4VwR4tz0PoNGNqNtnOLqHy2QnhtNArqmkZqLYz6Pi8d8+fiv1HQt5ntW+APnb8ZvO1VYZ4O1b3ZWYHdDBsZ08Glvk8LFVUjKJ8EJpu/VntOh0w1dA6LtI9BokHpWZp0yC3/Huae7QBw6oLw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=suse.com; dmarc=pass action=none header.from=suse.com; dkim=pass header.d=suse.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=QSYhHwEHCj4GgUa37gwyrn0krmirMvAhFzjeijjhJcM=; b=tMeR7+T6dIw1ZI+ZgXHRWnf5T67StBNG0yWhkAlKYbf520CIYx/tnUb4apn1zvqBvDxznZjW0UXwJ8TZ3xXeubhS2JwjUKhfugKwBUeQrw7AGwWxBM4Q4+fzJ3UBr3caL/7daO+8xOuCJ7chIuIRTIeR42SK+1e9lfZSn8W2ifo/U/U/ASQDDhTmmOzywP6p3bWeMaNeGwEleoZa2D9iSK66lIV0rFlmTvrygWDzFU3KQ0O+DyX1QcLlxDG8Rrq5yFx/YMsp/FQNLGZ+Iwtc+QLxctBw3iRsd2vbGD4LY9kh3jXwdddHxgW2OeH1UgxqUwiyd2ykXV/BEvQl5U2o6A== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=suse.com; Received: from AM0PR0402MB3428.eurprd04.prod.outlook.com (2603:10a6:208:1a::25) by AS5PR04MB9895.eurprd04.prod.outlook.com (2603:10a6:20b:651::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6178.26; Tue, 14 Mar 2023 13:47:08 +0000 Received: from AM0PR0402MB3428.eurprd04.prod.outlook.com ([fe80::2b1f:7e5:94d0:3ba9]) by AM0PR0402MB3428.eurprd04.prod.outlook.com ([fe80::2b1f:7e5:94d0:3ba9%3]) with mapi id 15.20.6178.026; Tue, 14 Mar 2023 13:47:08 +0000 From: Chester Lin To: Linus Walleij , Andy Shevchenko Cc: Chester Lin , NXP S32 Linux Team , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Ghennadi Procopciuc , Andrei Stefanescu , Radu Pirea , =?utf-8?q?Andreas_F=C3=A4rber?= , Matthias Brugger Subject: [PATCH 3/3] pinctrl: s32cc: embed generic struct pingroup and pinfunction Date: Tue, 14 Mar 2023 21:46:42 +0800 Message-Id: <20230314134642.21535-4-clin@suse.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20230314134642.21535-1-clin@suse.com> References: <20230314134642.21535-1-clin@suse.com> X-ClientProxiedBy: FR0P281CA0114.DEUP281.PROD.OUTLOOK.COM (2603:10a6:d10:a8::16) To AM0PR0402MB3428.eurprd04.prod.outlook.com (2603:10a6:208:1a::25) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM0PR0402MB3428:EE_|AS5PR04MB9895:EE_ X-MS-Office365-Filtering-Correlation-Id: 6cbdc19d-9a3d-45a8-0069-08db24929acc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 6PdMiN577keC9xW6epd+PM3OIy8oc8EF5ueM3gzg2Qhicll95wvjAfIpz+5M8LY6qnTmnADzqVTNPlPpMdLpJBIMr84UAQ4g1Ah2Q9ulQuljlgMS+/w+TQeO3G4HbBiAHMYci4N763X8tQoC5ia1bX0/6g+Ds1iv04hkVcAfTh4Fl7unbnbZE9FEJffAvXmFZvP1Y4OA5dtFLjHzPnG5k+iGBLPHf/1H0Zm+Kcx5LjYsfGqzeMl1Zo7jO5SJw6TapVTGW7pZpvBAtjsQ86FOcjOFoqnTT/mFmsoMoYXXbS/pzRWlzfj2Kr6mhj9Ekpb9Rq6IKZH3oeC1R96QKCyRXWP5r6vXyI0MFEwZQMY1PyqQzeqLT9bOZhzq0RB2moz1gnZ7YFJrl3VU1/jWuzbLF1XxXjEYX037q/ToOwQ1G8QSzCCGX3tGOECO9WEjxrfG11gSz+1cv9E7ryVSG4+gW/3gAIdodBbCMEGkgKv4UEiXANo8xdId+m98D2WnXi56L+K2JuSJaveaf7bQETPjTNGtRi8FiBU4GkV9tM0VBMom6JiuChBAwJKwi997b/C+DXUNbBZ/emqLfaxjIDfALFBdh1PqMzNM0FE09uY0Fe/CNTU+SlbDoW1cnsrgGursmjOnP6reSSCQoZHGLs/IbMLpKcBpvWe4tnFZXLwAMuWm3xzAiYA6oYf07a/E+Blm X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM0PR0402MB3428.eurprd04.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230025)(39860400002)(396003)(346002)(366004)(136003)(376002)(451199018)(8936002)(36756003)(54906003)(478600001)(110136005)(316002)(66476007)(8676002)(66946007)(4326008)(66556008)(7416002)(41300700001)(2906002)(5660300002)(86362001)(6486002)(6512007)(6506007)(1076003)(26005)(6666004)(107886003)(186003)(2616005)(38100700002)(83380400001)(41533002); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: KADydvRg47cLt+SK/D2BiotqvWVFjSizOqI3ivk7ZLwDV1K21GzhMMovNcRbz5uka4nE1g3f6cXqwFlUF8V5PfkvHVVP6U26Eem2DE2z8mk6JBihNdaIA0RNPfg/BErv1ASmJ3WKMwGcD+JmkxaTYRufxPrYmHCL39UXBghqvQiOFsupINDPXiS+xHXHlbi3BFKN9ZcGG3DLdszog2A3/RoSbcAhgDWPeWe2WRdy221UjIoGB75GbddlX4Bj0XgC+sb8nU55mkRdLBT1FGmi/SHQAomLS2nBuLHjMaXx2gWGN0XMXV6mCJuPtnRQimolWuSrSSHLfs1NaTdhL3H/1CaJlpTxEiuKF8/FzfDJfy42hCssucNeV+Lsw28ir33mKJbsi0Mjkl7cmMHJcPors+ReQig3Z/ur8At2DbL+GNEgi/4CVozXgdG3kzzmKDpC+YJwKSkbNAlASUdHrbxk5mcUTE+7UiePtJR/OnqtiI6PhnSLxAIlwxVU/9+y5Ht0xHlKvHZ6uwVsdD61msbg89+Pzi1kn6vkcrx5HuK6eNauUu5BK/VrXt2rRbJRZCBwq+m/KLqQ/GnZ+Jca/p66c4N21zwhUIk5dRa40fWa9qL66efqaHrxdY5q16ILZT5SDjThhD1bafrmETTgZ6Ii+6z79gl6JrXwMCAQSdHlU81Bk0x9hXSEn16RCL9h8Xh71xJJxj3X9Vm60qEwkpiADgTAFJgbvOvyZKNLNAee/TMIR311dMWMR/KdobQ0lzgkNAay8SH4X04ObFXLK+x+2qHj9lmPgaYSePSrg2u/+MSJ6mj5ErvQNjV9vK2fR4LsWH7xowtqyRJJQj+hjmZ1vea0FSxNzlrLAWfC1VR3HW1HgOitJkQ24efEvbyXufEEd9RTv8MuxdMLJana4z7yb2cyJfUjex6DhKI+yNHiLw/0jImeJvApw8c19sxHjaVu/R7du0VijXqnseMvmGQyRxhpWhoShMxQYHE6G0m+dq1EYuUsx8HhCq5n1wOrpS2XzAh6EKvBYcY4s5rk7685Pof6lh30Ee5zbxgt4LF7owVJaYrvIsYfui9pehGHsyhIDIQekv4FZCFGItLybKHXnSmerKlnTD9tok0wM2AvCvLFYOe26HE43ZHJVvHNpFUFd9j1SU0b0+gSb+TJ8vAAqnpWWxV2Gkre9ocmrdGvVm6B2wlho4rSBlloyEmW5X+pJ9AxPmB+8lY9aFsCcEf/t9Se4MOkt26WS6tbm7BncCJdd+X6wpIMKIFR1Sn3jJV2QFBAtTMQJgDLyUzLORY79bxm0/bwNoSAv2OB7sqq7UKLY5UJMxxHY6URfwMSq/fxImM/1wuiwui+tpvwVhPsPK7Q3WpzsDCkBQZvaIqA08f3uN++Hij3LFZ0tsDQXCzJdObQyqZRvG+avGMgZzR3QjkvFtPl25i3zLlNazPr1VnpBY3G4fzux0kSNx8IxVK+XIo2+za68ipxHlCSyIitNY+nZGpM2XNJH7vA8eTLViY8PKuhqS5ns+Xt4rlHXHnujRDgH4IzAtNEHEVRfUfDKTLPqgRJTIvEL48Ja8+OG4k= X-OriginatorOrg: suse.com X-MS-Exchange-CrossTenant-Network-Message-Id: 6cbdc19d-9a3d-45a8-0069-08db24929acc X-MS-Exchange-CrossTenant-AuthSource: AM0PR0402MB3428.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Mar 2023 13:47:08.7380 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f7a17af6-1c5c-4a36-aa8b-f5be247aa4ba X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: UBGdgA8JzEHD/PmGqHj3GBoG9qUUKmgGj72b8C7N7VtBaJJYWtn7S8v+jTJqJ2jN X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS5PR04MB9895 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Use generic data structure to describe pin control functions and groups in S32 SoC family and drop duplicated struct members. Signed-off-by: Chester Lin --- drivers/pinctrl/nxp/pinctrl-s32.h | 22 +++----- drivers/pinctrl/nxp/pinctrl-s32cc.c | 78 ++++++++++++++++------------- 2 files changed, 49 insertions(+), 51 deletions(-) diff --git a/drivers/pinctrl/nxp/pinctrl-s32.h b/drivers/pinctrl/nxp/pinctrl-s32.h index 545bf16b988d..1a0aa1995908 100644 --- a/drivers/pinctrl/nxp/pinctrl-s32.h +++ b/drivers/pinctrl/nxp/pinctrl-s32.h @@ -15,29 +15,21 @@ struct platform_device; /** * struct s32_pin_group - describes an S32 pin group - * @name: the name of this specific pin group - * @npins: the number of pins in this group array, i.e. the number of - * elements in pin_ids and pin_sss so we can iterate over that array - * @pin_ids: an array of pin IDs in this group - * @pin_sss: an array of source signal select configs paired with pin_ids + * @data: generic data describes group name, number of pins, and a pin array in + this group. + * @pin_sss: an array of source signal select configs paired with pin array. */ struct s32_pin_group { - const char *name; - unsigned int npins; - unsigned int *pin_ids; + struct pingroup data; unsigned int *pin_sss; }; /** - * struct s32_pmx_func - describes S32 pinmux functions - * @name: the name of this specific function - * @groups: corresponding pin groups - * @num_groups: the number of groups + * struct s32_pmx_func - describes an S32 pinmux function + * @data: generic data to describe function name and associated groups. */ struct s32_pmx_func { - const char *name; - const char **groups; - unsigned int num_groups; + struct pinfunction data; }; /** diff --git a/drivers/pinctrl/nxp/pinctrl-s32cc.c b/drivers/pinctrl/nxp/pinctrl-s32cc.c index 9508fc1e9a90..76442c1bc7be 100644 --- a/drivers/pinctrl/nxp/pinctrl-s32cc.c +++ b/drivers/pinctrl/nxp/pinctrl-s32cc.c @@ -191,7 +191,7 @@ static const char *s32_get_group_name(struct pinctrl_dev *pctldev, struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); const struct s32_pinctrl_soc_info *info = ipctl->info; - return info->groups[selector].name; + return info->groups[selector].data.name; } static int s32_get_group_pins(struct pinctrl_dev *pctldev, @@ -201,8 +201,8 @@ static int s32_get_group_pins(struct pinctrl_dev *pctldev, struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); const struct s32_pinctrl_soc_info *info = ipctl->info; - *pins = info->groups[selector].pin_ids; - *npins = info->groups[selector].npins; + *pins = info->groups[selector].data.pins; + *npins = info->groups[selector].data.npins; return 0; } @@ -317,23 +317,23 @@ static int s32_pmx_set(struct pinctrl_dev *pctldev, unsigned int selector, grp = &info->groups[group]; dev_dbg(ipctl->dev, "set mux for function %s group %s\n", - info->functions[selector].name, grp->name); + info->functions[selector].data.name, grp->data.name); /* Check beforehand so we don't have a partial config. */ - for (i = 0; i < grp->npins; i++) { - if (s32_check_pin(pctldev, grp->pin_ids[i]) != 0) { + for (i = 0; i < grp->data.npins; i++) { + if (s32_check_pin(pctldev, grp->data.pins[i]) != 0) { dev_err(info->dev, "invalid pin: %u in group: %u\n", - grp->pin_ids[i], group); + grp->data.pins[i], group); return -EINVAL; } } - for (i = 0, ret = 0; i < grp->npins && !ret; i++) { - ret = s32_regmap_update(pctldev, grp->pin_ids[i], + for (i = 0, ret = 0; i < grp->data.npins && !ret; i++) { + ret = s32_regmap_update(pctldev, grp->data.pins[i], S32_MSCR_SSS_MASK, grp->pin_sss[i]); if (ret) { dev_err(info->dev, "Failed to set pin %u\n", - grp->pin_ids[i]); + grp->data.pins[i]); return ret; } } @@ -355,7 +355,7 @@ static const char *s32_pmx_get_func_name(struct pinctrl_dev *pctldev, struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); const struct s32_pinctrl_soc_info *info = ipctl->info; - return info->functions[selector].name; + return info->functions[selector].data.name; } static int s32_pmx_get_groups(struct pinctrl_dev *pctldev, @@ -366,8 +366,8 @@ static int s32_pmx_get_groups(struct pinctrl_dev *pctldev, struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); const struct s32_pinctrl_soc_info *info = ipctl->info; - *groups = info->functions[selector].groups; - *num_groups = info->functions[selector].num_groups; + *groups = info->functions[selector].data.groups; + *num_groups = info->functions[selector].data.ngroups; return 0; } @@ -611,8 +611,8 @@ static int s32_pconf_group_set(struct pinctrl_dev *pctldev, unsigned int selecto int i, ret; grp = &info->groups[selector]; - for (i = 0; i < grp->npins; i++) { - ret = s32_pinconf_mscr_update(pctldev, grp->pin_ids[i], + for (i = 0; i < grp->data.npins; i++) { + ret = s32_pinconf_mscr_update(pctldev, grp->data.pins[i], configs, num_configs); if (ret) return ret; @@ -646,9 +646,9 @@ static void s32_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, seq_puts(s, "\n"); grp = &info->groups[selector]; - for (i = 0; i < grp->npins; i++) { - name = pin_get_name(pctldev, grp->pin_ids[i]); - ret = s32_regmap_read(pctldev, grp->pin_ids[i], &config); + for (i = 0; i < grp->data.npins; i++) { + name = pin_get_name(pctldev, grp->data.pins[i]); + ret = s32_regmap_read(pctldev, grp->data.pins[i], &config); if (ret) return; seq_printf(s, "%s: 0x%x\n", name, config); @@ -741,6 +741,7 @@ static int s32_pinctrl_parse_groups(struct device_node *np, const __be32 *p; struct device *dev; struct property *prop; + unsigned int *pins, *sss; int i, npins; u32 pinmux; @@ -749,38 +750,40 @@ static int s32_pinctrl_parse_groups(struct device_node *np, dev_dbg(dev, "group: %pOFn\n", np); /* Initialise group */ - grp->name = np->name; + grp->data.name = np->name; npins = of_property_count_elems_of_size(np, "pinmux", sizeof(u32)); if (npins < 0) { dev_err(dev, "Failed to read 'pinmux' property in node %s.\n", - grp->name); + grp->data.name); return -EINVAL; } if (!npins) { - dev_err(dev, "The group %s has no pins.\n", grp->name); + dev_err(dev, "The group %s has no pins.\n", grp->data.name); return -EINVAL; } - grp->npins = npins; + grp->data.npins = npins; - grp->pin_ids = devm_kcalloc(info->dev, grp->npins, + pins = devm_kcalloc(info->dev, grp->data.npins, sizeof(unsigned int), GFP_KERNEL); - grp->pin_sss = devm_kcalloc(info->dev, grp->npins, + sss = devm_kcalloc(info->dev, grp->data.npins, sizeof(unsigned int), GFP_KERNEL); - if (!grp->pin_ids || !grp->pin_sss) + if (!pins || !sss) return -ENOMEM; i = 0; of_property_for_each_u32(np, "pinmux", prop, p, pinmux) { - grp->pin_ids[i] = get_pin_no(pinmux); - grp->pin_sss[i] = get_pin_func(pinmux); + pins[i] = get_pin_no(pinmux); + sss[i] = get_pin_func(pinmux); - dev_dbg(info->dev, "pin-id: 0x%x, sss: 0x%x", - grp->pin_ids[i], grp->pin_sss[i]); + dev_dbg(info->dev, "pin: 0x%x, sss: 0x%x", pins[i], sss[i]); i++; } + grp->data.pins = pins; + grp->pin_sss = sss; + return 0; } @@ -791,6 +794,7 @@ static int s32_pinctrl_parse_functions(struct device_node *np, struct device_node *child; struct s32_pmx_func *func; struct s32_pin_group *grp; + char **groups; u32 i = 0; int ret = 0; @@ -799,19 +803,19 @@ static int s32_pinctrl_parse_functions(struct device_node *np, func = &info->functions[index]; /* Initialise function */ - func->name = np->name; - func->num_groups = of_get_child_count(np); - if (func->num_groups == 0) { + func->data.name = np->name; + func->data.ngroups = of_get_child_count(np); + if (func->data.ngroups == 0) { dev_err(info->dev, "no groups defined in %pOF\n", np); return -EINVAL; } - func->groups = devm_kcalloc(info->dev, func->num_groups, - sizeof(char *), GFP_KERNEL); - if (!func->groups) + groups = devm_kcalloc(info->dev, func->data.ngroups, + sizeof(char *), GFP_KERNEL); + if (!groups) return -ENOMEM; for_each_child_of_node(np, child) { - func->groups[i] = child->name; + groups[i] = (char *)child->name; grp = &info->groups[info->grp_index++]; ret = s32_pinctrl_parse_groups(child, grp, info); if (ret) @@ -819,6 +823,8 @@ static int s32_pinctrl_parse_functions(struct device_node *np, i++; } + func->data.groups = (const char **)groups; + return 0; }