From patchwork Tue Mar 14 15:35:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 663043 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 842FEC6FD1C for ; Tue, 14 Mar 2023 15:37:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231760AbjCNPha (ORCPT ); Tue, 14 Mar 2023 11:37:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43602 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231769AbjCNPhJ (ORCPT ); Tue, 14 Mar 2023 11:37:09 -0400 Received: from mail-lj1-x22b.google.com (mail-lj1-x22b.google.com [IPv6:2a00:1450:4864:20::22b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6234A5C9D4 for ; Tue, 14 Mar 2023 08:35:59 -0700 (PDT) Received: by mail-lj1-x22b.google.com with SMTP id h3so16423077lja.12 for ; Tue, 14 Mar 2023 08:35:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678808148; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BU7SujQTaU90GwhqWBCXuwboKMKnBmogSD90LjZY5/Y=; b=ut6lD63El1fmQP8JF4V1uEHf/KoNIMMChfMDQzHyktO8ma1fGtbQCTnMwsKwigvSI8 YhwWyYDnC9tk2TnOkyBQ2gzLPaZWRYjOM1yI2qn55E21BJbeH9igAj/UZH6rUE4gY17a NjiQCqS+WwzwQ/H4rELGdtQ8AFB8uPBAcPV1btPD7pSS6lb52rY4DUcfmVSYcQFfK/I2 /ehZ+1qAUR0K+A9NEi5CGtFjWDWsSSWmUimzi/vFpZ19vgXN1Zc0yORQwBe206drSHm/ wBvxCW9OMhGl2uGZwUv0fYCbrNYfhg0tD45rLKpgL1k9iBhLJOkKT+a3G7nKTLivAA++ mBNw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678808148; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BU7SujQTaU90GwhqWBCXuwboKMKnBmogSD90LjZY5/Y=; b=BBHyUuvAntoe4GygBiLcL7AnlIQl1LfNA58wj5FXbYii1bW9tavJPNFbkTb+oBgewN ap0Hq+e1t7Hs95qdl+IKd49kd9taiwPUUVK4XwTVKosdY5Ilmj0gnR3CDKwL0KU3mued 8mXk4AHMJhbDDEs5NbAHyYGuUEj5SYUnWB2Qgo+Nu42xev7LV0eiUYcos5DmcUZ7DOkq a76jsWnhPIGCXDhUPCqhF45vDL2I4rjyvB8DJpkY5bueCx20M/ipuDlGABY5i20vFVsx 6JXtu2MUggtDCtD+DsZJYCMSp+Nn4qt8YPFgITHAbBi/hXy+nq+jt4OvBfuVRhkQNivg tY1A== X-Gm-Message-State: AO0yUKV39nGtPaaUHlB5LIaDvtcjgGfUZWIop0rhrEyZkueSRSN2Vgqk dID2p8KhgC9Y36+b8UFedIf5ag== X-Google-Smtp-Source: AK7set+1Zgj5gNQc9n7PpGwR2ZmaVnO2W3pwevVm83Me+ElvExLhltt/TlikQf7lj2B48BsGaHl2bQ== X-Received: by 2002:a2e:730b:0:b0:295:b0a5:f67a with SMTP id o11-20020a2e730b000000b00295b0a5f67amr12016215ljc.22.1678808148506; Tue, 14 Mar 2023 08:35:48 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id z8-20020a2eb528000000b0029573844d03sm470854ljm.109.2023.03.14.08.35.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Mar 2023 08:35:48 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Abhinav Kumar Cc: Stephen Boyd , David Airlie , Daniel Vetter , Bjorn Andersson , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH v6 03/32] drm/msm/dpu: move SSPP debugfs creation to dpu_kms.c Date: Tue, 14 Mar 2023 18:35:16 +0300 Message-Id: <20230314153545.3442879-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230314153545.3442879-1-dmitry.baryshkov@linaro.org> References: <20230314153545.3442879-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org As SSPP blocks are now visible through dpu_kms->rm.sspp_blocks, move SSPP debugfs creation from dpu_plane to dpu_kms. We are going to break the 1:1 correspondence between planes and SSPPs, so it makes no sense anymore to create SSPP debugfs entries in dpu_plane.c Reviewed-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 1 - drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 18 ++++++++++++++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 16 ---------------- 3 files changed, 18 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h index bbff908e6dbe..c30f168b6c0a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h @@ -388,7 +388,6 @@ struct dpu_hw_sspp *dpu_hw_sspp_init(enum dpu_sspp idx, */ void dpu_hw_sspp_destroy(struct dpu_hw_sspp *ctx); -void dpu_debugfs_sspp_init(struct dpu_kms *dpu_kms, struct dentry *debugfs_root); int _dpu_hw_sspp_init_debugfs(struct dpu_hw_sspp *hw_pipe, struct dpu_kms *kms, struct dentry *entry); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index 681dd2e0c7e8..35194262e628 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -250,6 +250,24 @@ void dpu_debugfs_create_regset32(const char *name, umode_t mode, debugfs_create_file(name, mode, parent, regset, &dpu_regset32_fops); } +static void dpu_debugfs_sspp_init(struct dpu_kms *dpu_kms, struct dentry *debugfs_root) +{ + struct dentry *entry = debugfs_create_dir("sspp", debugfs_root); + int i; + + if (IS_ERR(entry)) + return; + + for (i = SSPP_NONE; i < SSPP_MAX; i++) { + struct dpu_hw_sspp *hw = dpu_rm_get_sspp(&dpu_kms->rm, i); + + if (!hw) + continue; + + _dpu_hw_sspp_init_debugfs(hw, dpu_kms, entry); + } +} + static int dpu_kms_debugfs_init(struct msm_kms *kms, struct drm_minor *minor) { struct dpu_kms *dpu_kms = to_dpu_kms(kms); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index b054055f120b..2b0ebdd4c207 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -1399,22 +1399,6 @@ void dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable) _dpu_plane_set_qos_ctrl(plane, enable, DPU_PLANE_QOS_PANIC_CTRL); pm_runtime_put_sync(&dpu_kms->pdev->dev); } - -/* SSPP live inside dpu_plane private data only. Enumerate them here. */ -void dpu_debugfs_sspp_init(struct dpu_kms *dpu_kms, struct dentry *debugfs_root) -{ - struct drm_plane *plane; - struct dentry *entry = debugfs_create_dir("sspp", debugfs_root); - - if (IS_ERR(entry)) - return; - - drm_for_each_plane(plane, dpu_kms->dev) { - struct dpu_plane *pdpu = to_dpu_plane(plane); - - _dpu_hw_sspp_init_debugfs(pdpu->pipe_hw, dpu_kms, entry); - } -} #endif static bool dpu_plane_format_mod_supported(struct drm_plane *plane, From patchwork Tue Mar 14 15:35:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 663042 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 50F9CC74A4B for ; Tue, 14 Mar 2023 15:37:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231782AbjCNPhc (ORCPT ); Tue, 14 Mar 2023 11:37:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44114 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231725AbjCNPhL (ORCPT ); Tue, 14 Mar 2023 11:37:11 -0400 Received: from mail-lj1-x22d.google.com (mail-lj1-x22d.google.com [IPv6:2a00:1450:4864:20::22d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 878B1ADC34 for ; Tue, 14 Mar 2023 08:36:04 -0700 (PDT) Received: by mail-lj1-x22d.google.com with SMTP id a32so16444507ljq.1 for ; Tue, 14 Mar 2023 08:36:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678808149; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=demNi9tY5y1rcHkWi3Rdcd6GdqUqaXSgbS47QqrmYDw=; b=nUvr0P7d/LVi575KjvQnzMqgnxYrsKxdbM4uVBEFiUSVUJzncfEzNYA3T68qc3zFx0 zBylrxHHGqrkbkhHnCByNUED9QdbqNBePUbms9N5HUayDDlXqdnQC8rdwSPqTuCxziiq hHyGY+UV5jburwc4eVeMXg/1QvOfr+1xw+FLVLqyhsUGXE9x5WVgX+45Hd/C3ypdwidk 4PT9D6g2mO1ddyKIUIEuHXZ1xHTAaJLTSlDYtBkJQBo4+XF/yAHseKCsinCLUkrAy8+e 4wfqU4+ZjXEExtRCwMHzSFqLMrISZMez1wPCAAvXWg01wjGlt0Aj1qlgzN1XPJRonFAf i+Mg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678808149; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=demNi9tY5y1rcHkWi3Rdcd6GdqUqaXSgbS47QqrmYDw=; b=i1bdWo9J3ISC2Inbwtu7XcmN4XGHxn2CgXb/iSVxAraTM2iJ3yQGumX3LvIpM7tnuu eukykHzqdx441BVtAxOLEPMR2g8LqqjhoBhBoHqExP0V+5Rcwmd7n2LGoYPM9xdJeIXO cfyy8KJ2fWN3NQtquVh/LhAx8j/EtNugYau42Vp1sFBglUlNEb2l7GZsUsYeyyMaXXuX Yf1n9kb/w9Q+sNs8lORHhS5Pj5Mnax6FVb3f2cac8r56p9yyriz7RLGL1JwNfRsK8r6d MJkaO6cKhLqIOgTXwLrDJtgUaiw+T2mshHo4POqZP+aJFOhOYRM2S0ISVHBus51mdA5G jb3g== X-Gm-Message-State: AO0yUKXmbt6MLGBsPyPhjK/zzAc9ZCHgNdqn1Kp6x7qR5KjoT8W7IfYb gTgme/cKYiNQ7vyySvtNAQy4mw== X-Google-Smtp-Source: AK7set+y/LQFDBwhtv1fMYkhSiPbToBHbFyzweRpHLfqV7qRT2hCubGz9Ag7usJPySn7h5SWnbdb7A== X-Received: by 2002:a05:651c:301:b0:295:9d32:a195 with SMTP id a1-20020a05651c030100b002959d32a195mr10165678ljp.32.1678808149178; Tue, 14 Mar 2023 08:35:49 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id z8-20020a2eb528000000b0029573844d03sm470854ljm.109.2023.03.14.08.35.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Mar 2023 08:35:48 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Abhinav Kumar Cc: Stephen Boyd , David Airlie , Daniel Vetter , Bjorn Andersson , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH v6 04/32] drm/msm/dpu: drop EAGAIN check from dpu_format_populate_layout Date: Tue, 14 Mar 2023 18:35:17 +0300 Message-Id: <20230314153545.3442879-5-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230314153545.3442879-1-dmitry.baryshkov@linaro.org> References: <20230314153545.3442879-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The pipe's layout is not cached, corresponding data structure is zeroed out each time in the dpu_plane_sspp_atomic_update(), right before the call to _dpu_plane_set_scanout() -> dpu_format_populate_layout(). Drop plane_addr comparison against previous layout and corresponding EAGAIN handling. Reviewed-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 10 +--------- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 4 +--- 2 files changed, 2 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c index d95540309d4d..ec1001e10f4f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c @@ -918,8 +918,7 @@ int dpu_format_populate_layout( struct drm_framebuffer *fb, struct dpu_hw_fmt_layout *layout) { - uint32_t plane_addr[DPU_MAX_PLANES]; - int i, ret; + int ret; if (!fb || !layout) { DRM_ERROR("invalid arguments\n"); @@ -940,9 +939,6 @@ int dpu_format_populate_layout( if (ret) return ret; - for (i = 0; i < DPU_MAX_PLANES; ++i) - plane_addr[i] = layout->plane_addr[i]; - /* Populate the addresses given the fb */ if (DPU_FORMAT_IS_UBWC(layout->format) || DPU_FORMAT_IS_TILE(layout->format)) @@ -950,10 +946,6 @@ int dpu_format_populate_layout( else ret = _dpu_format_populate_addrs_linear(aspace, fb, layout); - /* check if anything changed */ - if (!ret && !memcmp(plane_addr, layout->plane_addr, sizeof(plane_addr))) - ret = -EAGAIN; - return ret; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 2b0ebdd4c207..d6518ef1beb2 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -476,9 +476,7 @@ static void _dpu_plane_set_scanout(struct drm_plane *plane, int ret; ret = dpu_format_populate_layout(aspace, fb, &pipe_cfg->layout); - if (ret == -EAGAIN) - DPU_DEBUG_PLANE(pdpu, "not updating same src addrs\n"); - else if (ret) + if (ret) DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret); else if (pdpu->pipe_hw->ops.setup_sourceaddress) { trace_dpu_plane_set_scanout(pdpu->pipe_hw->idx, From patchwork Tue Mar 14 15:35:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 663041 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 051DEC74A4B for ; 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Tue, 14 Mar 2023 08:35:49 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Abhinav Kumar Cc: Stephen Boyd , David Airlie , Daniel Vetter , Bjorn Andersson , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH v6 05/32] drm/msm/dpu: move pipe_hw to dpu_plane_state Date: Tue, 14 Mar 2023 18:35:18 +0300 Message-Id: <20230314153545.3442879-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230314153545.3442879-1-dmitry.baryshkov@linaro.org> References: <20230314153545.3442879-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org In preparation to adding fully virtualized planes, move struct dpu_hw_sspp instance from struct dpu_plane to struct dpu_plane_state, as it will become a part of state (variable, changes during runtime) rather than part of a plane (ideally should be statically allocated during boot). The sspp pointer is set at the dpu_plane_reset(), since this is the function which allocates the state. Once we have fully virtual plane<->SSPP relationship, the SSPP will be allocated dynamically in the dpu_plane_atomic_check() function. Reviewed-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 107 ++++++++++++---------- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 2 + 2 files changed, 62 insertions(+), 47 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index d6518ef1beb2..546629232e3d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -104,7 +104,6 @@ struct dpu_plane { enum dpu_sspp pipe; - struct dpu_hw_sspp *pipe_hw; uint32_t color_fill; bool is_error; bool is_rt_pipe; @@ -279,6 +278,7 @@ static void _dpu_plane_set_qos_lut(struct drm_plane *plane, struct drm_framebuffer *fb, struct dpu_hw_sspp_cfg *pipe_cfg) { struct dpu_plane *pdpu = to_dpu_plane(plane); + struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state); const struct dpu_format *fmt = NULL; u64 qos_lut; u32 total_fl = 0, lut_usage; @@ -310,7 +310,7 @@ static void _dpu_plane_set_qos_lut(struct drm_plane *plane, fmt ? (char *)&fmt->base.pixel_format : NULL, pdpu->is_rt_pipe, total_fl, qos_lut); - pdpu->pipe_hw->ops.setup_creq_lut(pdpu->pipe_hw, qos_lut); + pstate->hw_sspp->ops.setup_creq_lut(pstate->hw_sspp, qos_lut); } /** @@ -322,6 +322,7 @@ static void _dpu_plane_set_danger_lut(struct drm_plane *plane, struct drm_framebuffer *fb) { struct dpu_plane *pdpu = to_dpu_plane(plane); + struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state); const struct dpu_format *fmt = NULL; u32 danger_lut, safe_lut; @@ -361,7 +362,7 @@ static void _dpu_plane_set_danger_lut(struct drm_plane *plane, danger_lut, safe_lut); - pdpu->pipe_hw->ops.setup_danger_safe_lut(pdpu->pipe_hw, + pstate->hw_sspp->ops.setup_danger_safe_lut(pstate->hw_sspp, danger_lut, safe_lut); } @@ -375,14 +376,15 @@ static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane, bool enable, u32 flags) { struct dpu_plane *pdpu = to_dpu_plane(plane); + struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state); struct dpu_hw_pipe_qos_cfg pipe_qos_cfg; memset(&pipe_qos_cfg, 0, sizeof(pipe_qos_cfg)); if (flags & DPU_PLANE_QOS_VBLANK_CTRL) { - pipe_qos_cfg.creq_vblank = pdpu->pipe_hw->cap->sblk->creq_vblank; + pipe_qos_cfg.creq_vblank = pstate->hw_sspp->cap->sblk->creq_vblank; pipe_qos_cfg.danger_vblank = - pdpu->pipe_hw->cap->sblk->danger_vblank; + pstate->hw_sspp->cap->sblk->danger_vblank; pipe_qos_cfg.vblank_en = enable; } @@ -408,7 +410,7 @@ static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane, pipe_qos_cfg.danger_vblank, pdpu->is_rt_pipe); - pdpu->pipe_hw->ops.setup_qos_ctrl(pdpu->pipe_hw, + pstate->hw_sspp->ops.setup_qos_ctrl(pstate->hw_sspp, &pipe_qos_cfg); } @@ -422,18 +424,19 @@ static void _dpu_plane_set_ot_limit(struct drm_plane *plane, struct drm_crtc *crtc, struct dpu_hw_sspp_cfg *pipe_cfg) { struct dpu_plane *pdpu = to_dpu_plane(plane); + struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state); struct dpu_vbif_set_ot_params ot_params; struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); memset(&ot_params, 0, sizeof(ot_params)); - ot_params.xin_id = pdpu->pipe_hw->cap->xin_id; - ot_params.num = pdpu->pipe_hw->idx - SSPP_NONE; + ot_params.xin_id = pstate->hw_sspp->cap->xin_id; + ot_params.num = pstate->hw_sspp->idx - SSPP_NONE; ot_params.width = drm_rect_width(&pipe_cfg->src_rect); ot_params.height = drm_rect_height(&pipe_cfg->src_rect); ot_params.is_wfd = !pdpu->is_rt_pipe; ot_params.frame_rate = drm_mode_vrefresh(&crtc->mode); ot_params.vbif_idx = VBIF_RT; - ot_params.clk_ctrl = pdpu->pipe_hw->cap->clk_ctrl; + ot_params.clk_ctrl = pstate->hw_sspp->cap->clk_ctrl; ot_params.rd = true; dpu_vbif_set_ot_limit(dpu_kms, &ot_params); @@ -446,14 +449,15 @@ static void _dpu_plane_set_ot_limit(struct drm_plane *plane, static void _dpu_plane_set_qos_remap(struct drm_plane *plane) { struct dpu_plane *pdpu = to_dpu_plane(plane); + struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state); struct dpu_vbif_set_qos_params qos_params; struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); memset(&qos_params, 0, sizeof(qos_params)); qos_params.vbif_idx = VBIF_RT; - qos_params.clk_ctrl = pdpu->pipe_hw->cap->clk_ctrl; - qos_params.xin_id = pdpu->pipe_hw->cap->xin_id; - qos_params.num = pdpu->pipe_hw->idx - SSPP_VIG0; + qos_params.clk_ctrl = pstate->hw_sspp->cap->clk_ctrl; + qos_params.xin_id = pstate->hw_sspp->cap->xin_id; + qos_params.num = pstate->hw_sspp->idx - SSPP_VIG0; qos_params.is_rt = pdpu->is_rt_pipe; DPU_DEBUG_PLANE(pdpu, "pipe:%d vbif:%d xin:%d rt:%d, clk_ctrl:%d\n", @@ -478,11 +482,11 @@ static void _dpu_plane_set_scanout(struct drm_plane *plane, ret = dpu_format_populate_layout(aspace, fb, &pipe_cfg->layout); if (ret) DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret); - else if (pdpu->pipe_hw->ops.setup_sourceaddress) { - trace_dpu_plane_set_scanout(pdpu->pipe_hw->idx, + else if (pstate->hw_sspp->ops.setup_sourceaddress) { + trace_dpu_plane_set_scanout(pstate->hw_sspp->idx, &pipe_cfg->layout, pstate->multirect_index); - pdpu->pipe_hw->ops.setup_sourceaddress(pdpu->pipe_hw, pipe_cfg, + pstate->hw_sspp->ops.setup_sourceaddress(pstate->hw_sspp, pipe_cfg, pstate->multirect_index); } } @@ -534,7 +538,7 @@ static void _dpu_plane_setup_scaler3(struct dpu_plane *pdpu, scale_cfg->src_height[i] /= chroma_subsmpl_v; } - if (pdpu->pipe_hw->cap->features & + if (pstate->hw_sspp->cap->features & BIT(DPU_SSPP_SCALER_QSEED4)) { scale_cfg->preload_x[i] = DPU_QSEED4_DEFAULT_PRELOAD_H; scale_cfg->preload_y[i] = DPU_QSEED4_DEFAULT_PRELOAD_V; @@ -607,6 +611,7 @@ static const struct dpu_csc_cfg dpu_csc10_YUV2RGB_601L = { static const struct dpu_csc_cfg *_dpu_plane_get_csc(struct dpu_plane *pdpu, const struct dpu_format *fmt) { + struct dpu_plane_state *pstate = to_dpu_plane_state(pdpu->base.state); const struct dpu_csc_cfg *csc_ptr; if (!pdpu) { @@ -617,7 +622,7 @@ static const struct dpu_csc_cfg *_dpu_plane_get_csc(struct dpu_plane *pdpu, cons if (!DPU_FORMAT_IS_YUV(fmt)) return NULL; - if (BIT(DPU_SSPP_CSC_10BIT) & pdpu->pipe_hw->cap->features) + if (BIT(DPU_SSPP_CSC_10BIT) & pstate->hw_sspp->cap->features) csc_ptr = &dpu_csc10_YUV2RGB_601L; else csc_ptr = &dpu_csc_YUV2RGB_601L; @@ -660,8 +665,8 @@ static void _dpu_plane_setup_scaler(struct dpu_plane *pdpu, _dpu_plane_setup_pixel_ext(&scaler3_cfg, &pixel_ext, src_width, src_height, info->hsub, info->vsub); - if (pdpu->pipe_hw->ops.setup_pe) - pdpu->pipe_hw->ops.setup_pe(pdpu->pipe_hw, + if (pstate->hw_sspp->ops.setup_pe) + pstate->hw_sspp->ops.setup_pe(pstate->hw_sspp, &pixel_ext); /** @@ -669,9 +674,9 @@ static void _dpu_plane_setup_scaler(struct dpu_plane *pdpu, * bypassed. Still we need to update alpha and bitwidth * ONLY for RECT0 */ - if (pdpu->pipe_hw->ops.setup_scaler && + if (pstate->hw_sspp->ops.setup_scaler && pstate->multirect_index != DPU_SSPP_RECT_1) - pdpu->pipe_hw->ops.setup_scaler(pdpu->pipe_hw, + pstate->hw_sspp->ops.setup_scaler(pstate->hw_sspp, pipe_cfg, &scaler3_cfg); } @@ -700,8 +705,8 @@ static int _dpu_plane_color_fill(struct dpu_plane *pdpu, fmt = dpu_get_dpu_format(DRM_FORMAT_ABGR8888); /* update sspp */ - if (fmt && pdpu->pipe_hw->ops.setup_solidfill) { - pdpu->pipe_hw->ops.setup_solidfill(pdpu->pipe_hw, + if (fmt && pstate->hw_sspp->ops.setup_solidfill) { + pstate->hw_sspp->ops.setup_solidfill(pstate->hw_sspp, (color & 0xFFFFFF) | ((alpha & 0xFF) << 24), pstate->multirect_index); @@ -715,13 +720,13 @@ static int _dpu_plane_color_fill(struct dpu_plane *pdpu, pipe_cfg.src_rect.y2 = drm_rect_height(&pipe_cfg.dst_rect); - if (pdpu->pipe_hw->ops.setup_format) - pdpu->pipe_hw->ops.setup_format(pdpu->pipe_hw, + if (pstate->hw_sspp->ops.setup_format) + pstate->hw_sspp->ops.setup_format(pstate->hw_sspp, fmt, DPU_SSPP_SOLID_FILL, pstate->multirect_index); - if (pdpu->pipe_hw->ops.setup_rects) - pdpu->pipe_hw->ops.setup_rects(pdpu->pipe_hw, + if (pstate->hw_sspp->ops.setup_rects) + pstate->hw_sspp->ops.setup_rects(pstate->hw_sspp, &pipe_cfg, pstate->multirect_index); @@ -973,8 +978,8 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, uint32_t min_src_size, max_linewidth; unsigned int rotation; uint32_t supported_rotations; - const struct dpu_sspp_cfg *pipe_hw_caps = pdpu->pipe_hw->cap; - const struct dpu_sspp_sub_blks *sblk = pdpu->pipe_hw->cap->sblk; + const struct dpu_sspp_cfg *pipe_hw_caps = pstate->hw_sspp->cap; + const struct dpu_sspp_sub_blks *sblk = pstate->hw_sspp->cap->sblk; if (new_plane_state->crtc) crtc_state = drm_atomic_get_new_crtc_state(state, @@ -1087,12 +1092,12 @@ void dpu_plane_flush(struct drm_plane *plane) else if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG) /* force 100% alpha */ _dpu_plane_color_fill(pdpu, pdpu->color_fill, 0xFF); - else if (pdpu->pipe_hw && pdpu->pipe_hw->ops.setup_csc) { + else if (pstate->hw_sspp && pstate->hw_sspp->ops.setup_csc) { const struct dpu_format *fmt = to_dpu_format(msm_framebuffer_format(plane->state->fb)); const struct dpu_csc_cfg *csc_ptr = _dpu_plane_get_csc(pdpu, fmt); if (csc_ptr) - pdpu->pipe_hw->ops.setup_csc(pdpu->pipe_hw, csc_ptr); + pstate->hw_sspp->ops.setup_csc(pstate->hw_sspp, csc_ptr); } /* flag h/w flush complete */ @@ -1162,21 +1167,21 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) return; } - if (pdpu->pipe_hw->ops.setup_rects) { - pdpu->pipe_hw->ops.setup_rects(pdpu->pipe_hw, + if (pstate->hw_sspp->ops.setup_rects) { + pstate->hw_sspp->ops.setup_rects(pstate->hw_sspp, &pipe_cfg, pstate->multirect_index); } _dpu_plane_setup_scaler(pdpu, pstate, fmt, false, &pipe_cfg); - if (pdpu->pipe_hw->ops.setup_multirect) - pdpu->pipe_hw->ops.setup_multirect( - pdpu->pipe_hw, + if (pstate->hw_sspp->ops.setup_multirect) + pstate->hw_sspp->ops.setup_multirect( + pstate->hw_sspp, pstate->multirect_index, pstate->multirect_mode); - if (pdpu->pipe_hw->ops.setup_format) { + if (pstate->hw_sspp->ops.setup_format) { unsigned int rotation = pstate->rotation; src_flags = 0x0; @@ -1191,10 +1196,10 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) src_flags |= DPU_SSPP_ROT_90; /* update format */ - pdpu->pipe_hw->ops.setup_format(pdpu->pipe_hw, fmt, src_flags, + pstate->hw_sspp->ops.setup_format(pstate->hw_sspp, fmt, src_flags, pstate->multirect_index); - if (pdpu->pipe_hw->ops.setup_cdp) { + if (pstate->hw_sspp->ops.setup_cdp) { struct dpu_hw_cdp_cfg cdp_cfg; memset(&cdp_cfg, 0, sizeof(struct dpu_hw_cdp_cfg)); @@ -1208,7 +1213,8 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) DPU_FORMAT_IS_TILE(fmt); cdp_cfg.preload_ahead = DPU_SSPP_CDP_PRELOAD_AHEAD_64; - pdpu->pipe_hw->ops.setup_cdp(pdpu->pipe_hw, &cdp_cfg, pstate->multirect_index); + pstate->hw_sspp->ops.setup_cdp(pstate->hw_sspp, &cdp_cfg, + pstate->multirect_index); } } @@ -1348,10 +1354,9 @@ static void dpu_plane_atomic_print_state(struct drm_printer *p, const struct drm_plane_state *state) { const struct dpu_plane_state *pstate = to_dpu_plane_state(state); - const struct dpu_plane *pdpu = to_dpu_plane(state->plane); drm_printf(p, "\tstage=%d\n", pstate->stage); - drm_printf(p, "\tsspp=%s\n", pdpu->pipe_hw->cap->name); + drm_printf(p, "\tsspp=%s\n", pstate->hw_sspp->cap->name); drm_printf(p, "\tmultirect_mode=%s\n", dpu_get_multirect_mode(pstate->multirect_mode)); drm_printf(p, "\tmultirect_index=%s\n", dpu_get_multirect_index(pstate->multirect_index)); } @@ -1360,6 +1365,7 @@ static void dpu_plane_reset(struct drm_plane *plane) { struct dpu_plane *pdpu; struct dpu_plane_state *pstate; + struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); if (!plane) { DPU_ERROR("invalid plane\n"); @@ -1381,6 +1387,12 @@ static void dpu_plane_reset(struct drm_plane *plane) return; } + /* + * Set the SSPP here until we have proper virtualized DPU planes. + * This is the place where the state is allocated, so fill it fully. + */ + pstate->hw_sspp = dpu_rm_get_sspp(&dpu_kms->rm, pdpu->pipe); + __drm_atomic_helper_plane_reset(plane, &pstate->base); } @@ -1445,6 +1457,7 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev, struct dpu_plane *pdpu; struct msm_drm_private *priv = dev->dev_private; struct dpu_kms *kms = to_dpu_kms(priv->kms); + struct dpu_hw_sspp *pipe_hw; uint32_t num_formats; uint32_t supported_rotations; int ret = -EINVAL; @@ -1462,14 +1475,14 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev, pdpu->pipe = pipe; /* initialize underlying h/w driver */ - pdpu->pipe_hw = dpu_rm_get_sspp(&kms->rm, pipe); - if (!pdpu->pipe_hw || !pdpu->pipe_hw->cap || !pdpu->pipe_hw->cap->sblk) { + pipe_hw = dpu_rm_get_sspp(&kms->rm, pipe); + if (!pipe_hw || !pipe_hw->cap || !pipe_hw->cap->sblk) { DPU_ERROR("[%u]SSPP is invalid\n", pipe); goto clean_plane; } - format_list = pdpu->pipe_hw->cap->sblk->format_list; - num_formats = pdpu->pipe_hw->cap->sblk->num_formats; + format_list = pipe_hw->cap->sblk->format_list; + num_formats = pipe_hw->cap->sblk->num_formats; ret = drm_universal_plane_init(dev, plane, 0xff, &dpu_plane_funcs, format_list, num_formats, @@ -1491,7 +1504,7 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev, supported_rotations = DRM_MODE_REFLECT_MASK | DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180; - if (pdpu->pipe_hw->cap->features & BIT(DPU_SSPP_INLINE_ROTATION)) + if (pipe_hw->cap->features & BIT(DPU_SSPP_INLINE_ROTATION)) supported_rotations |= DRM_MODE_ROTATE_MASK; drm_plane_create_rotation_property(plane, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h index b7b1b05199c2..08a4b6a99f51 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h @@ -18,6 +18,7 @@ * struct dpu_plane_state: Define dpu extension of drm plane state object * @base: base drm plane state object * @aspace: pointer to address space for input/output buffers + * @hw_sspp: pointer to corresponding SSPP instance * @stage: assigned by crtc blender * @needs_qos_remap: qos remap settings need to be updated * @multirect_index: index of the rectangle of SSPP @@ -31,6 +32,7 @@ struct dpu_plane_state { struct drm_plane_state base; struct msm_gem_address_space *aspace; + struct dpu_hw_sspp *hw_sspp; enum dpu_stage stage; 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Reviewed-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 9 ++++----- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 9 ++++----- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 4 ++-- 3 files changed, 10 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c index a1492a7e43ce..3030cd3b253a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c @@ -419,19 +419,18 @@ static void dpu_hw_sspp_setup_pe_config(struct dpu_hw_sspp *ctx, } static void _dpu_hw_sspp_setup_scaler3(struct dpu_hw_sspp *ctx, - struct dpu_hw_sspp_cfg *sspp, - void *scaler_cfg) + struct dpu_hw_scaler3_cfg *scaler3_cfg, + const struct dpu_format *format) { u32 idx; - struct dpu_hw_scaler3_cfg *scaler3_cfg = scaler_cfg; - if (_sspp_subblk_offset(ctx, DPU_SSPP_SCALER_QSEED3, &idx) || !sspp + if (_sspp_subblk_offset(ctx, DPU_SSPP_SCALER_QSEED3, &idx) || !scaler3_cfg) return; dpu_hw_setup_scaler3(&ctx->hw, scaler3_cfg, idx, ctx->cap->sblk->scaler_blk.version, - sspp->layout.format); + format); } static u32 _dpu_hw_sspp_get_scaler3_ver(struct dpu_hw_sspp *ctx) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h index 5903413256ea..136b8713943f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h @@ -317,13 +317,12 @@ struct dpu_hw_sspp_ops { /** * setup_scaler - setup scaler - * @ctx: Pointer to pipe context - * @pipe_cfg: Pointer to pipe configuration - * @scaler_cfg: Pointer to scaler configuration + * @scaler3_cfg: Pointer to scaler configuration + * @format: pixel format parameters */ void (*setup_scaler)(struct dpu_hw_sspp *ctx, - struct dpu_hw_sspp_cfg *pipe_cfg, - void *scaler_cfg); + struct dpu_hw_scaler3_cfg *scaler3_cfg, + const struct dpu_format *format); /** * get_scaler_ver - get scaler h/w version diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 6ec39f937042..8c98385303ea 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -677,8 +677,8 @@ static void _dpu_plane_setup_scaler(struct dpu_sw_pipe *pipe, if (pipe_hw->ops.setup_scaler && pipe->multirect_index != DPU_SSPP_RECT_1) pipe_hw->ops.setup_scaler(pipe_hw, - pipe_cfg, - &scaler3_cfg); + &scaler3_cfg, + fmt); } /** From patchwork Tue Mar 14 15:35:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 663039 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9F9BBC6FD1F for ; Tue, 14 Mar 2023 15:37:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230038AbjCNPhk (ORCPT ); Tue, 14 Mar 2023 11:37:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39118 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229929AbjCNPhT (ORCPT ); Tue, 14 Mar 2023 11:37:19 -0400 Received: from mail-lj1-x231.google.com (mail-lj1-x231.google.com [IPv6:2a00:1450:4864:20::231]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B6CE1B3289 for ; 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Reviewed-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c index 3030cd3b253a..0a43c5682b2b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c @@ -563,11 +563,16 @@ static void dpu_hw_sspp_setup_csc(struct dpu_hw_sspp *ctx, static void dpu_hw_sspp_setup_solidfill(struct dpu_sw_pipe *pipe, u32 color) { struct dpu_hw_sspp *ctx = pipe->sspp; + struct dpu_hw_sspp_cfg cfg; u32 idx; if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx)) return; + /* cleanup source addresses */ + memset(&cfg, 0, sizeof(cfg)); + ctx->ops.setup_sourceaddress(pipe, &cfg); + if (pipe->multirect_index == DPU_SSPP_RECT_SOLO || pipe->multirect_index == DPU_SSPP_RECT_0) DPU_REG_WRITE(&ctx->hw, SSPP_SRC_CONSTANT_COLOR + idx, color); From patchwork Tue Mar 14 15:35:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 663038 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 12147C6FD1C for ; Tue, 14 Mar 2023 15:37:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231375AbjCNPhp (ORCPT ); Tue, 14 Mar 2023 11:37:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43446 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231359AbjCNPhY (ORCPT ); Tue, 14 Mar 2023 11:37:24 -0400 Received: from mail-lj1-x22c.google.com (mail-lj1-x22c.google.com [IPv6:2a00:1450:4864:20::22c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3D99AB3290 for ; Tue, 14 Mar 2023 08:36:18 -0700 (PDT) Received: by mail-lj1-x22c.google.com with SMTP id a32so16444775ljq.1 for ; Tue, 14 Mar 2023 08:36:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678808155; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7U9mRZZLSm5QarQQVbWxt//3fUoK3gGSiE5wb7ArKZQ=; b=THF2MLAl7BTo670y8alfRSATS7VWqPYBva1vy+6nyt+JCS6FdZxbHYOggqFm/ogQC7 rz38LjdqfvthtgCLL/Ey8jKgZstDVUNEHNX/lYrGUrDQGcvYNg66bN9MLuquDu4Cdqbf QCpblWrL44grm0WknvGn5aiQjAOiNdmEdumUOj7TTa2HDgWSVx6MV8T659NNsMSM9fZ0 EeBU14Jr8hiUPKRiahCcd9NeXb8VdXYeO6A6GHtTvGBaDc7Fa8IeuA4B24fcACWTE6XJ ONSYCMb9dIt4AFFLecO31TZbK4CS6nBsTMEWjxYRNmTJgkEMzOJezhX/Rl+OhzzRQiC+ ZpRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678808155; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7U9mRZZLSm5QarQQVbWxt//3fUoK3gGSiE5wb7ArKZQ=; b=ttpzauwIUFHKEOtOdE9CGUGo6TvN2ZHd7CnZf90LeUXphp7kQ5c/TjtgV7VTKO7tYo Ygwc6fDz5pAX5b6adSeo+qxC74hLN5075GOCvDjl52GsCTnnTMIvyBzM+27Vph2Hyx9h jr/PF/ROYV8nILFfXkUglNyTALgXv0/50mO3DEscuz7pad2aE9dA+3DOFp9llLkjdT8Q JBOzYzsKiGFJztQloPIjYRonIVn38Dr5SXej/bkWOuLUd0Vqv96eeeZP8V5iULIP2U2q vieneIn3tMjSM7I4tb9nTKGdKQtPsxjckfbqIkhExqyI7e7QnpXUvAwuGvBex/p8MZhK J1Pw== X-Gm-Message-State: AO0yUKWJ/azKZ4A/froF65wvd13YzFNfNZ+ZXMH6HKx0mNnBeOwNIkCl gqxkHgSQTodAZbm/TrnLabwDAA== X-Google-Smtp-Source: AK7set+6u6Z8XrmFvWainlSsPVtE1bJH3PIg3DbxS6lwTGWTF4Zv8G5b+BEN1IsxRwAdSiVZBzYFSg== X-Received: by 2002:a05:651c:10e:b0:295:a809:e014 with SMTP id a14-20020a05651c010e00b00295a809e014mr10784135ljb.6.1678808154823; Tue, 14 Mar 2023 08:35:54 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id z8-20020a2eb528000000b0029573844d03sm470854ljm.109.2023.03.14.08.35.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Mar 2023 08:35:54 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Abhinav Kumar Cc: Stephen Boyd , David Airlie , Daniel Vetter , Bjorn Andersson , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH v6 12/32] drm/msm/dpu: remove dpu_hw_fmt_layout from struct dpu_hw_sspp_cfg Date: Tue, 14 Mar 2023 18:35:25 +0300 Message-Id: <20230314153545.3442879-13-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230314153545.3442879-1-dmitry.baryshkov@linaro.org> References: <20230314153545.3442879-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Remove dpu_hw_fmt_layout instance from struct dpu_hw_sspp_cfg, leaving only src_rect and dst_rect. This way all the pipes used by the plane will have a common layout instance (as the framebuffer is shared between them), while still keeping a separate src/dst rectangle configuration for each pipe. Reviewed-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 32 ++++++++++----------- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 6 ++-- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 10 +++---- 3 files changed, 23 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c index ab95f2817378..e87c6377f315 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c @@ -490,7 +490,7 @@ static void dpu_hw_sspp_setup_rects(struct dpu_sw_pipe *pipe, } static void dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe *pipe, - struct dpu_hw_sspp_cfg *cfg) + struct dpu_hw_fmt_layout *layout) { struct dpu_hw_sspp *ctx = pipe->sspp; u32 ystride0, ystride1; @@ -501,41 +501,41 @@ static void dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe *pipe, return; if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) { - for (i = 0; i < ARRAY_SIZE(cfg->layout.plane_addr); i++) + for (i = 0; i < ARRAY_SIZE(layout->plane_addr); i++) DPU_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR + idx + i * 0x4, - cfg->layout.plane_addr[i]); + layout->plane_addr[i]); } else if (pipe->multirect_index == DPU_SSPP_RECT_0) { DPU_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR + idx, - cfg->layout.plane_addr[0]); + layout->plane_addr[0]); DPU_REG_WRITE(&ctx->hw, SSPP_SRC2_ADDR + idx, - cfg->layout.plane_addr[2]); + layout->plane_addr[2]); } else { DPU_REG_WRITE(&ctx->hw, SSPP_SRC1_ADDR + idx, - cfg->layout.plane_addr[0]); + layout->plane_addr[0]); DPU_REG_WRITE(&ctx->hw, SSPP_SRC3_ADDR + idx, - cfg->layout.plane_addr[2]); + layout->plane_addr[2]); } if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) { - ystride0 = (cfg->layout.plane_pitch[0]) | - (cfg->layout.plane_pitch[1] << 16); - ystride1 = (cfg->layout.plane_pitch[2]) | - (cfg->layout.plane_pitch[3] << 16); + ystride0 = (layout->plane_pitch[0]) | + (layout->plane_pitch[1] << 16); + ystride1 = (layout->plane_pitch[2]) | + (layout->plane_pitch[3] << 16); } else { ystride0 = DPU_REG_READ(&ctx->hw, SSPP_SRC_YSTRIDE0 + idx); ystride1 = DPU_REG_READ(&ctx->hw, SSPP_SRC_YSTRIDE1 + idx); if (pipe->multirect_index == DPU_SSPP_RECT_0) { ystride0 = (ystride0 & 0xFFFF0000) | - (cfg->layout.plane_pitch[0] & 0x0000FFFF); + (layout->plane_pitch[0] & 0x0000FFFF); ystride1 = (ystride1 & 0xFFFF0000)| - (cfg->layout.plane_pitch[2] & 0x0000FFFF); + (layout->plane_pitch[2] & 0x0000FFFF); } else { ystride0 = (ystride0 & 0x0000FFFF) | - ((cfg->layout.plane_pitch[0] << 16) & + ((layout->plane_pitch[0] << 16) & 0xFFFF0000); ystride1 = (ystride1 & 0x0000FFFF) | - ((cfg->layout.plane_pitch[2] << 16) & + ((layout->plane_pitch[2] << 16) & 0xFFFF0000); } } @@ -564,7 +564,7 @@ static void dpu_hw_sspp_setup_csc(struct dpu_hw_sspp *ctx, static void dpu_hw_sspp_setup_solidfill(struct dpu_sw_pipe *pipe, u32 color) { struct dpu_hw_sspp *ctx = pipe->sspp; - struct dpu_hw_sspp_cfg cfg; + struct dpu_hw_fmt_layout cfg; u32 idx; if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx)) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h index 136b8713943f..100d8e06c90d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h @@ -154,13 +154,11 @@ struct dpu_hw_pixel_ext { /** * struct dpu_hw_sspp_cfg : SSPP configuration - * @layout: format layout information for programming buffer to hardware * @src_rect: src ROI, caller takes into account the different operations * such as decimation, flip etc to program this field * @dest_rect: destination ROI. */ struct dpu_hw_sspp_cfg { - struct dpu_hw_fmt_layout layout; struct drm_rect src_rect; struct drm_rect dst_rect; }; @@ -243,10 +241,10 @@ struct dpu_hw_sspp_ops { /** * setup_sourceaddress - setup pipe source addresses * @pipe: Pointer to software pipe context - * @cfg: Pointer to pipe config structure + * @layout: format layout information for programming buffer to hardware */ void (*setup_sourceaddress)(struct dpu_sw_pipe *ctx, - struct dpu_hw_sspp_cfg *cfg); + struct dpu_hw_fmt_layout *layout); /** * setup_csc - setup color space coversion diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 8c98385303ea..4ae70d21c37a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -471,21 +471,21 @@ static void _dpu_plane_set_qos_remap(struct drm_plane *plane) static void _dpu_plane_set_scanout(struct drm_plane *plane, struct dpu_plane_state *pstate, - struct dpu_hw_sspp_cfg *pipe_cfg, struct drm_framebuffer *fb) { struct dpu_plane *pdpu = to_dpu_plane(plane); struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); struct msm_gem_address_space *aspace = kms->base.aspace; + struct dpu_hw_fmt_layout layout; int ret; - ret = dpu_format_populate_layout(aspace, fb, &pipe_cfg->layout); + ret = dpu_format_populate_layout(aspace, fb, &layout); if (ret) DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret); else if (pstate->pipe.sspp->ops.setup_sourceaddress) { trace_dpu_plane_set_scanout(&pstate->pipe, - &pipe_cfg->layout); - pstate->pipe.sspp->ops.setup_sourceaddress(&pstate->pipe, pipe_cfg); + &layout); + pstate->pipe.sspp->ops.setup_sourceaddress(&pstate->pipe, &layout); } } @@ -1134,7 +1134,7 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) memset(&pipe_cfg, 0, sizeof(struct dpu_hw_sspp_cfg)); - _dpu_plane_set_scanout(plane, pstate, &pipe_cfg, fb); + _dpu_plane_set_scanout(plane, pstate, fb); pstate->pending = true; From patchwork Tue Mar 14 15:35:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 663037 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D3235C7618A for ; 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Tue, 14 Mar 2023 08:35:56 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Abhinav Kumar Cc: Stephen Boyd , David Airlie , Daniel Vetter , Bjorn Andersson , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH v6 15/32] drm/msm/dpu: don't use unsupported blend stages Date: Tue, 14 Mar 2023 18:35:28 +0300 Message-Id: <20230314153545.3442879-16-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230314153545.3442879-1-dmitry.baryshkov@linaro.org> References: <20230314153545.3442879-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The dpu_crtc_atomic_check() compares blending stage with DPU_STAGE_MAX (maximum amount of blending stages supported by the driver), however we should compare it against .max_mixer_blendstages, the maximum blend stage supported by the mixer. Reviewed-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index ca7a9f58a97f..3ff9c6018a5b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -1154,6 +1154,7 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, crtc); struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc_state); + struct dpu_kms *dpu_kms = _dpu_crtc_get_kms(crtc); const struct drm_plane_state *pstate; struct drm_plane *plane; @@ -1189,7 +1190,7 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, drm_atomic_crtc_state_for_each_plane_state(plane, pstate, crtc_state) { struct dpu_plane_state *dpu_pstate = to_dpu_plane_state(pstate); struct drm_rect dst, clip = crtc_rect; - int z_pos; + int stage; if (IS_ERR_OR_NULL(pstate)) { rc = PTR_ERR(pstate); @@ -1214,17 +1215,16 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, return -E2BIG; } - z_pos = pstate->normalized_zpos; - - /* verify z_pos setting before using it */ - if (z_pos >= DPU_STAGE_MAX - DPU_STAGE_0) { + /* verify stage setting before using it */ + stage = DPU_STAGE_0 + pstate->normalized_zpos; + if (stage >= dpu_kms->catalog->caps->max_mixer_blendstages) { DPU_ERROR("> %d plane stages assigned\n", - DPU_STAGE_MAX - DPU_STAGE_0); + dpu_kms->catalog->caps->max_mixer_blendstages - DPU_STAGE_0); return -EINVAL; } - to_dpu_plane_state(pstate)->stage = z_pos + DPU_STAGE_0; - DRM_DEBUG_ATOMIC("%s: zpos %d\n", dpu_crtc->name, z_pos); + to_dpu_plane_state(pstate)->stage = stage; + DRM_DEBUG_ATOMIC("%s: stage %d\n", dpu_crtc->name, stage); } From patchwork Tue Mar 14 15:35:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 663036 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8EE65C7618D for ; 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Tue, 14 Mar 2023 08:35:57 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Abhinav Kumar Cc: Stephen Boyd , David Airlie , Daniel Vetter , Bjorn Andersson , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH v6 16/32] drm/msm/dpu: move the rest of plane checks to dpu_plane_atomic_check() Date: Tue, 14 Mar 2023 18:35:29 +0300 Message-Id: <20230314153545.3442879-17-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230314153545.3442879-1-dmitry.baryshkov@linaro.org> References: <20230314153545.3442879-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Move plane state updates from dpu_crtc_atomic_check() to the function where they belong: to dpu_plane_atomic_check(). Reviewed-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 18 +----------------- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 18 ++++++++++-------- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 6 ------ 3 files changed, 11 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index 3ff9c6018a5b..37e6e5750bdd 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -1154,7 +1154,6 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, crtc); struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc_state); - struct dpu_kms *dpu_kms = _dpu_crtc_get_kms(crtc); const struct drm_plane_state *pstate; struct drm_plane *plane; @@ -1186,11 +1185,10 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, crtc_rect.x2 = mode->hdisplay; crtc_rect.y2 = mode->vdisplay; - /* get plane state for all drm planes associated with crtc state */ + /* FIXME: move this to dpu_plane_atomic_check? */ drm_atomic_crtc_state_for_each_plane_state(plane, pstate, crtc_state) { struct dpu_plane_state *dpu_pstate = to_dpu_plane_state(pstate); struct drm_rect dst, clip = crtc_rect; - int stage; if (IS_ERR_OR_NULL(pstate)) { rc = PTR_ERR(pstate); @@ -1204,8 +1202,6 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, dpu_pstate->needs_dirtyfb = needs_dirtyfb; - dpu_plane_clear_multirect(pstate); - dst = drm_plane_state_dest(pstate); if (!drm_rect_intersect(&clip, &dst)) { DPU_ERROR("invalid vertical/horizontal destination\n"); @@ -1214,18 +1210,6 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, DRM_RECT_ARG(&dst)); return -E2BIG; } - - /* verify stage setting before using it */ - stage = DPU_STAGE_0 + pstate->normalized_zpos; - if (stage >= dpu_kms->catalog->caps->max_mixer_blendstages) { - DPU_ERROR("> %d plane stages assigned\n", - dpu_kms->catalog->caps->max_mixer_blendstages - DPU_STAGE_0); - return -EINVAL; - } - - to_dpu_plane_state(pstate)->stage = stage; - DRM_DEBUG_ATOMIC("%s: stage %d\n", dpu_crtc->name, stage); - } atomic_inc(&_dpu_crtc_get_kms(crtc)->bandwidth_ref); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index ce01a602cbc9..3fba63fbbd78 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -733,14 +733,6 @@ static int _dpu_plane_color_fill(struct dpu_plane *pdpu, return 0; } -void dpu_plane_clear_multirect(const struct drm_plane_state *drm_state) -{ - struct dpu_plane_state *pstate = to_dpu_plane_state(drm_state); - - pstate->pipe.multirect_index = DPU_SSPP_RECT_SOLO; - pstate->pipe.multirect_mode = DPU_SSPP_MULTIRECT_NONE; -} - int dpu_plane_validate_multirect_v2(struct dpu_multirect_plane_states *plane) { struct dpu_plane_state *pstate[R_MAX]; @@ -994,6 +986,16 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, if (!new_plane_state->visible) return 0; + pstate->pipe.multirect_index = DPU_SSPP_RECT_SOLO; + pstate->pipe.multirect_mode = DPU_SSPP_MULTIRECT_NONE; + + pstate->stage = DPU_STAGE_0 + pstate->base.normalized_zpos; + if (pstate->stage >= pdpu->catalog->caps->max_mixer_blendstages) { + DPU_ERROR("> %d plane stages assigned\n", + pdpu->catalog->caps->max_mixer_blendstages - DPU_STAGE_0); + return -EINVAL; + } + src.x1 = new_plane_state->src_x >> 16; src.y1 = new_plane_state->src_y >> 16; src.x2 = src.x1 + (new_plane_state->src_w >> 16); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h index 228db401e905..a08b0539513b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h @@ -88,12 +88,6 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev, */ int dpu_plane_validate_multirect_v2(struct dpu_multirect_plane_states *plane); -/** - * dpu_plane_clear_multirect - clear multirect bits for the given pipe - * @drm_state: Pointer to DRM plane state - */ -void dpu_plane_clear_multirect(const struct drm_plane_state *drm_state); - /** * dpu_plane_color_fill - enables color fill on plane * @plane: Pointer to DRM plane object From patchwork Tue Mar 14 15:35:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 663035 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3647BC6FD1C for ; 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Tue, 14 Mar 2023 08:35:59 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Abhinav Kumar Cc: Stephen Boyd , David Airlie , Daniel Vetter , Bjorn Andersson , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH v6 19/32] drm/msm/dpu: make _dpu_plane_calc_clk accept mode directly Date: Tue, 14 Mar 2023 18:35:32 +0300 Message-Id: <20230314153545.3442879-20-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230314153545.3442879-1-dmitry.baryshkov@linaro.org> References: <20230314153545.3442879-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Rework bandwidth/clock calculation functions to use mode directly rather than fetching it through the plane data. Reviewed-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 39 ++++++++++------------- 1 file changed, 17 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index aaea7c63d944..6cd787e85be8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -127,20 +127,19 @@ static struct dpu_kms *_dpu_plane_get_kms(struct drm_plane *plane) /** * _dpu_plane_calc_bw - calculate bandwidth required for a plane - * @plane: Pointer to drm plane. + * @catalog: Points to dpu catalog structure * @fmt: Pointer to source buffer format + * @mode: Pointer to drm display mode * @pipe_cfg: Pointer to pipe configuration * Result: Updates calculated bandwidth in the plane state. * BW Equation: src_w * src_h * bpp * fps * (v_total / v_dest) * Prefill BW Equation: line src bytes * line_time */ -static void _dpu_plane_calc_bw(struct drm_plane *plane, +static u64 _dpu_plane_calc_bw(const struct dpu_mdss_cfg *catalog, const struct dpu_format *fmt, + const struct drm_display_mode *mode, struct dpu_sw_pipe_cfg *pipe_cfg) { - struct dpu_plane_state *pstate; - struct drm_display_mode *mode; - struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); int src_width, src_height, dst_height, fps; u64 plane_prefill_bw; u64 plane_bw; @@ -148,9 +147,6 @@ static void _dpu_plane_calc_bw(struct drm_plane *plane, u64 scale_factor; int vbp, vpw, vfp; - pstate = to_dpu_plane_state(plane->state); - mode = &plane->state->crtc->mode; - src_width = drm_rect_width(&pipe_cfg->src_rect); src_height = drm_rect_height(&pipe_cfg->src_rect); dst_height = drm_rect_height(&pipe_cfg->dst_rect); @@ -158,7 +154,7 @@ static void _dpu_plane_calc_bw(struct drm_plane *plane, vbp = mode->vtotal - mode->vsync_end; vpw = mode->vsync_end - mode->vsync_start; vfp = mode->vsync_start - mode->vdisplay; - hw_latency_lines = dpu_kms->catalog->perf->min_prefill_lines; + hw_latency_lines = catalog->perf->min_prefill_lines; scale_factor = src_height > dst_height ? mult_frac(src_height, 1, dst_height) : 1; @@ -178,37 +174,36 @@ static void _dpu_plane_calc_bw(struct drm_plane *plane, do_div(plane_prefill_bw, hw_latency_lines); - pstate->plane_fetch_bw = max(plane_bw, plane_prefill_bw); + return max(plane_bw, plane_prefill_bw); } /** * _dpu_plane_calc_clk - calculate clock required for a plane - * @plane: Pointer to drm plane. + * @mode: Pointer to drm display mode * @pipe_cfg: Pointer to pipe configuration * Result: Updates calculated clock in the plane state. * Clock equation: dst_w * v_total * fps * (src_h / dst_h) */ -static void _dpu_plane_calc_clk(struct drm_plane *plane, struct dpu_sw_pipe_cfg *pipe_cfg) +static u64 _dpu_plane_calc_clk(const struct drm_display_mode *mode, + struct dpu_sw_pipe_cfg *pipe_cfg) { - struct dpu_plane_state *pstate; - struct drm_display_mode *mode; int dst_width, src_height, dst_height, fps; - - pstate = to_dpu_plane_state(plane->state); - mode = &plane->state->crtc->mode; + u64 plane_clk; src_height = drm_rect_height(&pipe_cfg->src_rect); dst_width = drm_rect_width(&pipe_cfg->dst_rect); dst_height = drm_rect_height(&pipe_cfg->dst_rect); fps = drm_mode_vrefresh(mode); - pstate->plane_clk = + plane_clk = dst_width * mode->vtotal * fps; if (src_height > dst_height) { - pstate->plane_clk *= src_height; - do_div(pstate->plane_clk, dst_height); + plane_clk *= src_height; + do_div(plane_clk, dst_height); } + + return plane_clk; } /** @@ -1219,9 +1214,9 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) _dpu_plane_set_qos_remap(plane, pipe); } - _dpu_plane_calc_bw(plane, fmt, &pipe_cfg); + pstate->plane_fetch_bw = _dpu_plane_calc_bw(pdpu->catalog, fmt, &crtc->mode, &pipe_cfg); - _dpu_plane_calc_clk(plane, &pipe_cfg); + pstate->plane_clk = _dpu_plane_calc_clk(&crtc->mode, &pipe_cfg); } static void _dpu_plane_atomic_disable(struct drm_plane *plane) From patchwork Tue Mar 14 15:35:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 663034 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A3ADCC6FD1F for ; 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Tue, 14 Mar 2023 08:36:01 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Abhinav Kumar Cc: Stephen Boyd , David Airlie , Daniel Vetter , Bjorn Andersson , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH v6 21/32] drm/msm/dpu: simplify dpu_plane_validate_src() Date: Tue, 14 Mar 2023 18:35:34 +0300 Message-Id: <20230314153545.3442879-22-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230314153545.3442879-1-dmitry.baryshkov@linaro.org> References: <20230314153545.3442879-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The plane's clipped coordinates has already been validated against FB size in the drm_atomic_plane_check(). There is no need to check them again. Remove corresponding checks and inline dpu_plane_validate_src(). Reviewed-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 30 ++++++++--------------- 1 file changed, 10 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index ba850e9feb9b..9c556ba9cb7b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -894,25 +894,6 @@ static void dpu_plane_cleanup_fb(struct drm_plane *plane, old_pstate->needs_dirtyfb); } -static bool dpu_plane_validate_src(struct drm_rect *src, - struct drm_rect *fb_rect, - uint32_t min_src_size) -{ - /* Ensure fb size is supported */ - if (drm_rect_width(fb_rect) > MAX_IMG_WIDTH || - drm_rect_height(fb_rect) > MAX_IMG_HEIGHT) - return false; - - /* Ensure src rect is above the minimum size */ - if (drm_rect_width(src) < min_src_size || - drm_rect_height(src) < min_src_size) - return false; - - /* Ensure src is fully encapsulated in fb */ - return drm_rect_intersect(fb_rect, src) && - drm_rect_equals(fb_rect, src); -} - static int dpu_plane_check_inline_rotation(struct dpu_plane *pdpu, const struct dpu_sspp_sub_blks *sblk, struct drm_rect src, const struct dpu_format *fmt) @@ -998,6 +979,14 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, fb_rect.x2 = new_plane_state->fb->width; fb_rect.y2 = new_plane_state->fb->height; + /* Ensure fb size is supported */ + if (drm_rect_width(&fb_rect) > MAX_IMG_WIDTH || + drm_rect_height(&fb_rect) > MAX_IMG_HEIGHT) { + DPU_DEBUG_PLANE(pdpu, "invalid framebuffer " DRM_RECT_FMT "\n", + DRM_RECT_ARG(&fb_rect)); + return -E2BIG; + } + max_linewidth = pdpu->catalog->caps->max_linewidth; fmt = to_dpu_format(msm_framebuffer_format(new_plane_state->fb)); @@ -1012,7 +1001,8 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, return -EINVAL; /* check src bounds */ - } else if (!dpu_plane_validate_src(&pipe_cfg->src_rect, &fb_rect, min_src_size)) { + } else if (drm_rect_width(&pipe_cfg->src_rect) < min_src_size || + drm_rect_height(&pipe_cfg->src_rect) < min_src_size) { DPU_DEBUG_PLANE(pdpu, "invalid source " DRM_RECT_FMT "\n", DRM_RECT_ARG(&pipe_cfg->src_rect)); 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Tue, 14 Mar 2023 08:36:01 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Abhinav Kumar Cc: Stephen Boyd , David Airlie , Daniel Vetter , Bjorn Andersson , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH v6 22/32] drm/msm/dpu: rework dpu_plane_sspp_atomic_update() Date: Tue, 14 Mar 2023 18:35:35 +0300 Message-Id: <20230314153545.3442879-23-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230314153545.3442879-1-dmitry.baryshkov@linaro.org> References: <20230314153545.3442879-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Split pipe-dependent code from dpu_plane_sspp_atomic_update() into the separate function dpu_plane_sspp_update_pipe(). This is one of preparational steps to add r_pipe support. Reviewed-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 113 ++++++++++++---------- 1 file changed, 63 insertions(+), 50 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 9c556ba9cb7b..f97ea39423a2 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -404,12 +404,13 @@ static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane, * _dpu_plane_set_ot_limit - set OT limit for the given plane * @plane: Pointer to drm plane * @pipe: Pointer to software pipe - * @crtc: Pointer to drm crtc * @pipe_cfg: Pointer to pipe configuration + * @frame_rate: CRTC's frame rate */ static void _dpu_plane_set_ot_limit(struct drm_plane *plane, struct dpu_sw_pipe *pipe, - struct drm_crtc *crtc, struct dpu_sw_pipe_cfg *pipe_cfg) + struct dpu_sw_pipe_cfg *pipe_cfg, + int frame_rate) { struct dpu_plane *pdpu = to_dpu_plane(plane); struct dpu_vbif_set_ot_params ot_params; @@ -421,7 +422,7 @@ static void _dpu_plane_set_ot_limit(struct drm_plane *plane, ot_params.width = drm_rect_width(&pipe_cfg->src_rect); ot_params.height = drm_rect_height(&pipe_cfg->src_rect); ot_params.is_wfd = !pdpu->is_rt_pipe; - ot_params.frame_rate = drm_mode_vrefresh(&crtc->mode); + ot_params.frame_rate = frame_rate; ot_params.vbif_idx = VBIF_RT; ot_params.clk_ctrl = pipe->sspp->cap->clk_ctrl; ot_params.rd = true; @@ -457,26 +458,6 @@ static void _dpu_plane_set_qos_remap(struct drm_plane *plane, dpu_vbif_set_qos_remap(dpu_kms, &qos_params); } -static void _dpu_plane_set_scanout(struct drm_plane *plane, - struct dpu_plane_state *pstate, - struct drm_framebuffer *fb) -{ - struct dpu_plane *pdpu = to_dpu_plane(plane); - struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); - struct msm_gem_address_space *aspace = kms->base.aspace; - struct dpu_hw_fmt_layout layout; - int ret; - - ret = dpu_format_populate_layout(aspace, fb, &layout); - if (ret) - DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret); - else if (pstate->pipe.sspp->ops.setup_sourceaddress) { - trace_dpu_plane_set_scanout(&pstate->pipe, - &layout); - pstate->pipe.sspp->ops.setup_sourceaddress(&pstate->pipe, &layout); - } -} - static void _dpu_plane_setup_scaler3(struct dpu_hw_sspp *pipe_hw, uint32_t src_w, uint32_t src_h, uint32_t dst_w, uint32_t dst_h, struct dpu_hw_scaler3_cfg *scale_cfg, @@ -1103,35 +1084,25 @@ void dpu_plane_set_error(struct drm_plane *plane, bool error) pdpu->is_error = error; } -static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) +static void dpu_plane_sspp_update_pipe(struct drm_plane *plane, + struct dpu_sw_pipe *pipe, + struct dpu_sw_pipe_cfg *pipe_cfg, + const struct dpu_format *fmt, + int frame_rate, + struct dpu_hw_fmt_layout *layout) { uint32_t src_flags; struct dpu_plane *pdpu = to_dpu_plane(plane); struct drm_plane_state *state = plane->state; struct dpu_plane_state *pstate = to_dpu_plane_state(state); - struct dpu_sw_pipe *pipe = &pstate->pipe; - struct drm_crtc *crtc = state->crtc; - struct drm_framebuffer *fb = state->fb; - bool is_rt_pipe; - const struct dpu_format *fmt = - to_dpu_format(msm_framebuffer_format(fb)); - struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg; - _dpu_plane_set_scanout(plane, pstate, fb); - - pstate->pending = true; - - is_rt_pipe = (dpu_crtc_get_client_type(crtc) != NRT_CLIENT); - pstate->needs_qos_remap |= (is_rt_pipe != pdpu->is_rt_pipe); - pdpu->is_rt_pipe = is_rt_pipe; + if (layout && pipe->sspp->ops.setup_sourceaddress) { + trace_dpu_plane_set_scanout(pipe, layout); + pipe->sspp->ops.setup_sourceaddress(pipe, layout); + } _dpu_plane_set_qos_ctrl(plane, pipe, false, DPU_PLANE_QOS_PANIC_CTRL); - DPU_DEBUG_PLANE(pdpu, "FB[%u] " DRM_RECT_FP_FMT "->crtc%u " DRM_RECT_FMT - ", %4.4s ubwc %d\n", fb->base.id, DRM_RECT_FP_ARG(&state->src), - crtc->base.id, DRM_RECT_ARG(&state->dst), - (char *)&fmt->base.pixel_format, DPU_FORMAT_IS_UBWC(fmt)); - /* override for color fill */ if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG) { /* skip remaining processing on color fill */ @@ -1184,23 +1155,65 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) } } - _dpu_plane_set_qos_lut(plane, pipe, fmt, &pstate->pipe_cfg); + _dpu_plane_set_qos_lut(plane, pipe, fmt, pipe_cfg); _dpu_plane_set_danger_lut(plane, pipe, fmt); if (plane->type != DRM_PLANE_TYPE_CURSOR) { _dpu_plane_set_qos_ctrl(plane, pipe, true, DPU_PLANE_QOS_PANIC_CTRL); - _dpu_plane_set_ot_limit(plane, pipe, crtc, &pstate->pipe_cfg); + _dpu_plane_set_ot_limit(plane, pipe, pipe_cfg, frame_rate); } - if (pstate->needs_qos_remap) { - pstate->needs_qos_remap = false; + if (pstate->needs_qos_remap) _dpu_plane_set_qos_remap(plane, pipe); - } +} + +static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) +{ + struct dpu_plane *pdpu = to_dpu_plane(plane); + struct drm_plane_state *state = plane->state; + struct dpu_plane_state *pstate = to_dpu_plane_state(state); + struct dpu_sw_pipe *pipe = &pstate->pipe; + struct drm_crtc *crtc = state->crtc; + struct drm_framebuffer *fb = state->fb; + bool is_rt_pipe; + const struct dpu_format *fmt = + to_dpu_format(msm_framebuffer_format(fb)); + struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg; + + struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); + struct msm_gem_address_space *aspace = kms->base.aspace; + struct dpu_hw_fmt_layout layout; + bool layout_valid = false; + int ret; + + ret = dpu_format_populate_layout(aspace, fb, &layout); + if (ret) + DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret); + else + layout_valid = true; + + pstate->pending = true; + + is_rt_pipe = (dpu_crtc_get_client_type(crtc) != NRT_CLIENT); + pstate->needs_qos_remap |= (is_rt_pipe != pdpu->is_rt_pipe); + pdpu->is_rt_pipe = is_rt_pipe; + + DPU_DEBUG_PLANE(pdpu, "FB[%u] " DRM_RECT_FP_FMT "->crtc%u " DRM_RECT_FMT + ", %4.4s ubwc %d\n", fb->base.id, DRM_RECT_FP_ARG(&state->src), + crtc->base.id, DRM_RECT_ARG(&state->dst), + (char *)&fmt->base.pixel_format, DPU_FORMAT_IS_UBWC(fmt)); + + dpu_plane_sspp_update_pipe(plane, pipe, pipe_cfg, fmt, + drm_mode_vrefresh(&crtc->mode), + layout_valid ? &layout : NULL); + + if (pstate->needs_qos_remap) + pstate->needs_qos_remap = false; pstate->plane_fetch_bw = _dpu_plane_calc_bw(pdpu->catalog, fmt, - &crtc->mode, &pstate->pipe_cfg); + &crtc->mode, pipe_cfg); - pstate->plane_clk = _dpu_plane_calc_clk(&crtc->mode, &pstate->pipe_cfg); + pstate->plane_clk = _dpu_plane_calc_clk(&crtc->mode, pipe_cfg); } static void _dpu_plane_atomic_disable(struct drm_plane *plane) From patchwork Tue Mar 14 15:35:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 663032 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 45020C7618D for ; Tue, 14 Mar 2023 15:38:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230289AbjCNPiF (ORCPT ); Tue, 14 Mar 2023 11:38:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39118 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229866AbjCNPhj (ORCPT ); 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Tue, 14 Mar 2023 08:36:03 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Abhinav Kumar Cc: Stephen Boyd , David Airlie , Daniel Vetter , Bjorn Andersson , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH v6 25/32] drm/msm/dpu: rework static color fill code Date: Tue, 14 Mar 2023 18:35:38 +0300 Message-Id: <20230314153545.3442879-26-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230314153545.3442879-1-dmitry.baryshkov@linaro.org> References: <20230314153545.3442879-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Rework static color fill code to separate the pipe / pipe_cfg handling. This is a preparation for the r_pipe support. Reviewed-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 69 +++++++++++++---------- 1 file changed, 40 insertions(+), 29 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 6031d270992f..f52120b05b6e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -640,20 +640,52 @@ static void _dpu_plane_setup_scaler(struct dpu_sw_pipe *pipe, fmt); } +static void _dpu_plane_color_fill_pipe(struct dpu_plane_state *pstate, + struct dpu_sw_pipe *pipe, + struct drm_rect *dst_rect, + u32 fill_color, + const struct dpu_format *fmt) +{ + struct dpu_sw_pipe_cfg pipe_cfg; + + /* update sspp */ + if (!pipe->sspp->ops.setup_solidfill) + return; + + pipe->sspp->ops.setup_solidfill(pipe, fill_color); + + /* override scaler/decimation if solid fill */ + pipe_cfg.dst_rect = *dst_rect; + + pipe_cfg.src_rect.x1 = 0; + pipe_cfg.src_rect.y1 = 0; + pipe_cfg.src_rect.x2 = + drm_rect_width(&pipe_cfg.dst_rect); + pipe_cfg.src_rect.y2 = + drm_rect_height(&pipe_cfg.dst_rect); + + if (pipe->sspp->ops.setup_format) + pipe->sspp->ops.setup_format(pipe, fmt, DPU_SSPP_SOLID_FILL); + + if (pipe->sspp->ops.setup_rects) + pipe->sspp->ops.setup_rects(pipe, &pipe_cfg); + + _dpu_plane_setup_scaler(pipe, fmt, true, &pipe_cfg, pstate->rotation); +} + /** * _dpu_plane_color_fill - enables color fill on plane * @pdpu: Pointer to DPU plane object * @color: RGB fill color value, [23..16] Blue, [15..8] Green, [7..0] Red * @alpha: 8-bit fill alpha value, 255 selects 100% alpha - * Returns: 0 on success */ -static int _dpu_plane_color_fill(struct dpu_plane *pdpu, +static void _dpu_plane_color_fill(struct dpu_plane *pdpu, uint32_t color, uint32_t alpha) { const struct dpu_format *fmt; const struct drm_plane *plane = &pdpu->base; struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state); - struct dpu_sw_pipe_cfg pipe_cfg; + u32 fill_color = (color & 0xFFFFFF) | ((alpha & 0xFF) << 24); DPU_DEBUG_PLANE(pdpu, "\n"); @@ -662,34 +694,13 @@ static int _dpu_plane_color_fill(struct dpu_plane *pdpu, * h/w only supports RGB variants */ fmt = dpu_get_dpu_format(DRM_FORMAT_ABGR8888); + /* should not happen ever */ + if (!fmt) + return; /* update sspp */ - if (fmt && pstate->pipe.sspp->ops.setup_solidfill) { - pstate->pipe.sspp->ops.setup_solidfill(&pstate->pipe, - (color & 0xFFFFFF) | ((alpha & 0xFF) << 24)); - - /* override scaler/decimation if solid fill */ - pipe_cfg.dst_rect = pstate->base.dst; - - pipe_cfg.src_rect.x1 = 0; - pipe_cfg.src_rect.y1 = 0; - pipe_cfg.src_rect.x2 = - drm_rect_width(&pipe_cfg.dst_rect); - pipe_cfg.src_rect.y2 = - drm_rect_height(&pipe_cfg.dst_rect); - - if (pstate->pipe.sspp->ops.setup_format) - pstate->pipe.sspp->ops.setup_format(&pstate->pipe, - fmt, DPU_SSPP_SOLID_FILL); - - if (pstate->pipe.sspp->ops.setup_rects) - pstate->pipe.sspp->ops.setup_rects(&pstate->pipe, - &pipe_cfg); - - _dpu_plane_setup_scaler(&pstate->pipe, fmt, true, &pipe_cfg, pstate->rotation); - } - - return 0; + _dpu_plane_color_fill_pipe(pstate, &pstate->pipe, &pstate->pipe_cfg.dst_rect, + fill_color, fmt); } int dpu_plane_validate_multirect_v2(struct dpu_multirect_plane_states *plane) From patchwork Tue Mar 14 15:35:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 663031 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 98CB0C6FD1C for ; Tue, 14 Mar 2023 15:38:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230123AbjCNPiH (ORCPT ); Tue, 14 Mar 2023 11:38:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44434 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230396AbjCNPhn (ORCPT ); Tue, 14 Mar 2023 11:37:43 -0400 Received: from mail-lj1-x22d.google.com (mail-lj1-x22d.google.com [IPv6:2a00:1450:4864:20::22d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2CD6530DF for ; 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This is a preparation for the r_pipe support. Reviewed-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 79 +++++++++++++++--------- 1 file changed, 50 insertions(+), 29 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index 89d2c4735001..217a8112f1a2 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -401,6 +401,46 @@ static void _dpu_crtc_program_lm_output_roi(struct drm_crtc *crtc) } } +static void _dpu_crtc_blend_setup_pipe(struct drm_crtc *crtc, + struct drm_plane *plane, + struct dpu_crtc_mixer *mixer, + u32 num_mixers, + enum dpu_stage stage, + struct dpu_format *format, + uint64_t modifier, + struct dpu_sw_pipe *pipe, + unsigned int stage_idx, + struct dpu_hw_stage_cfg *stage_cfg + ) +{ + uint32_t lm_idx; + enum dpu_sspp sspp_idx; + struct drm_plane_state *state; + + sspp_idx = pipe->sspp->idx; + + state = plane->state; + + trace_dpu_crtc_setup_mixer(DRMID(crtc), DRMID(plane), + state, to_dpu_plane_state(state), stage_idx, + format->base.pixel_format, + modifier); + + DRM_DEBUG_ATOMIC("crtc %d stage:%d - plane %d sspp %d fb %d\n", + crtc->base.id, + stage, + plane->base.id, + sspp_idx - SSPP_NONE, + state->fb ? state->fb->base.id : -1); + + stage_cfg->stage[stage][stage_idx] = sspp_idx; + stage_cfg->multirect_index[stage][stage_idx] = pipe->multirect_index; + + /* blend config update */ + for (lm_idx = 0; lm_idx < num_mixers; lm_idx++) + mixer[lm_idx].lm_ctl->ops.update_pending_flush_sspp(mixer[lm_idx].lm_ctl, sspp_idx); +} + static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc, struct dpu_crtc *dpu_crtc, struct dpu_crtc_mixer *mixer, struct dpu_hw_stage_cfg *stage_cfg) @@ -413,15 +453,12 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc, struct dpu_format *format; struct dpu_hw_ctl *ctl = mixer->lm_ctl; - uint32_t stage_idx, lm_idx; - int zpos_cnt[DPU_STAGE_MAX + 1] = { 0 }; + uint32_t lm_idx; bool bg_alpha_enable = false; DECLARE_BITMAP(fetch_active, SSPP_MAX); memset(fetch_active, 0, sizeof(fetch_active)); drm_atomic_crtc_for_each_plane(plane, crtc) { - enum dpu_sspp sspp_idx; - state = plane->state; if (!state) continue; @@ -432,39 +469,21 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc, pstate = to_dpu_plane_state(state); fb = state->fb; - sspp_idx = pstate->pipe.sspp->idx; - set_bit(sspp_idx, fetch_active); - - DRM_DEBUG_ATOMIC("crtc %d stage:%d - plane %d sspp %d fb %d\n", - crtc->base.id, - pstate->stage, - plane->base.id, - sspp_idx - SSPP_VIG0, - state->fb ? state->fb->base.id : -1); - format = to_dpu_format(msm_framebuffer_format(pstate->base.fb)); if (pstate->stage == DPU_STAGE_BASE && format->alpha_enable) bg_alpha_enable = true; - stage_idx = zpos_cnt[pstate->stage]++; - stage_cfg->stage[pstate->stage][stage_idx] = - sspp_idx; - stage_cfg->multirect_index[pstate->stage][stage_idx] = - pstate->pipe.multirect_index; - - trace_dpu_crtc_setup_mixer(DRMID(crtc), DRMID(plane), - state, pstate, stage_idx, - format->base.pixel_format, - fb ? fb->modifier : 0); + set_bit(pstate->pipe.sspp->idx, fetch_active); + _dpu_crtc_blend_setup_pipe(crtc, plane, + mixer, cstate->num_mixers, + pstate->stage, + format, fb ? fb->modifier : 0, + &pstate->pipe, 0, stage_cfg); /* blend config update */ for (lm_idx = 0; lm_idx < cstate->num_mixers; lm_idx++) { - _dpu_crtc_setup_blend_cfg(mixer + lm_idx, - pstate, format); - - mixer[lm_idx].lm_ctl->ops.update_pending_flush_sspp(mixer[lm_idx].lm_ctl, - sspp_idx); + _dpu_crtc_setup_blend_cfg(mixer + lm_idx, pstate, format); if (bg_alpha_enable && !format->alpha_enable) mixer[lm_idx].mixer_op_mode = 0; @@ -1322,6 +1341,8 @@ static int _dpu_debugfs_status_show(struct seq_file *s, void *data) seq_printf(s, "\tdst x:%4d dst_y:%4d dst_w:%4d dst_h:%4d\n", state->crtc_x, state->crtc_y, state->crtc_w, state->crtc_h); + seq_printf(s, "\tsspp:%s\n", + pstate->pipe.sspp->cap->name); seq_printf(s, "\tmultirect: mode: %d index: %d\n", pstate->pipe.multirect_mode, pstate->pipe.multirect_index); From patchwork Tue Mar 14 15:35:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 663030 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 54322C6FD1C for ; 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Tue, 14 Mar 2023 08:36:05 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Abhinav Kumar Cc: Stephen Boyd , David Airlie , Daniel Vetter , Bjorn Andersson , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH v6 28/32] drm/msm/dpu: populate SmartDMA features in hw catalog Date: Tue, 14 Mar 2023 18:35:41 +0300 Message-Id: <20230314153545.3442879-29-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230314153545.3442879-1-dmitry.baryshkov@linaro.org> References: <20230314153545.3442879-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Downstream driver uses dpu->caps->smart_dma_rev to update sspp->cap->features with the bit corresponding to the supported SmartDMA version. Upstream driver does not do this, resulting in SSPP subdriver not enabling setup_multirect callback. Add corresponding SmartDMA SSPP feature bits to dpu hw catalog. Per Abhinav's request enable the SmartDMA features only on the platforms where the multirect was actually verified visually (sdm845 and sm8250). An (untested) enablement on the rest of the platforms comes in the next patch. Reviewed-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov --- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 44 ++++++++++++------- 1 file changed, 28 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index b39e72a72d58..b762a23313ab 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -27,9 +27,15 @@ #define VIG_SDM845_MASK \ (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3)) +#define VIG_SDM845_MASK_SDMA \ + (VIG_SDM845_MASK | BIT(DPU_SSPP_SMART_DMA_V2)) + #define VIG_SC7180_MASK \ (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED4)) +#define VIG_SC7180_MASK_SDMA \ + (VIG_SC7180_MASK | BIT(DPU_SSPP_SMART_DMA_V2)) + #define VIG_QCM2290_MASK (VIG_BASE_MASK | BIT(DPU_SSPP_QOS_8LVL)) #define DMA_MSM8998_MASK \ @@ -48,6 +54,12 @@ #define DMA_CURSOR_SDM845_MASK \ (DMA_SDM845_MASK | BIT(DPU_SSPP_CURSOR)) +#define DMA_SDM845_MASK_SDMA \ + (DMA_SDM845_MASK | BIT(DPU_SSPP_SMART_DMA_V2)) + +#define DMA_CURSOR_SDM845_MASK_SDMA \ + (DMA_CURSOR_SDM845_MASK | BIT(DPU_SSPP_SMART_DMA_V2)) + #define DMA_CURSOR_MSM8998_MASK \ (DMA_MSM8998_MASK | BIT(DPU_SSPP_CURSOR)) @@ -1197,21 +1209,21 @@ static const struct dpu_sspp_cfg msm8998_sspp[] = { }; static const struct dpu_sspp_cfg sdm845_sspp[] = { - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SDM845_MASK, + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SDM845_MASK_SDMA, sdm845_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), - SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SDM845_MASK, + SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SDM845_MASK_SDMA, sdm845_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1), - SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_SDM845_MASK, + SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_SDM845_MASK_SDMA, sdm845_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2), - SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_SDM845_MASK, + SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_SDM845_MASK_SDMA, sdm845_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3), - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK, + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK_SDMA, sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), - SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK, + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK_SDMA, sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), - SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK, + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK_SDMA, sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), - SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_SDM845_MASK, + SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_SDM845_MASK_SDMA, sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3), }; @@ -1252,21 +1264,21 @@ static const struct dpu_sspp_sub_blks sm8250_vig_sblk_3 = _VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED4); static const struct dpu_sspp_cfg sm8250_sspp[] = { - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7180_MASK, + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7180_MASK_SDMA, sm8250_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), - SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SC7180_MASK, + SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SC7180_MASK_SDMA, sm8250_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1), - SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_SC7180_MASK, + SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_SC7180_MASK_SDMA, sm8250_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2), - SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_SC7180_MASK, + SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_SC7180_MASK_SDMA, sm8250_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3), - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK, + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK_SDMA, sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), - SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK, + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK_SDMA, sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), - SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK, + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK_SDMA, sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), - SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_SDM845_MASK, + SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_SDM845_MASK_SDMA, sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3), }; 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Tue, 14 Mar 2023 08:36:07 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id z8-20020a2eb528000000b0029573844d03sm470854ljm.109.2023.03.14.08.36.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Mar 2023 08:36:07 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Abhinav Kumar Cc: Stephen Boyd , David Airlie , Daniel Vetter , Bjorn Andersson , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH v6 30/32] drm/msm/dpu: drop smart_dma_rev from dpu_caps Date: Tue, 14 Mar 2023 18:35:43 +0300 Message-Id: <20230314153545.3442879-31-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230314153545.3442879-1-dmitry.baryshkov@linaro.org> References: <20230314153545.3442879-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The code doesn't use dpu_caps::smart_dma_rev field. It checks if the corresponding feature is enabled in the SSPP features. Drop the smart_dma_rev field completely. Reviewed-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 13 ------------- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 -- 2 files changed, 15 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index 443a300df92d..50c302d1d17b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -306,7 +306,6 @@ static const struct dpu_caps msm8998_dpu_caps = { .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages = 0x7, .qseed_type = DPU_SSPP_SCALER_QSEED3, - .smart_dma_rev = DPU_SSPP_SMART_DMA_V1, .ubwc_version = DPU_HW_UBWC_VER_10, .has_src_split = true, .has_dim_layer = true, @@ -321,7 +320,6 @@ static const struct dpu_caps msm8998_dpu_caps = { static const struct dpu_caps qcm2290_dpu_caps = { .max_mixer_width = DEFAULT_DPU_LINE_WIDTH, .max_mixer_blendstages = 0x4, - .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, .has_dim_layer = true, .has_idle_pc = true, .max_linewidth = 2160, @@ -332,7 +330,6 @@ static const struct dpu_caps sdm845_dpu_caps = { .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages = 0xb, .qseed_type = DPU_SSPP_SCALER_QSEED3, - .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, .ubwc_version = DPU_HW_UBWC_VER_20, .has_src_split = true, .has_dim_layer = true, @@ -348,7 +345,6 @@ static const struct dpu_caps sc7180_dpu_caps = { .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages = 0x9, .qseed_type = DPU_SSPP_SCALER_QSEED4, - .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, .ubwc_version = DPU_HW_UBWC_VER_20, .has_dim_layer = true, .has_idle_pc = true, @@ -360,7 +356,6 @@ static const struct dpu_caps sm6115_dpu_caps = { .max_mixer_width = DEFAULT_DPU_LINE_WIDTH, .max_mixer_blendstages = 0x4, .qseed_type = DPU_SSPP_SCALER_QSEED4, - .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */ .ubwc_version = DPU_HW_UBWC_VER_10, .has_dim_layer = true, .has_idle_pc = true, @@ -372,7 +367,6 @@ static const struct dpu_caps sm8150_dpu_caps = { .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages = 0xb, .qseed_type = DPU_SSPP_SCALER_QSEED3, - .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */ .ubwc_version = DPU_HW_UBWC_VER_30, .has_src_split = true, .has_dim_layer = true, @@ -388,7 +382,6 @@ static const struct dpu_caps sc8180x_dpu_caps = { .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages = 0xb, .qseed_type = DPU_SSPP_SCALER_QSEED3, - .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */ .ubwc_version = DPU_HW_UBWC_VER_30, .has_src_split = true, .has_dim_layer = true, @@ -404,7 +397,6 @@ static const struct dpu_caps sc8280xp_dpu_caps = { .max_mixer_width = 2560, .max_mixer_blendstages = 11, .qseed_type = DPU_SSPP_SCALER_QSEED4, - .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */ .ubwc_version = DPU_HW_UBWC_VER_40, .has_src_split = true, .has_dim_layer = true, @@ -418,7 +410,6 @@ static const struct dpu_caps sm8250_dpu_caps = { .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages = 0xb, .qseed_type = DPU_SSPP_SCALER_QSEED4, - .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */ .ubwc_version = DPU_HW_UBWC_VER_40, .has_src_split = true, .has_dim_layer = true, @@ -432,7 +423,6 @@ static const struct dpu_caps sm8350_dpu_caps = { .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages = 0xb, .qseed_type = DPU_SSPP_SCALER_QSEED4, - .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */ .ubwc_version = DPU_HW_UBWC_VER_40, .has_src_split = true, .has_dim_layer = true, @@ -446,7 +436,6 @@ static const struct dpu_caps sm8450_dpu_caps = { .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages = 0xb, .qseed_type = DPU_SSPP_SCALER_QSEED4, - .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */ .ubwc_version = DPU_HW_UBWC_VER_40, .has_src_split = true, .has_dim_layer = true, @@ -460,7 +449,6 @@ static const struct dpu_caps sm8550_dpu_caps = { .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages = 0xb, .qseed_type = DPU_SSPP_SCALER_QSEED4, - .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */ .ubwc_version = DPU_HW_UBWC_VER_40, .has_src_split = true, .has_dim_layer = true, @@ -474,7 +462,6 @@ static const struct dpu_caps sc7280_dpu_caps = { .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages = 0x7, .qseed_type = DPU_SSPP_SCALER_QSEED4, - .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, .ubwc_version = DPU_HW_UBWC_VER_30, .has_dim_layer = true, .has_idle_pc = true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index ae85b40e282b..89b372cdca92 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -395,7 +395,6 @@ struct dpu_rotation_cfg { * @max_mixer_blendstages max layer mixer blend stages or * supported z order * @qseed_type qseed2 or qseed3 support. - * @smart_dma_rev Supported version of SmartDMA feature. * @ubwc_version UBWC feature version (0x0 for not supported) * @has_src_split source split feature status * @has_dim_layer dim layer feature status @@ -410,7 +409,6 @@ struct dpu_caps { u32 max_mixer_width; u32 max_mixer_blendstages; u32 qseed_type; - u32 smart_dma_rev; u32 ubwc_version; bool has_src_split; bool has_dim_layer; From patchwork Tue Mar 14 15:35:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 663028 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BD711C6FD1C for ; Tue, 14 Mar 2023 15:38:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231461AbjCNPiR (ORCPT ); Tue, 14 Mar 2023 11:38:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44172 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230365AbjCNPh4 (ORCPT ); Tue, 14 Mar 2023 11:37:56 -0400 Received: from mail-lj1-x22f.google.com (mail-lj1-x22f.google.com [IPv6:2a00:1450:4864:20::22f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 701AEABB0A for ; Tue, 14 Mar 2023 08:37:03 -0700 (PDT) Received: by mail-lj1-x22f.google.com with SMTP id y14so16443667ljq.4 for ; Tue, 14 Mar 2023 08:37:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678808169; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yCPzZ1cychu0OUgOZNR9WWIZNNnjC8fiTwJ8RQSNivs=; b=M1A/D0rqTPJyCssFt0ZFFcuBHdGQmfTIR8c05au1F0o/EKL4eHv/47wxMyh2LWQk0y Mxx70YKbzFEkVkRGoihHbY2/TPUzOwx+H5AljaViphMsXoEg0HwYG9RZtrNzJPq4iS/X k2AaBsOFHMImMNlPQH/ds8ZXWlJDp2EKpWBu3CECWq0G65/T7BkxyEYhMHznIbiyzLmq Pp78Ov7bucB1ol2U9+DTEJCm98v10NCsPJVI+6uHHpyD/cy6LY9ltFOlPZLw+eoBcZGq x9qvjw6AgJ6Rf1occPUnpb4ZVsEYxkxM9V6SgI+ivCNgw8jpe3Bg+WKoWBJJzYBbnqGd QfbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678808169; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yCPzZ1cychu0OUgOZNR9WWIZNNnjC8fiTwJ8RQSNivs=; b=j1Eaj81ZyaAKArGkrIJeWRCRxcMmR4O0RHFMDSeGyZQyWyRLBcNO3IZxxOqqc+XUoW baOnsTEOEkwYtv/4+KP+8DXnP8pi1YwDwUgLlRqs7Z6LEZMhXwhxkbvfJ3ojV9kFFLeE Oq3ys53CLu1wQiSqpwC1V/pmQjShTZ5tGn82lHE5O9PIuVJhTTEA0xvh/Mf9/PEUsh7U FuWvG7ExGt6nPAHpAJ7n5JUJTYRvQXqj8d3Ts3i2WQqrzX6IOacCRaIHBdQdR3RVCzHX Zb11DAzakFx6hxPDOdIOR7xe2mjqfi4/9oMga/WGKLoJI1sv+1txLdkq+Y0lT03yCCE7 iPRg== X-Gm-Message-State: AO0yUKWcqIyxP/wuKL03PjFqqjgVsVt05zt2ZF6Z8eOZapxgVXR10ipE BnkM8bbUaKZLTMu7vW7F1/o09Q== X-Google-Smtp-Source: AK7set+2euD9jIKStIIJvyzs8z0deAMdjOS4IMkSX6MuZJqFhgpFOnp4UpCxBi2L1FEzxxSMbMEJQw== X-Received: by 2002:a2e:ba15:0:b0:295:a2a6:672 with SMTP id p21-20020a2eba15000000b00295a2a60672mr13646309lja.10.1678808169134; Tue, 14 Mar 2023 08:36:09 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id z8-20020a2eb528000000b0029573844d03sm470854ljm.109.2023.03.14.08.36.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Mar 2023 08:36:08 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Abhinav Kumar Cc: Stephen Boyd , David Airlie , Daniel Vetter , Bjorn Andersson , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH v6 32/32] drm/msm/dpu: remove unused dpu_plane_validate_multirect_v2 function Date: Tue, 14 Mar 2023 18:35:45 +0300 Message-Id: <20230314153545.3442879-33-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230314153545.3442879-1-dmitry.baryshkov@linaro.org> References: <20230314153545.3442879-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Abhinav Kumar After cleaning up the older multirect support the function dpu_plane_validate_multirect_v2() is unused. Lets remove it. Signed-off-by: Abhinav Kumar [DB: also drop struct dpu_multirect_plane_states] Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 111 ---------------------- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 17 ---- 2 files changed, 128 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 494c1144075a..177338603ef3 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -707,117 +707,6 @@ static void _dpu_plane_color_fill(struct dpu_plane *pdpu, fill_color, fmt); } -int dpu_plane_validate_multirect_v2(struct dpu_multirect_plane_states *plane) -{ - struct dpu_plane_state *pstate[R_MAX]; - const struct drm_plane_state *drm_state[R_MAX]; - struct drm_rect src[R_MAX], dst[R_MAX]; - struct dpu_plane *dpu_plane[R_MAX]; - const struct dpu_format *fmt[R_MAX]; - int i, buffer_lines; - unsigned int max_tile_height = 1; - bool parallel_fetch_qualified = true; - bool has_tiled_rect = false; - - for (i = 0; i < R_MAX; i++) { - const struct msm_format *msm_fmt; - - drm_state[i] = i ? plane->r1 : plane->r0; - msm_fmt = msm_framebuffer_format(drm_state[i]->fb); - fmt[i] = to_dpu_format(msm_fmt); - - if (DPU_FORMAT_IS_UBWC(fmt[i])) { - has_tiled_rect = true; - if (fmt[i]->tile_height > max_tile_height) - max_tile_height = fmt[i]->tile_height; - } - } - - for (i = 0; i < R_MAX; i++) { - int width_threshold; - - pstate[i] = to_dpu_plane_state(drm_state[i]); - dpu_plane[i] = to_dpu_plane(drm_state[i]->plane); - - if (pstate[i] == NULL) { - DPU_ERROR("DPU plane state of plane id %d is NULL\n", - drm_state[i]->plane->base.id); - return -EINVAL; - } - - src[i].x1 = drm_state[i]->src_x >> 16; - src[i].y1 = drm_state[i]->src_y >> 16; - src[i].x2 = src[i].x1 + (drm_state[i]->src_w >> 16); - src[i].y2 = src[i].y1 + (drm_state[i]->src_h >> 16); - - dst[i] = drm_plane_state_dest(drm_state[i]); - - if (drm_rect_calc_hscale(&src[i], &dst[i], 1, 1) != 1 || - drm_rect_calc_vscale(&src[i], &dst[i], 1, 1) != 1) { - DPU_ERROR_PLANE(dpu_plane[i], - "scaling is not supported in multirect mode\n"); - return -EINVAL; - } - - if (DPU_FORMAT_IS_YUV(fmt[i])) { - DPU_ERROR_PLANE(dpu_plane[i], - "Unsupported format for multirect mode\n"); - return -EINVAL; - } - - /** - * SSPP PD_MEM is split half - one for each RECT. - * Tiled formats need 5 lines of buffering while fetching - * whereas linear formats need only 2 lines. - * So we cannot support more than half of the supported SSPP - * width for tiled formats. - */ - width_threshold = dpu_plane[i]->catalog->caps->max_linewidth; - if (has_tiled_rect) - width_threshold /= 2; - - if (parallel_fetch_qualified && - drm_rect_width(&src[i]) > width_threshold) - parallel_fetch_qualified = false; - - } - - /* Validate RECT's and set the mode */ - - /* Prefer PARALLEL FETCH Mode over TIME_MX Mode */ - if (parallel_fetch_qualified) { - pstate[R0]->pipe.multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL; - pstate[R1]->pipe.multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL; - - goto done; - } - - /* TIME_MX Mode */ - buffer_lines = 2 * max_tile_height; - - if (dst[R1].y1 >= dst[R0].y2 + buffer_lines || - dst[R0].y1 >= dst[R1].y2 + buffer_lines) { - pstate[R0]->pipe.multirect_mode = DPU_SSPP_MULTIRECT_TIME_MX; - pstate[R1]->pipe.multirect_mode = DPU_SSPP_MULTIRECT_TIME_MX; - } else { - DPU_ERROR( - "No multirect mode possible for the planes (%d - %d)\n", - drm_state[R0]->plane->base.id, - drm_state[R1]->plane->base.id); - return -EINVAL; - } - -done: - pstate[R0]->pipe.multirect_index = DPU_SSPP_RECT_0; - pstate[R1]->pipe.multirect_index = DPU_SSPP_RECT_1; - - DPU_DEBUG_PLANE(dpu_plane[R0], "R0: %d - %d\n", - pstate[R0]->pipe.multirect_mode, pstate[R0]->pipe.multirect_index); - DPU_DEBUG_PLANE(dpu_plane[R1], "R1: %d - %d\n", - pstate[R1]->pipe.multirect_mode, pstate[R1]->pipe.multirect_index); - return 0; -} - static int dpu_plane_prepare_fb(struct drm_plane *plane, struct drm_plane_state *new_state) { diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h index 7490ffd94d03..abd6b21a049b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h @@ -50,16 +50,6 @@ struct dpu_plane_state { unsigned int rotation; }; -/** - * struct dpu_multirect_plane_states: Defines multirect pair of drm plane states - * @r0: drm plane configured on rect 0 - * @r1: drm plane configured on rect 1 - */ -struct dpu_multirect_plane_states { - const struct drm_plane_state *r0; - const struct drm_plane_state *r1; -}; - #define to_dpu_plane_state(x) \ container_of(x, struct dpu_plane_state, base) @@ -87,13 +77,6 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev, uint32_t pipe, enum drm_plane_type type, unsigned long possible_crtcs); -/** - * dpu_plane_validate_multirecti_v2 - validate the multirect planes - * against hw limitations - * @plane: drm plate states of the multirect pair - */ -int dpu_plane_validate_multirect_v2(struct dpu_multirect_plane_states *plane); - /** * dpu_plane_color_fill - enables color fill on plane * @plane: Pointer to DRM plane object