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[46.138.144.249]) by smtp.gmail.com with ESMTPSA id z6-20020a2e7e06000000b002946f95b359sm312840ljc.105.2023.03.11.05.24.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 11 Mar 2023 05:24:17 -0800 (PST) Message-ID: <640c8101.2e0a0220.aa0c5.0bd4@mx.google.com> From: Sergey Lisov Date: Sat, 11 Mar 2023 15:54:22 +0300 Subject: [PATCH 1/2] devicetree: synopsys-dw-mshc-common: add "fifo-access-32bit" property To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Jaehoon Chung Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org --- .../devicetree/bindings/mmc/synopsys-dw-mshc-common.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc-common.yaml b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc-common.yaml index 8dfad89c7..2bc5ac528 100644 --- a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc-common.yaml +++ b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc-common.yaml @@ -57,6 +57,12 @@ properties: force fifo watermark setting accordingly. $ref: /schemas/types.yaml#/definitions/flag + fifo-access-32bit: + description: + Specifies that this device requires accesses to its 64-bit registers + to be done as pairs of 32-bit accesses, even on architectures where + readq is available. + dmas: maxItems: 1 From patchwork Sat Mar 11 12:54:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergey Lisov X-Patchwork-Id: 662615 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0D32EC61DA4 for ; Sat, 11 Mar 2023 13:24:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229666AbjCKNYw (ORCPT ); Sat, 11 Mar 2023 08:24:52 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39504 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229934AbjCKNYv (ORCPT ); Sat, 11 Mar 2023 08:24:51 -0500 Received: from mail-lf1-x132.google.com (mail-lf1-x132.google.com [IPv6:2a00:1450:4864:20::132]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0A74710EAA2 for ; Sat, 11 Mar 2023 05:24:50 -0800 (PST) Received: by mail-lf1-x132.google.com with SMTP id t11so10192582lfr.1 for ; Sat, 11 Mar 2023 05:24:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1678541088; h=cc:to:subject:date:from:message-id:from:to:cc:subject:date :message-id:reply-to; bh=F7N4XcDM0EGKh1CMHgzJCQlyNXmM/HdEL/4Dosq+GKE=; b=H06s4en1uv1UC0ReJdT3uJEDSblPMZdAYc3SoWyHDDGKzhwa9NAijVM5pe080/A0C9 8KwpjShDTo30F9g15VBO53a8v/DJQhvValw8XndrJo2Ev+MN0r0aSXcpzihJLdTErCIb HDu6HSxC5iN0tva6l6ygKu1gmShDeG2iqXiPynvBYQTjnpL1v8UKHZpMTJp1v9Puowsf 6xEQdPpisFMqvj5s4/slnZRPEgBNp6xPZZI8O4XioIh3thHIHpT+BMH8l9CE3qxGcvxf ku8p+78REsH95F9AW+HjtJySVXL58mUXR5iZhk2zoY5kV0pZnBRxGSy/pwivOnbPqmxI 5jBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678541088; h=cc:to:subject:date:from:message-id:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=F7N4XcDM0EGKh1CMHgzJCQlyNXmM/HdEL/4Dosq+GKE=; b=DmEMmPKzMTUHV5gdlVAAVpJ2BINbzdRmzwX7O+jPU8fNKviODITiUiNqfzBq8OOWEA xbrf2aHKIvieon3kdccK5GGMBxRXLsRP46V+mom92BlXiuqzh1rOhrGRXDYyGnCnAdhn sAg75aJKRmOhEia6rW6arRuoKburXvR2hkkfLeTo+tGEvkQ6QTpjS3k0Ng3yUkzrKPSh r2qHcMUk3mJ2qMaa5Qp75CFgoqXgN8af0w6ihu7ECe95MdYOk8K4nrSiAUFJBysTCDbs Dj6Oz9i57N8d2HfpyPnwlXBL/gH65IDADK9WIYuA7H9fbr0ogWVC+/10H0wn9HgKDLex V5lw== X-Gm-Message-State: AO0yUKXoyCAwkDxw+q038r3k0ICwJI/qh7mPGXzRHeHy0G4TXYMT1gID Wj2vqIpMWQOaAFOozzGk7MGCFd47peAZRr6Gcok= X-Google-Smtp-Source: AK7set/xdXrteBR61s8Br4R7oSHmaQ2VQXKQp3rvctJJH8F+GqeH1LypPQhJjsQgCgb52/QxyLe7Kw== X-Received: by 2002:ac2:51cd:0:b0:4dd:a61c:8f71 with SMTP id u13-20020ac251cd000000b004dda61c8f71mr8554559lfm.41.1678541087984; Sat, 11 Mar 2023 05:24:47 -0800 (PST) Received: from 0002-dw_mmc-add-an-option-to-force-32-bit-accesses-to-64-.patch (46-138-144-249.dynamic.spd-mgts.ru. [46.138.144.249]) by smtp.gmail.com with ESMTPSA id m4-20020ac24244000000b004d61af6771dsm318744lfl.41.2023.03.11.05.24.47 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 11 Mar 2023 05:24:47 -0800 (PST) Message-ID: <640c811f.c20a0220.6bf04.0bdb@mx.google.com> From: Sergey Lisov Date: Sat, 11 Mar 2023 15:54:50 +0300 Subject: [PATCH 2/2] dw_mmc: add an option to force 32-bit accesses to 64-bit device registers To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Jaehoon Chung Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org --- drivers/mmc/host/dw_mmc.c | 125 +++++++++++++++++++++++++++++++++++++- drivers/mmc/host/dw_mmc.h | 2 + 2 files changed, 125 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c index 581614196..eee430620 100644 --- a/drivers/mmc/host/dw_mmc.c +++ b/drivers/mmc/host/dw_mmc.c @@ -2575,6 +2575,119 @@ static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt) } } +/* + Some dw_mmc devices have 64-bit FIFOs, but expect them to be + accessed using two 32-bit accesses. If such controller is used + with a 64-bit kernel, this has to be done explicitly. + + XXX: Is this issue specific to Exynos7? +*/ + +static inline uint64_t mci_fifo_readq_32(void __iomem *addr) +{ + uint64_t ans; + uint32_t proxy[2]; + + proxy[0] = mci_fifo_readl(addr); + proxy[1] = mci_fifo_readl(addr+4); + memcpy(&ans, proxy, 8); + return ans; +} + +static inline void mci_fifo_writeq_32(void __iomem *addr, uint64_t value) +{ + uint32_t proxy[2]; + + memcpy(proxy, &value, 8); + mci_fifo_writel(addr, proxy[0]); + mci_fifo_writel(addr+4, proxy[1]); +} + +static void dw_mci_push_data64_32(struct dw_mci *host, void *buf, int cnt) +{ + struct mmc_data *data = host->data; + int init_cnt = cnt; + + /* try and push anything in the part_buf */ + if (unlikely(host->part_buf_count)) { + int len = dw_mci_push_part_bytes(host, buf, cnt); + + buf += len; + cnt -= len; + + if (host->part_buf_count == 8) { + mci_fifo_writeq_32(host->fifo_reg, host->part_buf); + host->part_buf_count = 0; + } + } +#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS + if (unlikely((unsigned long)buf & 0x7)) { + while (cnt >= 8) { + u64 aligned_buf[16]; + int len = min(cnt & -8, (int)sizeof(aligned_buf)); + int items = len >> 3; + int i; + /* memcpy from input buffer into aligned buffer */ + memcpy(aligned_buf, buf, len); + buf += len; + cnt -= len; + /* push data from aligned buffer into fifo */ + for (i = 0; i < items; ++i) + mci_fifo_writeq_32(host->fifo_reg, aligned_buf[i]); + } + } else +#endif + { + u64 *pdata = buf; + + for (; cnt >= 8; cnt -= 8) + mci_fifo_writeq_32(host->fifo_reg, *pdata++); + buf = pdata; + } + /* put anything remaining in the part_buf */ + if (cnt) { + dw_mci_set_part_bytes(host, buf, cnt); + /* Push data if we have reached the expected data length */ + if ((data->bytes_xfered + init_cnt) == + (data->blksz * data->blocks)) + mci_fifo_writeq_32(host->fifo_reg, host->part_buf); + } +} + +static void dw_mci_pull_data64_32(struct dw_mci *host, void *buf, int cnt) +{ +#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS + if (unlikely((unsigned long)buf & 0x7)) { + while (cnt >= 8) { + /* pull data from fifo into aligned buffer */ + u64 aligned_buf[16]; + int len = min(cnt & -8, (int)sizeof(aligned_buf)); + int items = len >> 3; + int i; + + for (i = 0; i < items; ++i) + aligned_buf[i] = mci_fifo_readq_32(host->fifo_reg); + + /* memcpy from aligned buffer into output buffer */ + memcpy(buf, aligned_buf, len); + buf += len; + cnt -= len; + } + } else +#endif + { + u64 *pdata = buf; + + for (; cnt >= 8; cnt -= 8) + *pdata++ = mci_fifo_readq_32(host->fifo_reg); + buf = pdata; + } + if (cnt) { + host->part_buf = mci_fifo_readq_32(host->fifo_reg); + dw_mci_pull_final_bytes(host, buf, cnt); + } +} + static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt) { int len; @@ -3239,6 +3352,9 @@ static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host) if (device_property_present(dev, "fifo-watermark-aligned")) host->wm_aligned = true; + if (device_property_present(dev, "fifo-access-32bit")) + host->quirks |= DW_MMC_QUIRK_FIFO64_32; + if (!device_property_read_u32(dev, "clock-frequency", &clock_frequency)) pdata->bus_hz = clock_frequency; @@ -3367,8 +3483,13 @@ int dw_mci_probe(struct dw_mci *host) width = 16; host->data_shift = 1; } else if (i == 2) { - host->push_data = dw_mci_push_data64; - host->pull_data = dw_mci_pull_data64; + if ((host->quirks & DW_MMC_QUIRK_FIFO64_32)) { + host->push_data = dw_mci_push_data64_32; + host->pull_data = dw_mci_pull_data64_32; + } else { + host->push_data = dw_mci_push_data64; + host->pull_data = dw_mci_pull_data64; + } width = 64; host->data_shift = 3; } else { diff --git a/drivers/mmc/host/dw_mmc.h b/drivers/mmc/host/dw_mmc.h index 4ed81f94f..edd642b92 100644 --- a/drivers/mmc/host/dw_mmc.h +++ b/drivers/mmc/host/dw_mmc.h @@ -280,6 +280,8 @@ struct dw_mci_board { /* Support for longer data read timeout */ #define DW_MMC_QUIRK_EXTENDED_TMOUT BIT(0) +/* Force 32-bit access to the FIFO */ +#define DW_MMC_QUIRK_FIFO64_32 BIT(1) #define DW_MMC_240A 0x240a #define DW_MMC_280A 0x280a