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[46.138.144.249]) by smtp.gmail.com with ESMTPSA id r15-20020ac25a4f000000b004db50b52c08sm387004lfn.102.2023.03.11.10.21.39 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 11 Mar 2023 10:21:40 -0800 (PST) Message-Id: <1678558770.495747-1-sleirsgoevy@gmail.com> In-Reply-To: <1678558770.495747-0-sleirsgoevy@gmail.com> From: Sergey Lisov Date: Sat, 11 Mar 2023 21:15:37 +0300 Subject: [PATCH v2 1/2] dt-bindings: synopsys-dw-mshc-common: add "fifo-access-32bit" property To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Jaehoon Chung Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Some Samsung Exynos boards using the arm64 architecture have DW MMC controllers configured for a 32-bit data bus but a 64-bit FIFO. On these systems the 64-bit FIFO registers must be accessed in two 32-bit halves. --- .../devicetree/bindings/mmc/synopsys-dw-mshc-common.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc-common.yaml b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc-common.yaml index 8dfad89c7..d025b38ca 100644 --- a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc-common.yaml +++ b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc-common.yaml @@ -57,6 +57,13 @@ properties: force fifo watermark setting accordingly. $ref: /schemas/types.yaml#/definitions/flag + fifo-access-32bit: + description: + Specifies that this device requires accesses to its 64-bit registers + to be done as pairs of 32-bit accesses, even on architectures where + readq is available. + $ref: /schemas/types.yaml#/definitions/flag + dmas: maxItems: 1 From patchwork Sat Mar 11 18:15:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergey Lisov X-Patchwork-Id: 662305 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 81C8DC6FD1C for ; Sat, 11 Mar 2023 18:22:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230027AbjCKSWq (ORCPT ); Sat, 11 Mar 2023 13:22:46 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36930 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230423AbjCKSWl (ORCPT ); Sat, 11 Mar 2023 13:22:41 -0500 Received: from mail-lf1-x129.google.com (mail-lf1-x129.google.com [IPv6:2a00:1450:4864:20::129]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4B0346BDF5 for ; Sat, 11 Mar 2023 10:22:13 -0800 (PST) Received: by mail-lf1-x129.google.com with SMTP id r27so10730291lfe.10 for ; Sat, 11 Mar 2023 10:22:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1678558928; h=cc:to:subject:date:from:in-reply-to:message-id:from:to:cc:subject :date:message-id:reply-to; bh=JmnRhaQGnYcC7TxoQ5v3x/8cn+va4CZCsQk0t4OobFo=; b=oYathJhNZIHCYkPtihBWPDSjig3180Pv564YDfbtWc76wE/h0V1wrOZbj2lQ5bDFLs DiKmh7lC2y33OubBCiuw0foyJXvjtYXFldemRWYyO2cNWvMvI3AQwRXmmXSYnvFyoSmM JWs0kk6jvZtRCCf8ZlyyjGPiDBxwrCxVJe+cncJONu385bA9HbkXfCOmZBLmK4kKwLfF vkEsANiJtTpHqeNeKga6o3DqbNt4dEFbPiosN46dS+mia406mANm+3idSR92UuGjwsCW rR3nNr9+6FpRV7SU3WYynaiIpvXfmuRbdKmDffuhUbvkIyrwyGaNIxlNvFMwJWlGClsR /YDQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678558928; h=cc:to:subject:date:from:in-reply-to:message-id:x-gm-message-state :from:to:cc:subject:date:message-id:reply-to; bh=JmnRhaQGnYcC7TxoQ5v3x/8cn+va4CZCsQk0t4OobFo=; b=HY1D8dX6nsNdHCFyWoeFctRE/xbgUNOnr+cZY5TvDtrMpojgngaxG+57lIiyxD1B+F YmrOw3ojT97VR1pjEJX8TeCFsyszZMMwjG3HNnvb7ycwRFRQb6nru+Fy06n5ck0BxcOp 5SNzeJMgNx8zuPiOgboayMfyClrX2yscbPp2ogWeQb3Kh6Qyr4xsS5qbpI+PShhtjrus jB543TkMq5XBXYxTLuCPvjjDF5kSKGAZS1BgrkmNqNZtzBEJwbuRAgE5krxqqEckrm2/ vVy+yxCff3GAcm9a91QYi+CXnYsqTD0DFAl9Izo/004nr8rrox2AnX7wSNnF4gYfSiki P9gg== X-Gm-Message-State: AO0yUKWoQJuq3EomnNJkaB+FwPNgVSXNx5czQwxD+2idquqbF0+fmhdy ckDb7QnncOnRADUleAVuIldGdlRZuPLVhRc0IWk= X-Google-Smtp-Source: AK7set/6hEWYVK3awh37ovIBb1xMbx7qROe4IO68xmYLmw2sEiC8lBN3Vhdgnb2J2hEffLlxWsPKqg== X-Received: by 2002:a05:6512:4d9:b0:4db:3e7e:51dc with SMTP id w25-20020a05651204d900b004db3e7e51dcmr8965336lfq.55.1678558928435; Sat, 11 Mar 2023 10:22:08 -0800 (PST) Received: from 0002-mmc-dw_mmc-add-an-option-to-force-32-bit-access-to-6.patch (46-138-144-249.dynamic.spd-mgts.ru. [46.138.144.249]) by smtp.gmail.com with ESMTPSA id s4-20020a19ad44000000b004d863fa8681sm390307lfd.173.2023.03.11.10.22.07 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 11 Mar 2023 10:22:08 -0800 (PST) Message-Id: <1678558770.495747-2-sleirsgoevy@gmail.com> In-Reply-To: <1678558770.495747-0-sleirsgoevy@gmail.com> From: Sergey Lisov Date: Sat, 11 Mar 2023 21:15:38 +0300 Subject: [PATCH v2 2/2] mmc: dw_mmc: add an option to force 32-bit access to 64-bit FIFO To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Jaehoon Chung Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Some Samsung Exynos boards using the arm64 architecture have DW MMC controllers configured for a 32-bit data bus but a 64-bit FIFO. On these systems the 64-bit FIFO registers must be accessed in two 32-bit halves. --- drivers/mmc/host/dw_mmc.c | 125 +++++++++++++++++++++++++++++++++++++- drivers/mmc/host/dw_mmc.h | 2 + 2 files changed, 125 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c index 581614196..eee430620 100644 --- a/drivers/mmc/host/dw_mmc.c +++ b/drivers/mmc/host/dw_mmc.c @@ -2575,6 +2575,119 @@ static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt) } } +/* + Some dw_mmc devices have 64-bit FIFOs, but expect them to be + accessed using two 32-bit accesses. If such controller is used + with a 64-bit kernel, this has to be done explicitly. + + XXX: Is this issue specific to Exynos7? +*/ + +static inline uint64_t mci_fifo_readq_32(void __iomem *addr) +{ + uint64_t ans; + uint32_t proxy[2]; + + proxy[0] = mci_fifo_readl(addr); + proxy[1] = mci_fifo_readl(addr+4); + memcpy(&ans, proxy, 8); + return ans; +} + +static inline void mci_fifo_writeq_32(void __iomem *addr, uint64_t value) +{ + uint32_t proxy[2]; + + memcpy(proxy, &value, 8); + mci_fifo_writel(addr, proxy[0]); + mci_fifo_writel(addr+4, proxy[1]); +} + +static void dw_mci_push_data64_32(struct dw_mci *host, void *buf, int cnt) +{ + struct mmc_data *data = host->data; + int init_cnt = cnt; + + /* try and push anything in the part_buf */ + if (unlikely(host->part_buf_count)) { + int len = dw_mci_push_part_bytes(host, buf, cnt); + + buf += len; + cnt -= len; + + if (host->part_buf_count == 8) { + mci_fifo_writeq_32(host->fifo_reg, host->part_buf); + host->part_buf_count = 0; + } + } +#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS + if (unlikely((unsigned long)buf & 0x7)) { + while (cnt >= 8) { + u64 aligned_buf[16]; + int len = min(cnt & -8, (int)sizeof(aligned_buf)); + int items = len >> 3; + int i; + /* memcpy from input buffer into aligned buffer */ + memcpy(aligned_buf, buf, len); + buf += len; + cnt -= len; + /* push data from aligned buffer into fifo */ + for (i = 0; i < items; ++i) + mci_fifo_writeq_32(host->fifo_reg, aligned_buf[i]); + } + } else +#endif + { + u64 *pdata = buf; + + for (; cnt >= 8; cnt -= 8) + mci_fifo_writeq_32(host->fifo_reg, *pdata++); + buf = pdata; + } + /* put anything remaining in the part_buf */ + if (cnt) { + dw_mci_set_part_bytes(host, buf, cnt); + /* Push data if we have reached the expected data length */ + if ((data->bytes_xfered + init_cnt) == + (data->blksz * data->blocks)) + mci_fifo_writeq_32(host->fifo_reg, host->part_buf); + } +} + +static void dw_mci_pull_data64_32(struct dw_mci *host, void *buf, int cnt) +{ +#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS + if (unlikely((unsigned long)buf & 0x7)) { + while (cnt >= 8) { + /* pull data from fifo into aligned buffer */ + u64 aligned_buf[16]; + int len = min(cnt & -8, (int)sizeof(aligned_buf)); + int items = len >> 3; + int i; + + for (i = 0; i < items; ++i) + aligned_buf[i] = mci_fifo_readq_32(host->fifo_reg); + + /* memcpy from aligned buffer into output buffer */ + memcpy(buf, aligned_buf, len); + buf += len; + cnt -= len; + } + } else +#endif + { + u64 *pdata = buf; + + for (; cnt >= 8; cnt -= 8) + *pdata++ = mci_fifo_readq_32(host->fifo_reg); + buf = pdata; + } + if (cnt) { + host->part_buf = mci_fifo_readq_32(host->fifo_reg); + dw_mci_pull_final_bytes(host, buf, cnt); + } +} + static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt) { int len; @@ -3239,6 +3352,9 @@ static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host) if (device_property_present(dev, "fifo-watermark-aligned")) host->wm_aligned = true; + if (device_property_present(dev, "fifo-access-32bit")) + host->quirks |= DW_MMC_QUIRK_FIFO64_32; + if (!device_property_read_u32(dev, "clock-frequency", &clock_frequency)) pdata->bus_hz = clock_frequency; @@ -3367,8 +3483,13 @@ int dw_mci_probe(struct dw_mci *host) width = 16; host->data_shift = 1; } else if (i == 2) { - host->push_data = dw_mci_push_data64; - host->pull_data = dw_mci_pull_data64; + if ((host->quirks & DW_MMC_QUIRK_FIFO64_32)) { + host->push_data = dw_mci_push_data64_32; + host->pull_data = dw_mci_pull_data64_32; + } else { + host->push_data = dw_mci_push_data64; + host->pull_data = dw_mci_pull_data64; + } width = 64; host->data_shift = 3; } else { diff --git a/drivers/mmc/host/dw_mmc.h b/drivers/mmc/host/dw_mmc.h index 4ed81f94f..edd642b92 100644 --- a/drivers/mmc/host/dw_mmc.h +++ b/drivers/mmc/host/dw_mmc.h @@ -280,6 +280,8 @@ struct dw_mci_board { /* Support for longer data read timeout */ #define DW_MMC_QUIRK_EXTENDED_TMOUT BIT(0) +/* Force 32-bit access to the FIFO */ +#define DW_MMC_QUIRK_FIFO64_32 BIT(1) #define DW_MMC_240A 0x240a #define DW_MMC_280A 0x280a