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Signed-off-by: Dipen Patel Acked-by: Thierry Reding --- MAINTAINERS | 3 +++ 1 file changed, 3 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 8d5bc223f305..65b58963f0d2 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -9425,6 +9425,9 @@ F: drivers/input/touchscreen/htcpen.c HTE SUBSYSTEM M: Dipen Patel +L: timestamp@lists.linux.dev +T: git git://git.kernel.org/pub/scm/linux/kernel/git/pateldipen1984/linux.git +Q: https://patchwork.kernel.org/project/timestamp/list/ S: Maintained F: Documentation/devicetree/bindings/timestamp/ F: Documentation/driver-api/hte/ From patchwork Fri Mar 10 19:06:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dipen Patel X-Patchwork-Id: 661905 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 168D1C76186 for ; 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Fri, 10 Mar 2023 11:06:38 -0800 From: Dipen Patel To: , , , , , , , , , , , , , CC: Dipen Patel Subject: [PATCH V3 2/6] dt-bindings: timestamp: Add Tegra234 support Date: Fri, 10 Mar 2023 11:06:30 -0800 Message-ID: <20230310190634.5053-3-dipenp@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230310190634.5053-1-dipenp@nvidia.com> References: <20230310190634.5053-1-dipenp@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT101:EE_|PH7PR12MB7234:EE_ X-MS-Office365-Filtering-Correlation-Id: 4a2a12d1-aa95-474c-c35d-08db219a9859 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 0LuXL6QZkZGpOchzl9frMhvOSPAUEpkbe2b10/xKEzJazqDh54TNklpqBXf2soHHt1uDobqATwahPgy3rbPBzbIRLKlagC5tsjDk7MQCRtGf7Rd1m1Vd1ZIbWa0duF2HUiHR5Y64u6fEqDLHDqWXB82eaSfjbOIlyZPL/mUMtf7WD2UL/tLXIfs1z6MdHcLh/pzgsS5FYqfHw543SbpeSHI9lxwYYumqCAh2OrIpyrqP3I1VApxtdpZfW5AV6Qqn1VLI8dLrJwb0DVr1cDYr0jt22Lg0zLprdxksMQW2JQPO1VOgLPTrtZjZ8yWpG8peznwhNub/gb8X3bCtwjffZD9iWISJHfVd0i2ko/MbIXQs33K4GPNFjNa6HnUNN3YR0XBa2Iy8xpIJgo618Utwylgi1WGm41E2zWgm/Vlp9z8q00RzjW8UvlcbFwYsUZ9mO9OKXt3Mvs1cG1aGmEz5exLxuBIgrcRTR5PZU1OHEeSv+buZ5I+Ih5yThavEftzy6kEvia6kR7ZcsxOsRtneGpTpXEauMKLl7lSRtkcoTUtzXnXr5z4MyLAgnIrBoPc6Qu0GLapyTs8kaAvJisHkWQC9FSYQc7nvvHVbvgxutX7TrQ2rSuvHmzZDjJNzx6DXkmQOqYJkRZ9W7PC0pRGAhsI8Z71gxka3jbwnXK9lpf//XoDgQu9iBMkgvHSyi4dWUJyMMQbQAFDGWzcpps1KuOQ9PYUgF9ink2xWoXOgWhCiIM85q7/25nfxe/1G4DuKY682Otxz04cHwV3ryUOVdDi1IkiNenF2KJSkBScioQpJREqyD17IXrTVIJ3veiy4ZKf8pHkWmF+EaxHcqW/kpB/GFFGa+Gmp2yvjqhrR6A637gfUh0NLu3tejdrFzSRCs945V0GeU5tPd62p/PliZA== X-Forefront-Antispam-Report: CIP:216.228.117.160; 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In addition, it addresses review comments from the previous review round as follows: - Removes nvidia,slices property. This was not necessary as it is a constant value and can be hardcoded inside the driver code. - Adds nvidia,gpio-controller property. This simplifies how GTE driver retrieves GPIO controller instance, see below explanation. Without this property code would look like: if (of_device_is_compatible(dev->of_node, "nvidia,tegra194-gte-aon")) hte_dev->c = gpiochip_find("tegra194-gpio-aon", tegra_get_gpiochip_from_name); else if (of_device_is_compatible(dev->of_node, "nvidia,tegra234-gte-aon")) hte_dev->c = gpiochip_find("tegra234-gpio-aon", tegra_get_gpiochip_from_name); else return -ENODEV; This means for every future addition of the compatible string, if else condition statements have to be expanded. With the property: gpio_ctrl = of_parse_phandle(dev->of_node, "nvidia,gpio-controller", 0); .... hte_dev->c = gpiochip_find(gpio_ctrl, tegra_get_gpiochip_from_of_node); We haven't technically started making use of these bindings, so backwards-compatibility shouldn't be an issue yet. Signed-off-by: Dipen Patel --- v2: - Removed nvidia,slices property - Added nvidia,gpio-controller based on review comments from Thierry, this will help simplify the hte provider driver. v3: - Explained changes in detail in commit message - Added allOf section per review comment .../timestamp/nvidia,tegra194-hte.yaml | 31 ++++++++++++------- 1 file changed, 20 insertions(+), 11 deletions(-) diff --git a/Documentation/devicetree/bindings/timestamp/nvidia,tegra194-hte.yaml b/Documentation/devicetree/bindings/timestamp/nvidia,tegra194-hte.yaml index c31e207d1652..eb904ac2f331 100644 --- a/Documentation/devicetree/bindings/timestamp/nvidia,tegra194-hte.yaml +++ b/Documentation/devicetree/bindings/timestamp/nvidia,tegra194-hte.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/timestamp/nvidia,tegra194-hte.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Tegra194 on chip generic hardware timestamping engine (HTE) +title: Tegra on chip generic hardware timestamping engine (HTE) provider maintainers: - Dipen Patel @@ -23,6 +23,8 @@ properties: enum: - nvidia,tegra194-gte-aon - nvidia,tegra194-gte-lic + - nvidia,tegra234-gte-aon + - nvidia,tegra234-gte-lic reg: maxItems: 1 @@ -38,14 +40,11 @@ properties: minimum: 1 maximum: 256 - nvidia,slices: - $ref: /schemas/types.yaml#/definitions/uint32 + nvidia,gpio-controller: + $ref: /schemas/types.yaml#/definitions/phandle description: - HTE lines are arranged in 32 bit slice where each bit represents different - line/signal that it can enable/configure for the timestamp. It is u32 - property and depends on the HTE instance in the chip. The value 3 is for - GPIO GTE and 11 for IRQ GTE. - enum: [3, 11] + The phandle to AON gpio controller instance. This is required to handle + namespace conversion between GPIO and GTE. '#timestamp-cells': description: @@ -59,9 +58,20 @@ required: - compatible - reg - interrupts - - nvidia,slices - "#timestamp-cells" +allOf: + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra194-gte-aon + - nvidia,tegra234-gte-aon + then: + required: + - nvidia,gpio-controller + additionalProperties: false examples: @@ -71,7 +81,7 @@ examples: reg = <0xc1e0000 0x10000>; interrupts = <0 13 0x4>; nvidia,int-threshold = <1>; - nvidia,slices = <3>; + nvidia,gpio-controller = <&gpio_aon>; #timestamp-cells = <1>; }; @@ -81,7 +91,6 @@ examples: reg = <0x3aa0000 0x10000>; interrupts = <0 11 0x4>; nvidia,int-threshold = <1>; - nvidia,slices = <11>; #timestamp-cells = <1>; }; From patchwork Fri Mar 10 19:06:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dipen Patel X-Patchwork-Id: 661903 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7BDE7C6FD19 for ; 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Fri, 10 Mar 2023 11:06:39 -0800 From: Dipen Patel To: , , , , , , , , , , , , , CC: Dipen Patel Subject: [PATCH V3 3/6] hte: Re-phrase tegra API document Date: Fri, 10 Mar 2023 11:06:31 -0800 Message-ID: <20230310190634.5053-4-dipenp@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230310190634.5053-1-dipenp@nvidia.com> References: <20230310190634.5053-1-dipenp@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT085:EE_|IA1PR12MB7712:EE_ X-MS-Office365-Filtering-Correlation-Id: 41fdef68-452e-431b-da8e-08db219a9bfe X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: nAzyAvOGVjM/C+UY7DxsmvXJPiDjUuQHDJnSM7BwcT3ZxTfsGJ+oWs0lnYzoSGmoiAl1gpqRTgYr4XlU04Dp8gAaKi/vaV3/FdKLgtAZcL6L2MhNEXdusHyXY5sqdpy7W9ftkmXorrTEpmwtWujDe6+Ijg0ZvsruIQy5TUlcFgQrJqoUTCIIseTME3j+SlAHMunwk2Y8AS4zJz8IgNoScgnelWeScqbLbQK2OSSY5DzapnBP0WX85UuWnF6H+q9MubXRKaW5PFetWJveCR6Vc7ZsAJmJublXJ826lnb6qfM2nyxFHJR2QlcNYwlb4TQJY48Fjak39ZlV/Hrwy+6wYGNTbjvdbl89UzCrEk01tEXfjPJ4E+VyjYhSOd1JgBGli8JalgG5X0WNx28q1mGzxBpKFvsmuvin6kc7pB8Nz8yh1dWfuUi55+xTuiraXe/OV0gCX2IOaGZjmrW+CBYuuFwOZBq8Xdp1gwM5cyVok20KD7haQey1sSwuFJ+jZHmF/TBQB+nPDVNI8cRm2nmiq8VA9CcwPUCIkAJUOYFUz1fNizsuTBmVFnQ8qRdOx+0kgWmiTeYBvar9NAO+CXm2id6IbJvxTnQW4eHuyZMfKlLyYJHcyky8DojifWXm0YLG/VCiA+AfuCOT+PMsS/D1stZhQjp3fLYD/pr25PUQiFxQHhanEqyNf+V4n1rQDVIGy4KiMfWSPrlIskLhA0BX27x+7mMRmUS0H3RyZsldmM0RoRmybtZEahIW++0iO0ida3egfjj0o/kBruHcgO8nEv31mg6PQk4RW4Y85C8pwTigboryHyc+EPi2spYaMpnA X-Forefront-Antispam-Report: CIP:216.228.117.161; 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Signed-off-by: Dipen Patel --- Documentation/driver-api/hte/tegra194-hte.rst | 33 +++++++++---------- 1 file changed, 16 insertions(+), 17 deletions(-) diff --git a/Documentation/driver-api/hte/tegra194-hte.rst b/Documentation/driver-api/hte/tegra194-hte.rst index f2d617265546..85e654772782 100644 --- a/Documentation/driver-api/hte/tegra194-hte.rst +++ b/Documentation/driver-api/hte/tegra194-hte.rst @@ -5,25 +5,25 @@ HTE Kernel provider driver Description ----------- -The Nvidia tegra194 HTE provider driver implements two GTE -(Generic Timestamping Engine) instances: 1) GPIO GTE and 2) LIC -(Legacy Interrupt Controller) IRQ GTE. Both GTE instances get the -timestamp from the system counter TSC which has 31.25MHz clock rate, and the -driver converts clock tick rate to nanoseconds before storing it as timestamp -value. +The Nvidia tegra HTE provider also known as GTE (Generic Timestamping Engine) +driver implements two GTE instances: 1) GPIO GTE and 2) LIC +(Legacy Interrupt Controller) IRQ GTE. Both GTE instances get the timestamp +from the system counter TSC which has 31.25MHz clock rate, and the driver +converts clock tick rate to nanoseconds before storing it as timestamp value. GPIO GTE -------- This GTE instance timestamps GPIO in real time. For that to happen GPIO -needs to be configured as input. The always on (AON) GPIO controller instance -supports timestamping GPIOs in real time and it has 39 GPIO lines. The GPIO GTE -and AON GPIO controller are tightly coupled as it requires very specific bits -to be set in GPIO config register before GPIO GTE can be used, for that GPIOLIB -adds two optional APIs as below. The GPIO GTE code supports both kernel -and userspace consumers. The kernel space consumers can directly talk to HTE -subsystem while userspace consumers timestamp requests go through GPIOLIB CDEV -framework to HTE subsystem. +needs to be configured as input. Only the always on (AON) GPIO controller +instance supports timestamping GPIOs in real time as it is tightly coupled with +the GPIO GTE. To support this, GPIOLIB adds two optional APIs as mentioned +below. The GPIO GTE code supports both kernel and userspace consumers. The +kernel space consumers can directly talk to HTE subsystem while userspace +consumers timestamp requests go through GPIOLIB CDEV framework to HTE +subsystem. The hte devicetree binding described at +``Documentation/devicetree/bindings/timestamp`` provides an example of how a +consumer can request an GPIO line. See gpiod_enable_hw_timestamp_ns() and gpiod_disable_hw_timestamp_ns(). @@ -34,9 +34,8 @@ returns the timestamp in nanoseconds. LIC (Legacy Interrupt Controller) IRQ GTE ----------------------------------------- -This GTE instance timestamps LIC IRQ lines in real time. There are 352 IRQ -lines which this instance can add timestamps to in real time. The hte -devicetree binding described at ``Documentation/devicetree/bindings/timestamp`` +This GTE instance timestamps LIC IRQ lines in real time. The hte devicetree +binding described at ``Documentation/devicetree/bindings/timestamp`` provides an example of how a consumer can request an IRQ line. Since it is a one-to-one mapping with IRQ GTE provider, consumers can simply specify the IRQ number that they are interested in. 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SFS:(13230025)(4636009)(396003)(39860400002)(346002)(136003)(376002)(451199018)(46966006)(36840700001)(356005)(36756003)(110136005)(478600001)(5660300002)(7416002)(316002)(7696005)(107886003)(70206006)(8936002)(2906002)(8676002)(70586007)(4326008)(41300700001)(82740400003)(1076003)(36860700001)(7636003)(921005)(40480700001)(86362001)(186003)(2616005)(26005)(82310400005)(83380400001)(6666004)(336012)(426003)(47076005)(83996005)(2101003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Mar 2023 19:06:53.3857 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: adf24e1c-577a-448f-38a6-08db219a9c62 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT056.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6268 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This patch adds HTE provider support for the Tegra234 and reflects the changes made in the device tree as follow. - Add slices field in the SoC specific structure - Remove gpio chip find by name function instead make use of the phandle parsed from the DT node Signed-off-by: Dipen Patel --- v2: - Changed how gpio_chip could be aquired for the mapping v3: - Renamed gpio_chip matching function - Used of_node to fwnode field in gpio_chip matching function as data as gpio_chip struct does not have of_node member anymore. drivers/hte/hte-tegra194-test.c | 2 +- drivers/hte/hte-tegra194.c | 152 ++++++++++++++++++++++++++++---- 2 files changed, 138 insertions(+), 16 deletions(-) diff --git a/drivers/hte/hte-tegra194-test.c b/drivers/hte/hte-tegra194-test.c index 5d776a185bd6..d79c28a80517 100644 --- a/drivers/hte/hte-tegra194-test.c +++ b/drivers/hte/hte-tegra194-test.c @@ -16,7 +16,7 @@ #include /* - * This sample HTE GPIO test driver demonstrates HTE API usage by enabling + * This sample HTE test driver demonstrates HTE API usage by enabling * hardware timestamp on gpio_in and specified LIC IRQ lines. * * Note: gpio_out and gpio_in need to be shorted externally in order for this diff --git a/drivers/hte/hte-tegra194.c b/drivers/hte/hte-tegra194.c index 49a27af22742..7c8a2973e6a3 100644 --- a/drivers/hte/hte-tegra194.c +++ b/drivers/hte/hte-tegra194.c @@ -62,6 +62,10 @@ #define NV_AON_HTE_SLICE2_IRQ_GPIO_25 25 #define NV_AON_HTE_SLICE2_IRQ_GPIO_26 26 #define NV_AON_HTE_SLICE2_IRQ_GPIO_27 27 +#define NV_AON_HTE_SLICE2_IRQ_GPIO_28 28 +#define NV_AON_HTE_SLICE2_IRQ_GPIO_29 29 +#define NV_AON_HTE_SLICE2_IRQ_GPIO_30 30 +#define NV_AON_HTE_SLICE2_IRQ_GPIO_31 31 #define HTE_TECTRL 0x0 #define HTE_TETSCH 0x4 @@ -114,6 +118,7 @@ struct tegra_hte_line_data { struct tegra_hte_data { enum tegra_hte_type type; + u32 slices; u32 map_sz; u32 sec_map_sz; const struct tegra_hte_line_mapped *map; @@ -220,18 +225,129 @@ static const struct tegra_hte_line_mapped tegra194_aon_gpio_sec_map[] = { [39] = {NV_AON_SLICE_INVALID, 0}, }; -static const struct tegra_hte_data aon_hte = { +static const struct tegra_hte_line_mapped tegra234_aon_gpio_map[] = { + /* gpio, slice, bit_index */ + /* AA port */ + [0] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_11}, + [1] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_10}, + [2] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_9}, + [3] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_8}, + [4] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_7}, + [5] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_6}, + [6] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_5}, + [7] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_4}, + /* BB port */ + [8] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_3}, + [9] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_2}, + [10] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_1}, + [11] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_0}, + /* CC port */ + [12] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_22}, + [13] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_21}, + [14] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_20}, + [15] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_19}, + [16] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_18}, + [17] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_17}, + [18] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_16}, + [19] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_15}, + /* DD port */ + [20] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_14}, + [21] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_13}, + [22] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_12}, + /* EE port */ + [23] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_31}, + [24] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_30}, + [25] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_29}, + [26] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_28}, + [27] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_27}, + [28] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_26}, + [29] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_25}, + [30] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_24}, + /* GG port */ + [31] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_23}, +}; + +static const struct tegra_hte_line_mapped tegra234_aon_gpio_sec_map[] = { + /* gpio, slice, bit_index */ + /* AA port */ + [0] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_11}, + [1] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_10}, + [2] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_9}, + [3] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_8}, + [4] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_7}, + [5] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_6}, + [6] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_5}, + [7] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_4}, + /* BB port */ + [8] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_3}, + [9] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_2}, + [10] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_1}, + [11] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_0}, + [12] = {NV_AON_SLICE_INVALID, 0}, + [13] = {NV_AON_SLICE_INVALID, 0}, + [14] = {NV_AON_SLICE_INVALID, 0}, + [15] = {NV_AON_SLICE_INVALID, 0}, + /* CC port */ + [16] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_22}, + [17] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_21}, + [18] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_20}, + [19] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_19}, + [20] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_18}, + [21] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_17}, + [22] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_16}, + [23] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_15}, + /* DD port */ + [24] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_14}, + [25] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_13}, + [26] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_12}, + [27] = {NV_AON_SLICE_INVALID, 0}, + [28] = {NV_AON_SLICE_INVALID, 0}, + [29] = {NV_AON_SLICE_INVALID, 0}, + [30] = {NV_AON_SLICE_INVALID, 0}, + [31] = {NV_AON_SLICE_INVALID, 0}, + /* EE port */ + [32] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_31}, + [33] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_30}, + [34] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_29}, + [35] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_28}, + [36] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_27}, + [37] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_26}, + [38] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_25}, + [39] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_24}, + /* GG port */ + [40] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_23}, +}; + +static const struct tegra_hte_data t194_aon_hte = { .map_sz = ARRAY_SIZE(tegra194_aon_gpio_map), .map = tegra194_aon_gpio_map, .sec_map_sz = ARRAY_SIZE(tegra194_aon_gpio_sec_map), .sec_map = tegra194_aon_gpio_sec_map, .type = HTE_TEGRA_TYPE_GPIO, + .slices = 3, }; -static const struct tegra_hte_data lic_hte = { +static const struct tegra_hte_data t234_aon_hte = { + .map_sz = ARRAY_SIZE(tegra234_aon_gpio_map), + .map = tegra234_aon_gpio_map, + .sec_map_sz = ARRAY_SIZE(tegra234_aon_gpio_sec_map), + .sec_map = tegra234_aon_gpio_sec_map, + .type = HTE_TEGRA_TYPE_GPIO, + .slices = 3, +}; + +static const struct tegra_hte_data t194_lic_hte = { .map_sz = 0, .map = NULL, .type = HTE_TEGRA_TYPE_LIC, + .slices = 11, +}; + +static const struct tegra_hte_data t234_lic_hte = { + .map_sz = 0, + .map = NULL, + .type = HTE_TEGRA_TYPE_LIC, + .slices = 17, }; static inline u32 tegra_hte_readl(struct tegra_hte_soc *hte, u32 reg) @@ -534,8 +650,10 @@ static bool tegra_hte_match_from_linedata(const struct hte_chip *chip, } static const struct of_device_id tegra_hte_of_match[] = { - { .compatible = "nvidia,tegra194-gte-lic", .data = &lic_hte}, - { .compatible = "nvidia,tegra194-gte-aon", .data = &aon_hte}, + { .compatible = "nvidia,tegra194-gte-lic", .data = &t194_lic_hte}, + { .compatible = "nvidia,tegra194-gte-aon", .data = &t194_aon_hte}, + { .compatible = "nvidia,tegra234-gte-lic", .data = &t234_lic_hte}, + { .compatible = "nvidia,tegra234-gte-aon", .data = &t234_aon_hte}, { } }; MODULE_DEVICE_TABLE(of, tegra_hte_of_match); @@ -556,9 +674,9 @@ static void tegra_gte_disable(void *data) tegra_hte_writel(gs, HTE_TECTRL, 0); } -static int tegra_get_gpiochip_from_name(struct gpio_chip *chip, void *data) +static int tegra_gpiochip_match(struct gpio_chip *chip, void *data) { - return !strcmp(chip->label, data); + return chip->fwnode == of_node_to_fwnode(data); } static int tegra_hte_probe(struct platform_device *pdev) @@ -569,16 +687,10 @@ static int tegra_hte_probe(struct platform_device *pdev) struct device *dev; struct tegra_hte_soc *hte_dev; struct hte_chip *gc; + struct device_node *gpio_ctrl; dev = &pdev->dev; - ret = of_property_read_u32(dev->of_node, "nvidia,slices", &slices); - if (ret != 0) { - dev_err(dev, "Could not read slices\n"); - return -EINVAL; - } - nlines = slices << 5; - hte_dev = devm_kzalloc(dev, sizeof(*hte_dev), GFP_KERNEL); if (!hte_dev) return -ENOMEM; @@ -590,6 +702,9 @@ static int tegra_hte_probe(struct platform_device *pdev) dev_set_drvdata(&pdev->dev, hte_dev); hte_dev->prov_data = of_device_get_match_data(&pdev->dev); + slices = hte_dev->prov_data->slices; + nlines = slices << 5; + hte_dev->regs = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(hte_dev->regs)) return PTR_ERR(hte_dev->regs); @@ -635,8 +750,15 @@ static int tegra_hte_probe(struct platform_device *pdev) gc->match_from_linedata = tegra_hte_match_from_linedata; - hte_dev->c = gpiochip_find("tegra194-gpio-aon", - tegra_get_gpiochip_from_name); + gpio_ctrl = of_parse_phandle(dev->of_node, + "nvidia,gpio-controller", 0); + if (!gpio_ctrl) { + dev_err(dev, "gpio controller node not found\n"); + return -ENODEV; + } + + hte_dev->c = gpiochip_find(gpio_ctrl, tegra_gpiochip_match); + of_node_put(gpio_ctrl); if (!hte_dev->c) return dev_err_probe(dev, -EPROBE_DEFER, "wait for gpio controller\n"); From patchwork Fri Mar 10 19:06:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dipen Patel X-Patchwork-Id: 662559 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 51DC3C74A44 for ; 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Fri, 10 Mar 2023 11:06:40 -0800 From: Dipen Patel To: , , , , , , , , , , , , , CC: Dipen Patel Subject: [PATCH V3 5/6] gpio: tegra186: Add Tegra234 hte support Date: Fri, 10 Mar 2023 11:06:33 -0800 Message-ID: <20230310190634.5053-6-dipenp@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230310190634.5053-1-dipenp@nvidia.com> References: <20230310190634.5053-1-dipenp@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT068:EE_|BL1PR12MB5205:EE_ X-MS-Office365-Filtering-Correlation-Id: 917ed2f0-bb76-4b3b-eefe-08db219a99c8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ZFyzOkhHOeJdte8rGP9MbS9I+T3DJK/7oAQeLZFdmElSRclIVZjQAfYOObLZbvKPh6Go9ESL1Dlv82hkSjlhqazIbkfra4axU8BO1PqCUDAIt0V9vVX6LZVKWp3TDfnqX24uFPNDmrRx8zQ1/jYU7rQWI5XP1FXTleXFagzqql1TI3x6suJFcfAoM7sTBGtHfLv1qY3wOW4UCfzS9VICJbzrxGIIEEOsYP51hXT0uT972twePOzaCB/btJrNXBzQMrcVa/17C6SGi1q8UdEJF/LALW3ovgfGDnwcnrVgQWkDX4Dfkay5uzflYDeJKy3Sm8l5nDAxJg1X3mhunpYupZ3VQyzqsqKBEyLyZroUwAb3Do6B3o2UDbHXBoTUIC0I9+MSdXtvbjE3IRwW2bPbWL2iQWjq4o233pmqJbVEWDZBg83se/L9cyxZNNbAbwPy56aAbcs2UF4RQgPHRRXg2io3+v2/N6vqhagtS89Lu0raZQoMKzzIqN+mkfh0Ao/OpyquJe2/W9Q9mD1vIfhZXPx+as8bdzvB3drvAPjhai0aeaSFHVk9Za0CaYsWtfrcFoILndEVxgpi+NEJZYYDvOEq9kx6eD7C3K0Nx+O99rUrgrdvGz7CNEcanR3s4rzLiZbtHB9fL90eA8Sd4rs3/VRVQetDypx2TdUg27Cz5YhaK4KsWSNMKp5htFoRgVrXqRTb/QKR8hyx1puUj6nXsGU9rK4AM8uw6A/chtNvZONpMh/KBS/Fiz05uuqZ1oo4l7ujEiWN4N50YY+c/T7FjmMFKVT2rkwqifmNwuyY9h4= X-Forefront-Antispam-Report: CIP:216.228.117.160; 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Signed-off-by: Dipen Patel Acked-by: Thierry Reding Acked-by: Bartosz Golaszewski --- drivers/gpio/gpio-tegra186.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpio/gpio-tegra186.c b/drivers/gpio/gpio-tegra186.c index 14c872b6ad05..b904de0b1784 100644 --- a/drivers/gpio/gpio-tegra186.c +++ b/drivers/gpio/gpio-tegra186.c @@ -1134,6 +1134,7 @@ static const struct tegra_gpio_soc tegra234_aon_soc = { .name = "tegra234-gpio-aon", .instance = 1, .num_irqs_per_bank = 8, + .has_gte = true, }; #define TEGRA241_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \ From patchwork Fri Mar 10 19:06:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dipen Patel X-Patchwork-Id: 661904 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 35672C74A5B for ; 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Fri, 10 Mar 2023 11:06:41 -0800 From: Dipen Patel To: , , , , , , , , , , , , , CC: Dipen Patel Subject: [PATCH V3 6/6] arm64: tegra: Add GTE nodes Date: Fri, 10 Mar 2023 11:06:34 -0800 Message-ID: <20230310190634.5053-7-dipenp@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230310190634.5053-1-dipenp@nvidia.com> References: <20230310190634.5053-1-dipenp@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT101:EE_|SA0PR12MB4557:EE_ X-MS-Office365-Filtering-Correlation-Id: 303dbcaa-6113-43cc-cc03-08db219a9a6f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: WYq2G/lsXR/L+tfghzT/iPPSnimKqDrdHOx2bHE66HK/XA6lvoJMlmmwLBRHJwyyJp9uDCj6FdJ/E9dH5vgga3eue2GrXumP+M5a7h7Wdqi5sHE12cLpjx6V4XsYwsRN5lL+BUhztwjH3sj+eYbZTOWQxDeS43LwwaL8aB/Q3JXHepbWFW77ebKxhp/tN0NicyS12nRyf7MW6iIu8eVDlPL268EU79QBzfhCPc1O8SqwZmS9gM1kCASmOLdIKAtGB4mHGIrDu5fo1gD3P1wXbzkD1gZ7UlDB2zrxgIZYaWe5KHczudszuqo/VGC6sJwCQ5bStrmLS7HpCfFT0GMM8fbBpwXMVgp/yqJaL4MTc0btt2M+pwcIAsix286Co7GUf0wlV3YBnVAvfVzgB94IG42+wk48EXYScTJtPYbrH4yWC5iKJ6hOX3+74xGM2T4RljdVEczBw6a3NJRAUeY0D3EqFvsPvscsBv8elmcJT/JnQj47eMoTTo5wKHXvandTU9tLF2D4gMwW9bFT6uXbF9uHGUqMvLgKEIuT/LupCW3cEiPOv5Aw2lZ1gNNTKFWfjOo21M+aGUoG2QLjgzBs+8VJ6jOOycIUtNtGIvv8gAoADW4k9q5kPnx1YNnB21vQj9fC0CTb1YUER0JTyEdfTqEKjL2rDtkanXXKaughaAEV4/M4FotA/juh1Jl1A1x1TQThmFCrycajgKqYp6dIwiSrZHRcPzn117eZjl3CWcQZmWP7GnuKLx5zMHRtiV2crTCj2PCgzUbFhlq3Jv9WraKcSFXHZzCRy/eXWFCZwyFB+DKlGUa7dfPtQeleTy94 X-Forefront-Antispam-Report: CIP:216.228.117.160; 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Also modify AON GTE nodes for the tegra194 to remove nvidia,slice property and add nvidia,gpio-controller property to specify AON GPIO controller node so that GTE driver can do namespace conversion between GPIO lines provided by the gpiolib framework and hardware timestamping engine subsystem. Signed-off-by: Dipen Patel --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 3 +-- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 17 +++++++++++++++++ 2 files changed, 18 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 133dbe5b429d..7065643af275 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -1355,7 +1355,6 @@ reg = <0x0 0x3aa0000 0x0 0x10000>; interrupts = ; nvidia,int-threshold = <1>; - nvidia,slices = <11>; #timestamp-cells = <1>; status = "okay"; }; @@ -1578,7 +1577,7 @@ reg = <0x0 0xc1e0000 0x0 0x10000>; interrupts = ; nvidia,int-threshold = <1>; - nvidia,slices = <3>; + nvidia,gpio-controller = <&gpio_aon>; #timestamp-cells = <1>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 8fe8eda7654d..54790c6b6a2c 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -1156,6 +1156,14 @@ clock-names = "fuse"; }; + hte_lic: hardware-timestamp@3aa0000 { + compatible = "nvidia,tegra234-gte-lic"; + reg = <0x0 0x3aa0000 0x0 0x10000>; + interrupts = ; + nvidia,int-threshold = <1>; + #timestamp-cells = <1>; + }; + hsp_top0: hsp@3c00000 { compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; reg = <0x0 0x03c00000 0x0 0xa0000>; @@ -1673,6 +1681,15 @@ #mbox-cells = <2>; }; + hte_aon: hardware-timestamp@c1e0000 { + compatible = "nvidia,tegra234-gte-aon"; + reg = <0x0 0xc1e0000 0x0 0x10000>; + interrupts = ; + nvidia,int-threshold = <1>; + nvidia,gpio-controller = <&gpio_aon>; + #timestamp-cells = <1>; + }; + gen2_i2c: i2c@c240000 { compatible = "nvidia,tegra194-i2c"; reg = <0x0 0xc240000 0x0 0x100>;