From patchwork Wed Mar 8 23:09:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 660741 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 174E3C74A5B for ; Wed, 8 Mar 2023 23:09:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230108AbjCHXJj (ORCPT ); Wed, 8 Mar 2023 18:09:39 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52156 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230092AbjCHXJg (ORCPT ); Wed, 8 Mar 2023 18:09:36 -0500 Received: from mail-ot1-x32d.google.com (mail-ot1-x32d.google.com [IPv6:2607:f8b0:4864:20::32d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BCB6164216 for ; Wed, 8 Mar 2023 15:09:35 -0800 (PST) Received: by mail-ot1-x32d.google.com with SMTP id e26-20020a9d6e1a000000b00694274b5d3aso105036otr.5 for ; Wed, 08 Mar 2023 15:09:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678316975; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=J5PJqs5BsEDG1wdBjWwvXsmxEV4UYqM9XMe4BPKxtuE=; b=ZU2X+gAAyNbrZY+ccoI8srKvzJyr8um35igO3wIc7sMBIwllqYYzfzRU6hDuVGzBr0 Z1nYOwbnWSEU2h/QgERS5S+ydFsTvlH6nNRE6m/j2Ky9GxN0Ci41a7LPYHEiiTVxReeS 5/rsNyudWq6Ka5nqw1VCHvBgAFvmaBpkSChwE6nZBj4I59II15cjF9FSygL2ikudqtxw qHohzOZJtqX/gh0emEUgvxEyOY7gXKgDlB3fses6xEISy921rs9AcR/5Pl2Aa9G8erh1 ykGcKppFLstx1j6aEsp4/FwxKopraCwUk/BgBZrvZbWjl35uDJagPNrJBvQ8ucaq8GfB 0JTw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678316975; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=J5PJqs5BsEDG1wdBjWwvXsmxEV4UYqM9XMe4BPKxtuE=; b=ALjsqA7S7eQ3BfVmX0rXjsStyZoJ1yC8v1AuRFweYABF3LaJ0vJfCFM3iGIWUE8DoF t11ZDnWr1bHCcEfpndA0zLiekUpP/80KbrxdtTaVj/B0FSuUKUiotOC7kTyOvWheErLQ W/XruZgrJENIVnrqGiHeiLwsRpPFDFYlpnWVTYXDnZXD/URXQsnGFxDMy3z93ZH4GEQw XYAArY+xjc04Ip5E11CKyvin0XgLZI4IIJvXNlfs2OnHFTHzWt68427qs61xF1aOuFhD XNefFhBo2h2O07L3ObASK4GmAOGasOrH4lNUNVZ3G38bFYLyjfcRaJxkIlVDSyiTAS+V yV/Q== X-Gm-Message-State: AO0yUKWtuiS/jzxJoenGZB4Vn5Wp7X0zN3lHy2N0DddEzjmjTaTLbdQm jHv5bpLpEE3nXqSZ8zxcMuvX7A== X-Google-Smtp-Source: AK7set9Bws1cMOebllDwvv/UMswljCg2/saQYhCNiwvbJgz55DbPlRXex9ohzIAXXIZMreMO0qAwgA== X-Received: by 2002:a05:6830:1f42:b0:68d:41b2:5b75 with SMTP id u2-20020a0568301f4200b0068d41b25b75mr9166479oth.11.1678316975008; Wed, 08 Mar 2023 15:09:35 -0800 (PST) Received: from localhost ([136.49.140.41]) by smtp.gmail.com with ESMTPSA id q24-20020a05683031b800b0068bc48c61a5sm6976067ots.19.2023.03.08.15.09.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Mar 2023 15:09:34 -0800 (PST) From: Sam Protsenko To: Krzysztof Kozlowski , Rob Herring Cc: Alim Akhtar , Marek Szyprowski , Chanwoo Choi , Chanho Park , David Virag , linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/6] dt-bindings: power: pd-samsung: Allow pd nodes to be children of PMU Date: Wed, 8 Mar 2023 17:09:27 -0600 Message-Id: <20230308230931.27261-3-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230308230931.27261-1-semen.protsenko@linaro.org> References: <20230308230931.27261-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Introduce a new "samsung,pd-index" property to choose a specific power domain. This way it would be possible to avoid specifying any addresses in power domain nodes, relying solely on syscon regmap from the parent node (which should be a PMU system controller). Therefore the "reg" property is deprecated now, as it's more logical to describe power domains as children of PMU node, because PD registers reside in the PMU area. Signed-off-by: Sam Protsenko --- .../devicetree/bindings/power/pd-samsung.yaml | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/power/pd-samsung.yaml b/Documentation/devicetree/bindings/power/pd-samsung.yaml index a353a705292c..73178b1a56ea 100644 --- a/Documentation/devicetree/bindings/power/pd-samsung.yaml +++ b/Documentation/devicetree/bindings/power/pd-samsung.yaml @@ -25,6 +25,10 @@ properties: reg: maxItems: 1 + deprecated: true + description: + Physical base address and length of Power Domains area (if not a child of + PMU). clocks: deprecated: true @@ -45,10 +49,15 @@ properties: power-domains: maxItems: 1 + samsung,pd-index: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Power domain index (if a child of PMU). Valid values are defined in:: + "include/dt-bindings/power/samsung,exynos850-power.h" - for Exynos850 + required: - compatible - "#power-domain-cells" - - reg unevaluatedProperties: false From patchwork Wed Mar 8 23:09:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 660740 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 017F0C742A7 for ; Wed, 8 Mar 2023 23:10:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230101AbjCHXKU (ORCPT ); Wed, 8 Mar 2023 18:10:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52460 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230157AbjCHXJn (ORCPT ); Wed, 8 Mar 2023 18:09:43 -0500 Received: from mail-oi1-x22b.google.com (mail-oi1-x22b.google.com [IPv6:2607:f8b0:4864:20::22b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F367B746F6 for ; Wed, 8 Mar 2023 15:09:39 -0800 (PST) Received: by mail-oi1-x22b.google.com with SMTP id q15so299888oiw.11 for ; Wed, 08 Mar 2023 15:09:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678316979; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PcyN6J8psmsD0AipK3PVomDiouRZnU8VIxAcqRxXEto=; b=q3IlJ0PtdTA2WKmAG1d3tU8qg7pF582NBzTvvAggce9S3FSEvf8Gz1eSbYK8GaLQnn 6L2l9Sf3hNlSlEip7YSk0h/xcJl+Ed7vho0cOw6r7pTJBDMwPj18FOSbZDbSMGgx6VGu RfpZTkv8DVSB82/Own1gEy/I1RlVGgYO6k9+mn+kdO5UJMSgL7tSBwUsfV+9OI+WMrEy mRfk0RAD/el8kQzsmmsXmjXPj3YV5Iy7eE+rEN3xqqqKeRL9XgsSHMn8wooKY7iXKRbY XSLksVHSnubrHoKQmQO/yhDHgAuLvhlUBANYUW53lOO+bskC5Op3QxwZY4WFty3woN9C IQtA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678316979; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PcyN6J8psmsD0AipK3PVomDiouRZnU8VIxAcqRxXEto=; b=Ub7Qe0AF9umUigtyC1aN4NY/Oiu24zkoGyGeWcD4m1TZhi0PS4QksJk32Yqh+tD1Tc MpA7S2FunMzFnSChY1J3x/f8U3aGkFZ2z6MKLH/mob/VIjAQUTr9UTlH+wZw0FMn//9y j+ajNJ9cKe+8U8GVpI/GmdKuMFNaQA+cUBCwER9iXV+xXduN26zZ+CRwZbmpsRhHagLS iJzatTwzyztuL1ANRmvpGGYkEeQq0ITT5hqQdtdOPsBCFuSV0QAmK4X2dnzwiJd6bIr2 GgTADf4+GKvTcasJtqDZUHatqmePqLUxGflE9+7oLBo7DgNmMVvEez3Ei2ZCPGkQGTYd 1zfQ== X-Gm-Message-State: AO0yUKUfTSnbvoURiO4U67DgGtdX48IFUi1AVf2JozPxDgPrCU9LDSCb 9gShfYb5KYIRNMn9VpcRnKMqDQ== X-Google-Smtp-Source: AK7set96vUGZQ9x3seGiIj9aPGfeXEqlsBW10Gzyw7TR94eZbEmXWAiaUl8btBnUMn29SmszXEwL6g== X-Received: by 2002:aca:240c:0:b0:384:349a:15ef with SMTP id n12-20020aca240c000000b00384349a15efmr9062265oic.36.1678316977577; Wed, 08 Mar 2023 15:09:37 -0800 (PST) Received: from localhost ([136.49.140.41]) by smtp.gmail.com with ESMTPSA id g10-20020a9d618a000000b006864c8043e0sm6969520otk.61.2023.03.08.15.09.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Mar 2023 15:09:37 -0800 (PST) From: Sam Protsenko To: Krzysztof Kozlowski , Rob Herring Cc: Alim Akhtar , Marek Szyprowski , Chanwoo Choi , Chanho Park , David Virag , linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/6] soc: samsung: pm_domains: Implement proper I/O operations Date: Wed, 8 Mar 2023 17:09:29 -0600 Message-Id: <20230308230931.27261-5-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230308230931.27261-1-semen.protsenko@linaro.org> References: <20230308230931.27261-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Instead of doing in-place readl()/writel() calls fed with magic numbers, provide dedicated read/write functions which implement proper register accesses: - Get rid of magic numbers by introducing actual constants for PD registers - Rework the write function to perform a RMW operation, as PD registers have some bits markes as "Reserved" in TRM, which shouldn't be changed - Add helper functions for reading the STATUS reg and writing CONFIGURATION reg, to make user code more neat and clean New functions are designed in such a way that it's easy to rework those further on top of regmap API. Signed-off-by: Sam Protsenko --- drivers/soc/samsung/pm_domains.c | 42 +++++++++++++++++++++++++++++--- 1 file changed, 38 insertions(+), 4 deletions(-) diff --git a/drivers/soc/samsung/pm_domains.c b/drivers/soc/samsung/pm_domains.c index 522a43005a5a..dd1ec3541e11 100644 --- a/drivers/soc/samsung/pm_domains.c +++ b/drivers/soc/samsung/pm_domains.c @@ -18,6 +18,10 @@ #include #include +/* Register offsets inside Power Domain area in PMU */ +#define EXYNOS_PD_CONF 0x0 +#define EXYNOS_PD_STATUS 0x4 + struct exynos_pm_domain_config { /* Value for LOCAL_PWR_CFG and STATUS fields for each domain */ u32 local_pwr_cfg; @@ -33,6 +37,37 @@ struct exynos_pm_domain { u32 local_pwr_cfg; }; +static void exynos_pd_write(struct exynos_pm_domain *pd, unsigned int reg, + unsigned int mask, unsigned int val) +{ + u32 v; + + v = readl_relaxed(pd->base + reg); + v = (v & ~mask) | val; + writel_relaxed(v, pd->base + reg); +} + +static void exynos_pd_read(struct exynos_pm_domain *pd, unsigned int reg, + unsigned int *val) +{ + *val = readl_relaxed(pd->base + reg); +} + +static unsigned int exynos_pd_read_status(struct exynos_pm_domain *pd) +{ + unsigned int val; + + exynos_pd_read(pd, EXYNOS_PD_STATUS, &val); + val &= pd->local_pwr_cfg; + + return val; +} + +static void exynos_pd_write_conf(struct exynos_pm_domain *pd, u32 val) +{ + exynos_pd_write(pd, EXYNOS_PD_CONF, pd->local_pwr_cfg, val); +} + static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on) { struct exynos_pm_domain *pd; @@ -44,12 +79,12 @@ static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on) base = pd->base; pwr = power_on ? pd->local_pwr_cfg : 0; - writel_relaxed(pwr, base); + exynos_pd_write_conf(pd, pwr); /* Wait max 1ms */ timeout = 10; - while ((readl_relaxed(base + 0x4) & pd->local_pwr_cfg) != pwr) { + while (exynos_pd_read_status(pd) != pwr) { if (!timeout) { op = (power_on) ? "enable" : "disable"; pr_err("Power domain %s %s failed\n", domain->name, op); @@ -135,8 +170,7 @@ static int exynos_pd_probe(struct platform_device *pdev) pd->pd.power_off = exynos_pd_power_off; pd->pd.power_on = exynos_pd_power_on; - on = readl_relaxed(pd->base + 0x4) & pd->local_pwr_cfg; - + on = exynos_pd_read_status(pd); pm_genpd_init(&pd->pd, NULL, !on); ret = of_genpd_add_provider_simple(np, &pd->pd); From patchwork Wed Mar 8 23:09:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 660739 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1BB35C64EC4 for ; Wed, 8 Mar 2023 23:10:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230163AbjCHXKW (ORCPT ); Wed, 8 Mar 2023 18:10:22 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52454 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230119AbjCHXJn (ORCPT ); Wed, 8 Mar 2023 18:09:43 -0500 Received: from mail-oo1-xc2a.google.com (mail-oo1-xc2a.google.com [IPv6:2607:f8b0:4864:20::c2a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A6D2F6F620 for ; Wed, 8 Mar 2023 15:09:39 -0800 (PST) Received: by mail-oo1-xc2a.google.com with SMTP id a23-20020a4ad5d7000000b005250867d3d9so22610oot.10 for ; Wed, 08 Mar 2023 15:09:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678316979; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vEY2uA2o2oPbWjPX8guKf4jPFyrDqDNeEX5TBL2/D90=; b=j6kAa0wPCPa7yN1ZIU3m6I1acUcTN9xge5yJvWmt5R58739PeZyQDvykgJ2PNvk5oE Ca3l8dybpeMnDf11qoqQEH0L5uHd0PVAQOjKKbnPrdBVUjaPayhpl9ni3ZkuwvWPZRt9 VTxJjn3jd0L9M/R/rI7ML0V7h9TLwvDIEvxs4jevQK+0d0WvBy4OIyRggInkDeRJ/uq8 mmSxX1UQKKxKmVnDHwq+uRzykwyy4fl0uOiMFutoyDxemoL/eSmmn1+uxLbG+7A1Ey4E 9lQqBddbKl96/521JETtnFyEDRt04svDU4akF3CI16xjwSR498CqRevfaxRmlJ5WZEku liXg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678316979; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vEY2uA2o2oPbWjPX8guKf4jPFyrDqDNeEX5TBL2/D90=; b=BkaGZryEKq3pFvCKv98mu381kF8By0cu3HZ9wZMnZ6eHY+FfET6nE+J8WtBkkAbmWS SfUcH020nQ8W8AFL7mO9Q7egdRdn+nkgOFNrOcG7CeeSeWZTGFVptP9h48OhWcMaQcti 0Nv/RDSEj33ir0LoeGm8Ki71jQuyKpX/DW2/vA4XtElHknL8elcDDDEE27acN/UvyY8k MTCzgCyDW2fnj4Y97AkJdAhR/eoCVrBtQhSuvZJ1G7dH9DlZoShjsY3tMSuAG1Uh1HZK gQIJ273vXk7p3oNiLRHxo6yFfYfxZvg9fU0AQbeoYH2KjzB1YbUSiD9kUGlyREYeYbZe sQ/g== X-Gm-Message-State: AO0yUKWfbHPbyE1NCEjcBfiNKUOuinYgihOui0/Kd3O64DCouWHKnYs3 4X0eR3ixYTUAmEPqBVe/d0490g== X-Google-Smtp-Source: AK7set88QmQlJhM0W50tNT2+6aJVp6JPQ62Z1IozArM9BOkPuX7PtZUWUiN/ybmikpNvxg2vWqeETQ== X-Received: by 2002:a4a:8007:0:b0:525:25f1:af68 with SMTP id x7-20020a4a8007000000b0052525f1af68mr7533432oof.3.1678316978837; Wed, 08 Mar 2023 15:09:38 -0800 (PST) Received: from localhost ([136.49.140.41]) by smtp.gmail.com with ESMTPSA id x8-20020a9d4588000000b00690e21a46e1sm6952404ote.56.2023.03.08.15.09.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Mar 2023 15:09:38 -0800 (PST) From: Sam Protsenko To: Krzysztof Kozlowski , Rob Herring Cc: Alim Akhtar , Marek Szyprowski , Chanwoo Choi , Chanho Park , David Virag , linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 5/6] soc: samsung: pm_domains: Allow PD to be a child of PMU syscon Date: Wed, 8 Mar 2023 17:09:30 -0600 Message-Id: <20230308230931.27261-6-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230308230931.27261-1-semen.protsenko@linaro.org> References: <20230308230931.27261-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Power Domains registers are a part of the PMU area in Exynos SoCs. The PMU area is shared between multiple users (like WDT driver, reset driver, PD driver, etc), and it's usually already implemented as a system controller in the SoC device tree. Make it possible for a PD node to be a child of that PMU syscon and utilize its shared regmap instance in PD driver to access the PMU area registers. When a PD node is a child of PMU, the "samsung,pd-index" DT property is used to specify the particular power domain (instead of providing base address in "reg" property). Implement the support for that index property, so that the driver can look up corresponding register offsets by that index, if the property is present. But also keep the compatibility with existing device trees where the index property is not defined in PD nodes and which rely on raw read/write access to the PMU registers. Signed-off-by: Sam Protsenko --- drivers/soc/samsung/Kconfig | 1 + drivers/soc/samsung/pm_domains.c | 49 ++++++++++++++++++++++++++------ 2 files changed, 41 insertions(+), 9 deletions(-) diff --git a/drivers/soc/samsung/Kconfig b/drivers/soc/samsung/Kconfig index 7a8f291e7704..dfe7a973b272 100644 --- a/drivers/soc/samsung/Kconfig +++ b/drivers/soc/samsung/Kconfig @@ -51,6 +51,7 @@ config EXYNOS_PMU_ARM_DRIVERS config EXYNOS_PM_DOMAINS bool "Exynos PM domains" if COMPILE_TEST depends on (ARCH_EXYNOS && PM_GENERIC_DOMAINS) || COMPILE_TEST + select MFD_SYSCON config SAMSUNG_PM_CHECK bool "S3C2410 PM Suspend Memory CRC" diff --git a/drivers/soc/samsung/pm_domains.c b/drivers/soc/samsung/pm_domains.c index dd1ec3541e11..ec630a151247 100644 --- a/drivers/soc/samsung/pm_domains.c +++ b/drivers/soc/samsung/pm_domains.c @@ -17,6 +17,8 @@ #include #include #include +#include +#include /* Register offsets inside Power Domain area in PMU */ #define EXYNOS_PD_CONF 0x0 @@ -25,6 +27,10 @@ struct exynos_pm_domain_config { /* Value for LOCAL_PWR_CFG and STATUS fields for each domain */ u32 local_pwr_cfg; + + /* Power domain offsets in PMU area, for each power domain index */ + const unsigned int *pd_offsets; + size_t pd_offsets_num; }; /* @@ -35,22 +41,32 @@ struct exynos_pm_domain { void __iomem *base; struct generic_pm_domain pd; u32 local_pwr_cfg; + + unsigned int offset; + struct regmap *pmureg; }; static void exynos_pd_write(struct exynos_pm_domain *pd, unsigned int reg, unsigned int mask, unsigned int val) { - u32 v; - - v = readl_relaxed(pd->base + reg); - v = (v & ~mask) | val; - writel_relaxed(v, pd->base + reg); + if (pd->pmureg) { + regmap_update_bits(pd->pmureg, pd->offset + reg, mask, val); + } else { + u32 v; + + v = readl_relaxed(pd->base + reg); + v = (v & ~mask) | val; + writel_relaxed(v, pd->base + reg); + } } static void exynos_pd_read(struct exynos_pm_domain *pd, unsigned int reg, unsigned int *val) { - *val = readl_relaxed(pd->base + reg); + if (pd->pmureg) + regmap_read(pd->pmureg, pd->offset + reg, val); + else + *val = readl_relaxed(pd->base + reg); } static unsigned int exynos_pd_read_status(struct exynos_pm_domain *pd) @@ -133,6 +149,8 @@ static int exynos_pd_parse_dt(struct exynos_pm_domain *pd) struct device *dev = pd->dev; struct device_node *np = dev->of_node; const char *name; + u32 index; + int ret; variant = of_device_get_match_data(dev); pd->local_pwr_cfg = variant->local_pwr_cfg; @@ -143,9 +161,22 @@ static int exynos_pd_parse_dt(struct exynos_pm_domain *pd) if (!pd->pd.name) return -ENOMEM; - pd->base = of_iomap(np, 0); - if (!pd->base) - return -ENODEV; + ret = of_property_read_u32(np, "samsung,pd-index", &index); + if (!ret) { + if (index >= variant->pd_offsets_num) + return -EINVAL; + if (!dev->parent) + return -ENODEV; + + pd->offset = variant->pd_offsets[index]; + pd->pmureg = syscon_node_to_regmap(dev->parent->of_node); + if (IS_ERR(pd->pmureg)) + return PTR_ERR(pd->pmureg); + } else { + pd->base = of_iomap(np, 0); + if (!pd->base) + return -ENODEV; + } return 0; }