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Miller" , , Subject: [PATCH v3 1/9] crypto: ccp: Drop TEE support for IRQ handler Date: Fri, 3 Mar 2023 10:50:39 -0600 Message-ID: <20230303165050.2918-2-mario.limonciello@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230303165050.2918-1-mario.limonciello@amd.com> References: <20230303165050.2918-1-mario.limonciello@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT038:EE_|BL3PR12MB6452:EE_ X-MS-Office365-Filtering-Correlation-Id: c61d58f4-48a2-46ba-3cbb-08db1c077b95 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: PCjkbVYaeogqoOYjlzVKOdbhloJXBPaCrLAsbANEx4yyRasUvqwLqiBEuXm0jBjYbyx9LvmLB63mZKJPR9WITRADYVE0I0+2Y5LGWqVhKFPG39aNxxNfg3Go9+k/gXqNGRuYGXso+3+B0HktY4/2plhQi7+dnqXEmXGMn1OLwORwUtbc2wrd8lp5er/I82uX/UJj0TRW299v7NmuNHuNAMKKAkNMFJ5PYnH8LqUgW0yEhzI0i80bjrRLVysf+DMK+Exrf5giMwni8FH81kE8Z++xnLn4as9b8Zenz0mRLSYQgwPVMAw9NnE9G/4/LrUR7wO8x40cN/4u02x2ViQXAJKbxqzjDwpRpciOPm1wzyW0WkfM+GyEcZN14WeaMwj4hjJlrm8yIzbbPUEhCSTZa9h6B3d1S4L5eFbS17zFU9wo9lJ1ZgquTdvNhqmL8H8fFXvQd9lKsheYG3qw+XPngjnPe6T/ZQt1SNPZCN1T+5QFoq22my5WRH18WrTvOqQcF3e7mqcIE/KSb6Ojbwd0fyHi1yZ7SIifynAkF86xKNJ+O5mZHaDNXmgIVr8IUwCEjXEpQz6lBFdoucEPH0k9fhBH+pfoRv9WVdS9xV7Al9mCSgVM52GMUwsSXygFxguOGM7MXYH9OJ+rh+HhHLGqmk1M52pNN7wJRqK7Rq25SUe2MvAgDFxE9p1QtaE9/ceJH1JuRj8L5peS4Ta2yFIhdgqYYeIjubOK8zIuJtu4hj9gbMWFCi91yy2cF7vREWBjEahhQJyzHzZUJnSFBOXIVQ== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230025)(4636009)(396003)(376002)(136003)(39860400002)(346002)(451199018)(36840700001)(46966006)(40470700004)(83380400001)(36860700001)(47076005)(426003)(1076003)(6666004)(36756003)(40460700003)(82310400005)(81166007)(5660300002)(82740400003)(8936002)(40480700001)(478600001)(356005)(86362001)(26005)(16526019)(43170500006)(2616005)(336012)(186003)(70206006)(70586007)(44832011)(2906002)(7696005)(8676002)(4326008)(41300700001)(316002)(54906003)(110136005)(6636002)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Mar 2023 16:51:06.5377 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c61d58f4-48a2-46ba-3cbb-08db1c077b95 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT038.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR12MB6452 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org The only PSP mailbox that currently supports interrupt on completion is the SEV mailbox. Drop the dead code for the TEE subdriver to potentially call it. Acked-by: Rijo Thomas Signed-off-by: Mario Limonciello --- v2->v3: * Pick up tags --- drivers/crypto/ccp/psp-dev.c | 15 --------------- drivers/crypto/ccp/psp-dev.h | 7 ------- 2 files changed, 22 deletions(-) diff --git a/drivers/crypto/ccp/psp-dev.c b/drivers/crypto/ccp/psp-dev.c index c9c741ac8442..cd8d1974726a 100644 --- a/drivers/crypto/ccp/psp-dev.c +++ b/drivers/crypto/ccp/psp-dev.c @@ -46,9 +46,6 @@ static irqreturn_t psp_irq_handler(int irq, void *data) if (status) { if (psp->sev_irq_handler) psp->sev_irq_handler(irq, psp->sev_irq_data, status); - - if (psp->tee_irq_handler) - psp->tee_irq_handler(irq, psp->tee_irq_data, status); } /* Clear the interrupt status by writing the same value we read. */ @@ -219,18 +216,6 @@ void psp_clear_sev_irq_handler(struct psp_device *psp) psp_set_sev_irq_handler(psp, NULL, NULL); } -void psp_set_tee_irq_handler(struct psp_device *psp, psp_irq_handler_t handler, - void *data) -{ - psp->tee_irq_data = data; - psp->tee_irq_handler = handler; -} - -void psp_clear_tee_irq_handler(struct psp_device *psp) -{ - psp_set_tee_irq_handler(psp, NULL, NULL); -} - struct psp_device *psp_get_master_device(void) { struct sp_device *sp = sp_get_psp_master_device(); diff --git a/drivers/crypto/ccp/psp-dev.h b/drivers/crypto/ccp/psp-dev.h index d528eb04c3ef..06e1f317216d 100644 --- a/drivers/crypto/ccp/psp-dev.h +++ b/drivers/crypto/ccp/psp-dev.h @@ -40,9 +40,6 @@ struct psp_device { psp_irq_handler_t sev_irq_handler; void *sev_irq_data; - psp_irq_handler_t tee_irq_handler; - void *tee_irq_data; - void *sev_data; void *tee_data; @@ -53,10 +50,6 @@ void psp_set_sev_irq_handler(struct psp_device *psp, psp_irq_handler_t handler, void *data); void psp_clear_sev_irq_handler(struct psp_device *psp); -void psp_set_tee_irq_handler(struct psp_device *psp, psp_irq_handler_t handler, - void *data); -void psp_clear_tee_irq_handler(struct psp_device *psp); - struct psp_device *psp_get_master_device(void); #define PSP_CAPABILITY_SEV BIT(0) From patchwork Fri Mar 3 16:50:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 658558 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 66F73C7EE32 for ; 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Miller" , Jens Wiklander , , , , , Subject: [PATCH v3 2/9] crypto: ccp: Add a header for multiple drivers to use `__psp_pa` Date: Fri, 3 Mar 2023 10:50:40 -0600 Message-ID: <20230303165050.2918-3-mario.limonciello@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230303165050.2918-1-mario.limonciello@amd.com> References: <20230303165050.2918-1-mario.limonciello@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT091:EE_|MN2PR12MB4110:EE_ X-MS-Office365-Filtering-Correlation-Id: 5971ef95-42d5-4bf9-181d-08db1c077cec X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: dErXDvke7aRINFhpkHQ8Z9iEaM/vN4prg64c9d8taqJMiBT56LA8p5dgExOUYt5CLxMdcNfRcB6bkM1hlA6IFL0HqJYNMjtiFYPv+ox9Ua5dPEL4OjPmcFc8Zwewhro8uE4z1Vamgrzi3zT57UIuiHjLG6wHrMO/KfMeWzBa7YZMsswplkOrqFXJNEuZILltbpHGTS2vYsFqjl5mMUgZxFdSyC6M3hcwNNv+kfHjzlB62H00VCnEEfwbi+v22KzfyMOypLTX0/seyuA8JNHe4GDSBubG4/4ROGzoXczykVBr7pcrMm17bcJyuML2ubMDo8r6nGXxRRPP4eXJhzTlmBpCM79Rh7noTRI/yFM0NCJABwLZNJ4It6YIJ+7Do/cAzn0gR11huEbhy4OR7SjyKgWchZ4DRzvBoN502fZhjyrunC2Us0Y6jQpvHWhG86C8HN1H6Dovhfe9SX+IiQYlGtS6ClBeoJdU4jUngpmLFuTU8BJufvgI+K7SaRN4xrNAYDD2ZlPm8YgCgjH1QUsQjs89NA6rQ25muoGTtkVs6b4XfOreJlfwSS7wD6udaX6fkVTpT8v2Dv7hmpLRurzq7ejFKLQ41aTBNfXKepsaVRxbOTJoNAadPqEqjFtcjGIwJ8F1QwdyWisfoxRka/7SNVOSfWRvpBNsaP4bH6U9UbLEVQkpphrlbhuXB/fnL04dTlDE4CBUvVfQN8PD32KSl4GNRz8G2Ii5LXvYJJP7HynPCe1jiRw1JvTggKmgHqtfhnxFXidkTAMy4wusqT32pQ== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230025)(4636009)(346002)(39860400002)(376002)(136003)(396003)(451199018)(40470700004)(36840700001)(46966006)(336012)(36860700001)(8936002)(7696005)(1076003)(26005)(2616005)(6666004)(16526019)(186003)(41300700001)(478600001)(54906003)(83380400001)(110136005)(316002)(921005)(4326008)(356005)(8676002)(40480700001)(47076005)(40460700003)(70586007)(426003)(70206006)(81166007)(82310400005)(86362001)(7416002)(2906002)(5660300002)(82740400003)(44832011)(36756003)(81973001)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Mar 2023 16:51:08.7847 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5971ef95-42d5-4bf9-181d-08db1c077cec X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT091.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4110 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org The TEE subdriver for CCP, the amdtee driver and the i2c-designware-amdpsp drivers all include `psp-sev.h` even though they don't use SEV functionality. Move the definition of `__psp_pa` into a common header to be included by all of these drivers. Reviewed-by: Jan Dabros Acked-by: Jarkko Nikula # For the drivers/i2c/busses/i2c-designware-amdpsp.c Acked-by: Sumit Garg # For TEE subsystem bits Signed-off-by: Mario Limonciello Acked-by: Sean Christopherson # KVM --- v1->v2: * Add tags --- arch/x86/kvm/svm/sev.c | 1 + drivers/crypto/ccp/sev-dev.c | 1 + drivers/crypto/ccp/tee-dev.c | 2 +- drivers/i2c/busses/i2c-designware-amdpsp.c | 2 +- drivers/tee/amdtee/call.c | 2 +- drivers/tee/amdtee/shm_pool.c | 2 +- include/linux/psp-sev.h | 8 -------- include/linux/psp.h | 14 ++++++++++++++ 8 files changed, 20 insertions(+), 12 deletions(-) create mode 100644 include/linux/psp.h diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c index c25aeb550cd9..ec18a756b7c9 100644 --- a/arch/x86/kvm/svm/sev.c +++ b/arch/x86/kvm/svm/sev.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/crypto/ccp/sev-dev.c b/drivers/crypto/ccp/sev-dev.c index e2f25926eb51..28945ca7c856 100644 --- a/drivers/crypto/ccp/sev-dev.c +++ b/drivers/crypto/ccp/sev-dev.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include diff --git a/drivers/crypto/ccp/tee-dev.c b/drivers/crypto/ccp/tee-dev.c index 5c9d47f3be37..f24fc953718a 100644 --- a/drivers/crypto/ccp/tee-dev.c +++ b/drivers/crypto/ccp/tee-dev.c @@ -13,7 +13,7 @@ #include #include #include -#include +#include #include #include "psp-dev.h" diff --git a/drivers/i2c/busses/i2c-designware-amdpsp.c b/drivers/i2c/busses/i2c-designware-amdpsp.c index 8f36167bce62..80f28a1bbbef 100644 --- a/drivers/i2c/busses/i2c-designware-amdpsp.c +++ b/drivers/i2c/busses/i2c-designware-amdpsp.c @@ -4,7 +4,7 @@ #include #include #include -#include +#include #include #include diff --git a/drivers/tee/amdtee/call.c b/drivers/tee/amdtee/call.c index cec6e70f0ac9..e8cd9aaa3467 100644 --- a/drivers/tee/amdtee/call.c +++ b/drivers/tee/amdtee/call.c @@ -8,7 +8,7 @@ #include #include #include -#include +#include #include "amdtee_if.h" #include "amdtee_private.h" diff --git a/drivers/tee/amdtee/shm_pool.c b/drivers/tee/amdtee/shm_pool.c index f87f96a291c9..f0303126f199 100644 --- a/drivers/tee/amdtee/shm_pool.c +++ b/drivers/tee/amdtee/shm_pool.c @@ -5,7 +5,7 @@ #include #include -#include +#include #include "amdtee_private.h" static int pool_op_alloc(struct tee_shm_pool *pool, struct tee_shm *shm, diff --git a/include/linux/psp-sev.h b/include/linux/psp-sev.h index 1595088c428b..7fd17e82bab4 100644 --- a/include/linux/psp-sev.h +++ b/include/linux/psp-sev.h @@ -14,14 +14,6 @@ #include -#ifdef CONFIG_X86 -#include - -#define __psp_pa(x) __sme_pa(x) -#else -#define __psp_pa(x) __pa(x) -#endif - #define SEV_FW_BLOB_MAX_SIZE 0x4000 /* 16KB */ /** diff --git a/include/linux/psp.h b/include/linux/psp.h new file mode 100644 index 000000000000..202162487ec3 --- /dev/null +++ b/include/linux/psp.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __PSP_H +#define __PSP_H + +#ifdef CONFIG_X86 +#include + +#define __psp_pa(x) __sme_pa(x) +#else +#define __psp_pa(x) __pa(x) +#endif + +#endif /* __PSP_H */ From patchwork Fri Mar 3 16:50:41 2023 Content-Type: text/plain; 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Miller" , , , Subject: [PATCH v3 3/9] crypto: ccp: Move some PSP mailbox bit definitions into common header Date: Fri, 3 Mar 2023 10:50:41 -0600 Message-ID: <20230303165050.2918-4-mario.limonciello@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230303165050.2918-1-mario.limonciello@amd.com> References: <20230303165050.2918-1-mario.limonciello@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT054:EE_|CO6PR12MB5491:EE_ X-MS-Office365-Filtering-Correlation-Id: 9a7907b1-0920-4917-c843-08db1c077e0b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: qRUYT6FH2KC7DKCZv0nzyNXmjuYskV9nM5VIiE59eNxlBDFBWQF1oxZYe3aabmCTf1uJpVNmQCFI7sfz2NzhmXX5Dx4z0B4hJlk4YliACVolHOrnOUN/E6JN7skuHQjLzb/ekbjScwt9Eo8om3ocvDdZIytEfAsBLUj/YdUlxzqxDgcTEs34ZkyL8c7z98mbeacjCj+iR7Qv9nE37wZmqtZPte4xP0TEYaSHTX3kqLbsPQn7vcvg8abC2Iemo9/UTa0ddwq4I1n56gwpN+E2rKCS4rC7wBf6DZxX5bjg2pU8NkMdegjKaJBYW4hb4SAKLPp/qyULPmVlPKiMWSiWH9oaHJb5XwBfMPPlizPQJyqhOavIchxoFB7Asmr5dDl1I1q8Vr6E1xONRbQ6a7g+vIkmdxBR5q+AvFYLerkFRte0mBjaBhYpUsVyinF7sA0C4VYo1dS3pU/skFK4O8MLd+v3/305SmqYXiSqTNlfeYgi04xBlP8RPphjPn0SNh5VfHXytOxCeAgI2gFcUDnnz4il050XBd2tL7puqIGYgEnzoU7/rLnU1gYqoyoCuXh/tsP9tFKI3KdgdWwWAU02QgJb3UmvtU6cOWZeAysZLL1evnvIicZwt2nBO4oz8fS4HpxiSff5aHiLwBKzF4QW3ZanvdUkNYEdQugkR97BFripP8DKZ7QNImxhHDDw2hne/ehRPoXz8LsuJ9nbIbXExZwgU+DibGTlNRVmL9yW0fnkOWw3x7RnqwO//I69QQPs X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230025)(4636009)(376002)(136003)(396003)(39860400002)(346002)(451199018)(40470700004)(36840700001)(46966006)(83380400001)(426003)(36860700001)(47076005)(36756003)(40460700003)(6666004)(82740400003)(8936002)(7416002)(5660300002)(81166007)(478600001)(2906002)(921005)(356005)(40480700001)(86362001)(82310400005)(2616005)(16526019)(186003)(336012)(26005)(1076003)(4326008)(70586007)(8676002)(70206006)(7696005)(44832011)(15650500001)(316002)(54906003)(110136005)(41300700001)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Mar 2023 16:51:10.6544 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9a7907b1-0920-4917-c843-08db1c077e0b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT054.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO6PR12MB5491 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Some of the bits and fields used for mailboxes communicating with the PSP are common across all mailbox implementations (SEV, TEE, etc). Move these bits into the common `linux/psp.h` so they don't need to be re-defined for each implementation. Acked-by: Rijo Thomas Signed-off-by: Mario Limonciello --- v2->v3: * Pick up tags v1->v2: * Update comment to indicate it's PSP response not PSP ready --- drivers/crypto/ccp/psp-dev.h | 3 --- drivers/crypto/ccp/sev-dev.c | 15 +++++++-------- drivers/crypto/ccp/sev-dev.h | 2 +- drivers/crypto/ccp/tee-dev.c | 15 ++++++++------- drivers/i2c/busses/i2c-designware-amdpsp.c | 16 +++++----------- include/linux/psp.h | 12 ++++++++++++ 6 files changed, 33 insertions(+), 30 deletions(-) diff --git a/drivers/crypto/ccp/psp-dev.h b/drivers/crypto/ccp/psp-dev.h index 06e1f317216d..55f54bb2b3fb 100644 --- a/drivers/crypto/ccp/psp-dev.h +++ b/drivers/crypto/ccp/psp-dev.h @@ -17,9 +17,6 @@ #include "sp-dev.h" -#define PSP_CMDRESP_RESP BIT(31) -#define PSP_CMDRESP_ERR_MASK 0xffff - #define MAX_PSP_NAME_LEN 16 extern struct psp_device *psp_master; diff --git a/drivers/crypto/ccp/sev-dev.c b/drivers/crypto/ccp/sev-dev.c index 28945ca7c856..6440d35dfa4e 100644 --- a/drivers/crypto/ccp/sev-dev.c +++ b/drivers/crypto/ccp/sev-dev.c @@ -7,6 +7,7 @@ * Author: Brijesh Singh */ +#include #include #include #include @@ -103,7 +104,7 @@ static void sev_irq_handler(int irq, void *data, unsigned int status) /* Check if it is SEV command completion: */ reg = ioread32(sev->io_regs + sev->vdata->cmdresp_reg); - if (reg & PSP_CMDRESP_RESP) { + if (FIELD_GET(PSP_CMDRESP_RESP, reg)) { sev->int_rcvd = 1; wake_up(&sev->int_queue); } @@ -347,9 +348,7 @@ static int __sev_do_cmd_locked(int cmd, void *data, int *psp_ret) sev->int_rcvd = 0; - reg = cmd; - reg <<= SEV_CMDRESP_CMD_SHIFT; - reg |= SEV_CMDRESP_IOC; + reg = FIELD_PREP(SEV_CMDRESP_CMD, cmd) | SEV_CMDRESP_IOC; iowrite32(reg, sev->io_regs + sev->vdata->cmdresp_reg); /* wait for command completion */ @@ -367,11 +366,11 @@ static int __sev_do_cmd_locked(int cmd, void *data, int *psp_ret) psp_timeout = psp_cmd_timeout; if (psp_ret) - *psp_ret = reg & PSP_CMDRESP_ERR_MASK; + *psp_ret = FIELD_GET(PSP_CMDRESP_STS, reg); - if (reg & PSP_CMDRESP_ERR_MASK) { - dev_dbg(sev->dev, "sev command %#x failed (%#010x)\n", - cmd, reg & PSP_CMDRESP_ERR_MASK); + if (FIELD_GET(PSP_CMDRESP_STS, reg)) { + dev_dbg(sev->dev, "sev command %#x failed (%#010lx)\n", + cmd, FIELD_GET(PSP_CMDRESP_STS, reg)); ret = -EIO; } else { ret = sev_write_init_ex_file_if_required(cmd); diff --git a/drivers/crypto/ccp/sev-dev.h b/drivers/crypto/ccp/sev-dev.h index 666c21eb81ab..778c95155e74 100644 --- a/drivers/crypto/ccp/sev-dev.h +++ b/drivers/crypto/ccp/sev-dev.h @@ -25,8 +25,8 @@ #include #include +#define SEV_CMDRESP_CMD GENMASK(26, 16) #define SEV_CMD_COMPLETE BIT(1) -#define SEV_CMDRESP_CMD_SHIFT 16 #define SEV_CMDRESP_IOC BIT(0) struct sev_misc_dev { diff --git a/drivers/crypto/ccp/tee-dev.c b/drivers/crypto/ccp/tee-dev.c index f24fc953718a..5560bf8329a1 100644 --- a/drivers/crypto/ccp/tee-dev.c +++ b/drivers/crypto/ccp/tee-dev.c @@ -8,6 +8,7 @@ * Copyright (C) 2019,2021 Advanced Micro Devices, Inc. */ +#include #include #include #include @@ -69,7 +70,7 @@ static int tee_wait_cmd_poll(struct psp_tee_device *tee, unsigned int timeout, while (--nloop) { *reg = ioread32(tee->io_regs + tee->vdata->cmdresp_reg); - if (*reg & PSP_CMDRESP_RESP) + if (FIELD_GET(PSP_CMDRESP_RESP, *reg)) return 0; usleep_range(10000, 10100); @@ -149,9 +150,9 @@ static int tee_init_ring(struct psp_tee_device *tee) goto free_buf; } - if (reg & PSP_CMDRESP_ERR_MASK) { - dev_err(tee->dev, "tee: ring init command failed (%#010x)\n", - reg & PSP_CMDRESP_ERR_MASK); + if (FIELD_GET(PSP_CMDRESP_STS, reg)) { + dev_err(tee->dev, "tee: ring init command failed (%#010lx)\n", + FIELD_GET(PSP_CMDRESP_STS, reg)); tee_free_ring(tee); ret = -EIO; } @@ -179,9 +180,9 @@ static void tee_destroy_ring(struct psp_tee_device *tee) ret = tee_wait_cmd_poll(tee, TEE_DEFAULT_TIMEOUT, ®); if (ret) { dev_err(tee->dev, "tee: ring destroy command timed out\n"); - } else if (reg & PSP_CMDRESP_ERR_MASK) { - dev_err(tee->dev, "tee: ring destroy command failed (%#010x)\n", - reg & PSP_CMDRESP_ERR_MASK); + } else if (FIELD_GET(PSP_CMDRESP_STS, reg)) { + dev_err(tee->dev, "tee: ring destroy command failed (%#010lx)\n", + FIELD_GET(PSP_CMDRESP_STS, reg)); } free_ring: diff --git a/drivers/i2c/busses/i2c-designware-amdpsp.c b/drivers/i2c/busses/i2c-designware-amdpsp.c index 80f28a1bbbef..652e6b64bd5f 100644 --- a/drivers/i2c/busses/i2c-designware-amdpsp.c +++ b/drivers/i2c/busses/i2c-designware-amdpsp.c @@ -25,12 +25,6 @@ #define PSP_I2C_REQ_STS_BUS_BUSY 0x1 #define PSP_I2C_REQ_STS_INV_PARAM 0x3 -#define PSP_MBOX_FIELDS_STS GENMASK(15, 0) -#define PSP_MBOX_FIELDS_CMD GENMASK(23, 16) -#define PSP_MBOX_FIELDS_RESERVED GENMASK(29, 24) -#define PSP_MBOX_FIELDS_RECOVERY BIT(30) -#define PSP_MBOX_FIELDS_READY BIT(31) - struct psp_req_buffer_hdr { u32 total_size; u32 status; @@ -99,15 +93,15 @@ static int psp_check_mbox_recovery(struct psp_mbox __iomem *mbox) tmp = readl(&mbox->cmd_fields); - return FIELD_GET(PSP_MBOX_FIELDS_RECOVERY, tmp); + return FIELD_GET(PSP_CMDRESP_RECOVERY, tmp); } static int psp_wait_cmd(struct psp_mbox __iomem *mbox) { u32 tmp, expected; - /* Expect mbox_cmd to be cleared and ready bit to be set by PSP */ - expected = FIELD_PREP(PSP_MBOX_FIELDS_READY, 1); + /* Expect mbox_cmd to be cleared and the response bit to be set by PSP */ + expected = FIELD_PREP(PSP_CMDRESP_RESP, 1); /* * Check for readiness of PSP mailbox in a tight loop in order to @@ -124,7 +118,7 @@ static u32 psp_check_mbox_sts(struct psp_mbox __iomem *mbox) cmd_reg = readl(&mbox->cmd_fields); - return FIELD_GET(PSP_MBOX_FIELDS_STS, cmd_reg); + return FIELD_GET(PSP_CMDRESP_STS, cmd_reg); } static int psp_send_cmd(struct psp_i2c_req *req) @@ -148,7 +142,7 @@ static int psp_send_cmd(struct psp_i2c_req *req) writeq(req_addr, &mbox->i2c_req_addr); /* Write command register to trigger processing */ - cmd_reg = FIELD_PREP(PSP_MBOX_FIELDS_CMD, PSP_I2C_REQ_BUS_CMD); + cmd_reg = FIELD_PREP(PSP_CMDRESP_CMD, PSP_I2C_REQ_BUS_CMD); writel(cmd_reg, &mbox->cmd_fields); if (psp_wait_cmd(mbox)) diff --git a/include/linux/psp.h b/include/linux/psp.h index 202162487ec3..d3424790a70e 100644 --- a/include/linux/psp.h +++ b/include/linux/psp.h @@ -11,4 +11,16 @@ #define __psp_pa(x) __pa(x) #endif +/* + * Fields and bits used by most PSP mailboxes + * + * Note: Some mailboxes (such as SEV) have extra bits or different meanings + * and should include an appropriate local definition in their source file. + */ +#define PSP_CMDRESP_STS GENMASK(15, 0) +#define PSP_CMDRESP_CMD GENMASK(23, 16) +#define PSP_CMDRESP_RESERVED GENMASK(29, 24) +#define PSP_CMDRESP_RECOVERY BIT(30) +#define PSP_CMDRESP_RESP BIT(31) + #endif /* __PSP_H */ From patchwork Fri Mar 3 16:50:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 658848 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D0CE6C7EE32 for ; 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Miller" , , Subject: [PATCH v3 4/9] crypto: ccp: Add support for an interface for platform features Date: Fri, 3 Mar 2023 10:50:42 -0600 Message-ID: <20230303165050.2918-5-mario.limonciello@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230303165050.2918-1-mario.limonciello@amd.com> References: <20230303165050.2918-1-mario.limonciello@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT054:EE_|PH7PR12MB7966:EE_ X-MS-Office365-Filtering-Correlation-Id: a716691e-b4a9-4e7d-ccd3-08db1c078021 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 2BXzNzK7T5bXi7cHgIOu4k1Og+EFfvlmPAEnjtJ+te7ga4EPYdpIF9MiQ8rpj3d1jhidwXHw9vqzP+Tsvlh0euDPD9BTgbejQ5KTMcxRCi6kLqwjlvQL2FZWXT2hIn+QqYhiZf2VKGE5LxRX+1CrBjfUOxr4XNIgx4B620PRev0y4emij3jFn+yxkV+cM82lX2f4TKkfxrIF2wOUSMorlT5+tt+x+XR3Ujk1xi6b8sHf7OUiHr94xhqFDQ+XsA5iZRgXjT1LmpBVeUuvW66wPD3ktgqZtf7HR7/sj1znwpTYukPxrhZJxnWyHmdHqmkEuKGDs0xMyo3be9OjnBen40FRnSJZKciTpBnmf2V9mj3wxqcodYW5sfwO3zzLq4gs3pW7/F8WAqqKyPfY1qXPlssz4CNlShTDnZkHyEVXtmVQu8jRbPVLmExwq7J0gM2v497FI/D8Hh+uerWv/N4t60LVyFpKkSRPESC3qiVqCnaaK/02bIZdKSZUWDqgW2siM1X5fYTrw76Da+/QyeqCy0IwVDBoZ/UEuEg9g+gOUxWjHwfQe76hbdXTP8ARRQa356gw2HSEjtu1AaM6RmP0Eci4orXDIFF72T0LVLnnKm2+3fYx2boDrs5Ry/ufWXINhyFlB+FRzwF6II1m84JV+Z/rClgyRaeWzcG49E+DaKemp9+RghzZLO9d/tMfrT9XZt+wuiyvlvg99NsMKj5OrFR+t2LQMXw+Gqh66Cgp9olmYPWEyLPHK2poi9B1GQiixntXR7ky5mndkib8k92dtA== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230025)(4636009)(396003)(39860400002)(136003)(376002)(346002)(451199018)(46966006)(36840700001)(40470700004)(2906002)(82740400003)(41300700001)(316002)(478600001)(44832011)(5660300002)(82310400005)(30864003)(83380400001)(36756003)(40460700003)(8936002)(40480700001)(336012)(70206006)(8676002)(4326008)(70586007)(356005)(110136005)(81166007)(6636002)(54906003)(86362001)(36860700001)(7696005)(2616005)(426003)(47076005)(26005)(6666004)(1076003)(186003)(16526019)(36900700001)(134885004); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Mar 2023 16:51:14.1698 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a716691e-b4a9-4e7d-ccd3-08db1c078021 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT054.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7966 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Some platforms with a PSP support an interface for features that interact directly with the PSP instead of through a SEV or TEE environment. Initialize this interface so that other drivers can consume it. These drivers may either be subdrivers for the ccp module or external modules. For external modules, export a symbol for them to utilize. Signed-off-by: Mario Limonciello --- v2->v3: * Drop safety check * Rename mutex * Add unique messages v1->v2: * Fix comment text * Add safety check that register values were populated --- drivers/crypto/ccp/Makefile | 3 +- drivers/crypto/ccp/platform-access.c | 166 +++++++++++++++++++++++++++ drivers/crypto/ccp/platform-access.h | 34 ++++++ drivers/crypto/ccp/psp-dev.c | 17 +++ drivers/crypto/ccp/psp-dev.h | 1 + drivers/crypto/ccp/sp-dev.h | 7 ++ include/linux/psp-platform-access.h | 49 ++++++++ 7 files changed, 276 insertions(+), 1 deletion(-) create mode 100644 drivers/crypto/ccp/platform-access.c create mode 100644 drivers/crypto/ccp/platform-access.h create mode 100644 include/linux/psp-platform-access.h diff --git a/drivers/crypto/ccp/Makefile b/drivers/crypto/ccp/Makefile index db362fe472ea..f6196495e862 100644 --- a/drivers/crypto/ccp/Makefile +++ b/drivers/crypto/ccp/Makefile @@ -10,7 +10,8 @@ ccp-$(CONFIG_CRYPTO_DEV_CCP_DEBUGFS) += ccp-debugfs.o ccp-$(CONFIG_PCI) += sp-pci.o ccp-$(CONFIG_CRYPTO_DEV_SP_PSP) += psp-dev.o \ sev-dev.o \ - tee-dev.o + tee-dev.o \ + platform-access.o obj-$(CONFIG_CRYPTO_DEV_CCP_CRYPTO) += ccp-crypto.o ccp-crypto-objs := ccp-crypto-main.o \ diff --git a/drivers/crypto/ccp/platform-access.c b/drivers/crypto/ccp/platform-access.c new file mode 100644 index 000000000000..d7669a44dcfe --- /dev/null +++ b/drivers/crypto/ccp/platform-access.c @@ -0,0 +1,166 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * AMD Platform Security Processor (PSP) Platform Access interface + * + * Copyright (C) 2023 Advanced Micro Devices, Inc. + * + * Author: Mario Limonciello + * + * Some of this code is adapted from drivers/i2c/busses/i2c-designware-amdpsp.c + * developed by Jan Dabros and Copyright (C) 2022 Google Inc. + * + */ + +#include +#include +#include +#include + +#include "platform-access.h" + +#define PSP_CMD_TIMEOUT_US (500 * USEC_PER_MSEC) + +/* Recovery field should be equal 0 to start sending commands */ +static int check_recovery(u32 __iomem *cmd) +{ + return FIELD_GET(PSP_CMDRESP_RECOVERY, ioread32(cmd)); +} + +static int wait_cmd(u32 __iomem *cmd) +{ + u32 tmp, expected; + + /* Expect mbox_cmd to be cleared and ready bit to be set by PSP */ + expected = FIELD_PREP(PSP_CMDRESP_RESP, 1); + + /* + * Check for readiness of PSP mailbox in a tight loop in order to + * process further as soon as command was consumed. + */ + return readl_poll_timeout(cmd, tmp, (tmp & expected), 0, + PSP_CMD_TIMEOUT_US); +} + +int psp_check_platform_access_status(void) +{ + struct psp_device *psp = psp_get_master_device(); + + if (!psp || !psp->platform_access_data) + return -ENODEV; + + return 0; +} +EXPORT_SYMBOL(psp_check_platform_access_status); + +int psp_send_platform_access_msg(enum psp_platform_access_msg msg, + struct psp_request *req) +{ + struct psp_device *psp = psp_get_master_device(); + u32 __iomem *cmd, __iomem *lo, __iomem *hi; + struct psp_platform_access_device *pa_dev; + phys_addr_t req_addr; + u32 cmd_reg; + int ret; + + if (!psp || !psp->platform_access_data) + return -ENODEV; + + pa_dev = psp->platform_access_data; + cmd = psp->io_regs + pa_dev->vdata->cmdresp_reg; + lo = psp->io_regs + pa_dev->vdata->cmdbuff_addr_lo_reg; + hi = psp->io_regs + pa_dev->vdata->cmdbuff_addr_hi_reg; + + mutex_lock(&pa_dev->mailbox_mutex); + + if (check_recovery(cmd)) { + dev_dbg(psp->dev, "platform mailbox is in recovery\n"); + ret = -EBUSY; + goto unlock; + } + + if (wait_cmd(cmd)) { + dev_dbg(psp->dev, "platform mailbox is not done processing command\n"); + ret = -EBUSY; + goto unlock; + } + + /* + * Fill mailbox with address of command-response buffer, which will be + * used for sending i2c requests as well as reading status returned by + * PSP. Use physical address of buffer, since PSP will map this region. + */ + req_addr = __psp_pa(req); + iowrite32(lower_32_bits(req_addr), lo); + iowrite32(upper_32_bits(req_addr), hi); + + print_hex_dump_debug("->psp ", DUMP_PREFIX_OFFSET, 16, 2, req, + req->header.payload_size, false); + + /* Write command register to trigger processing */ + cmd_reg = FIELD_PREP(PSP_CMDRESP_CMD, msg); + iowrite32(cmd_reg, cmd); + + if (wait_cmd(cmd)) { + ret = -ETIMEDOUT; + goto unlock; + } + + /* Ensure it was triggered by this driver */ + if (ioread32(lo) != lower_32_bits(req_addr) || + ioread32(hi) != upper_32_bits(req_addr)) { + ret = -EBUSY; + goto unlock; + } + + /* Store the status in request header for caller to investigate */ + cmd_reg = ioread32(cmd); + req->header.status = FIELD_GET(PSP_CMDRESP_STS, cmd_reg); + if (req->header.status) { + ret = -EIO; + goto unlock; + } + + print_hex_dump_debug("<-psp ", DUMP_PREFIX_OFFSET, 16, 2, req, + req->header.payload_size, false); + + ret = 0; + +unlock: + mutex_unlock(&pa_dev->mailbox_mutex); + + return ret; +} +EXPORT_SYMBOL_GPL(psp_send_platform_access_msg); + +void platform_access_dev_destroy(struct psp_device *psp) +{ + struct psp_platform_access_device *pa_dev = psp->platform_access_data; + + if (!pa_dev) + return; + + mutex_destroy(&pa_dev->mailbox_mutex); + psp->platform_access_data = NULL; +} + +int platform_access_dev_init(struct psp_device *psp) +{ + struct device *dev = psp->dev; + struct psp_platform_access_device *pa_dev; + + pa_dev = devm_kzalloc(dev, sizeof(*pa_dev), GFP_KERNEL); + if (!pa_dev) + return -ENOMEM; + + psp->platform_access_data = pa_dev; + pa_dev->psp = psp; + pa_dev->dev = dev; + + pa_dev->vdata = (struct platform_access_vdata *)psp->vdata->platform_access; + + mutex_init(&pa_dev->mailbox_mutex); + + dev_dbg(dev, "platform access enabled\n"); + + return 0; +} diff --git a/drivers/crypto/ccp/platform-access.h b/drivers/crypto/ccp/platform-access.h new file mode 100644 index 000000000000..c3a97893320d --- /dev/null +++ b/drivers/crypto/ccp/platform-access.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * AMD Platform Security Processor (PSP) Platform Access interface + * + * Copyright (C) 2023 Advanced Micro Devices, Inc. + * + * Author: Mario Limonciello + */ + +#ifndef __PSP_PLATFORM_ACCESS_H__ +#define __PSP_PLATFORM_ACCESS_H__ + +#include +#include +#include +#include + +#include "psp-dev.h" + +struct psp_platform_access_device { + struct device *dev; + struct psp_device *psp; + + struct platform_access_vdata *vdata; + + struct mutex mailbox_mutex; + + void *platform_access_data; +}; + +void platform_access_dev_destroy(struct psp_device *psp); +int platform_access_dev_init(struct psp_device *psp); + +#endif /* __PSP_PLATFORM_ACCESS_H__ */ diff --git a/drivers/crypto/ccp/psp-dev.c b/drivers/crypto/ccp/psp-dev.c index cd8d1974726a..ec98f19800de 100644 --- a/drivers/crypto/ccp/psp-dev.c +++ b/drivers/crypto/ccp/psp-dev.c @@ -14,6 +14,7 @@ #include "psp-dev.h" #include "sev-dev.h" #include "tee-dev.h" +#include "platform-access.h" struct psp_device *psp_master; @@ -102,6 +103,17 @@ static int psp_check_tee_support(struct psp_device *psp) return 0; } +static void psp_init_platform_access(struct psp_device *psp) +{ + int ret; + + ret = platform_access_dev_init(psp); + if (ret) { + dev_warn(psp->dev, "platform access init failed: %d\n", ret); + return; + } +} + static int psp_init(struct psp_device *psp) { int ret; @@ -118,6 +130,9 @@ static int psp_init(struct psp_device *psp) return ret; } + if (psp->vdata->platform_access) + psp_init_platform_access(psp); + return 0; } @@ -198,6 +213,8 @@ void psp_dev_destroy(struct sp_device *sp) tee_dev_destroy(psp); + platform_access_dev_destroy(psp); + sp_free_psp_irq(sp, psp); if (sp->clear_psp_master_device) diff --git a/drivers/crypto/ccp/psp-dev.h b/drivers/crypto/ccp/psp-dev.h index 55f54bb2b3fb..505e4bdeaca8 100644 --- a/drivers/crypto/ccp/psp-dev.h +++ b/drivers/crypto/ccp/psp-dev.h @@ -39,6 +39,7 @@ struct psp_device { void *sev_data; void *tee_data; + void *platform_access_data; unsigned int capability; }; diff --git a/drivers/crypto/ccp/sp-dev.h b/drivers/crypto/ccp/sp-dev.h index 20377e67f65d..5ec6c219a731 100644 --- a/drivers/crypto/ccp/sp-dev.h +++ b/drivers/crypto/ccp/sp-dev.h @@ -53,9 +53,16 @@ struct tee_vdata { const unsigned int ring_rptr_reg; }; +struct platform_access_vdata { + const unsigned int cmdresp_reg; + const unsigned int cmdbuff_addr_lo_reg; + const unsigned int cmdbuff_addr_hi_reg; +}; + struct psp_vdata { const struct sev_vdata *sev; const struct tee_vdata *tee; + const struct platform_access_vdata *platform_access; const unsigned int feature_reg; const unsigned int inten_reg; const unsigned int intsts_reg; diff --git a/include/linux/psp-platform-access.h b/include/linux/psp-platform-access.h new file mode 100644 index 000000000000..977df5cfd494 --- /dev/null +++ b/include/linux/psp-platform-access.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __PSP_PLATFORM_ACCESS_H +#define __PSP_PLATFORM_ACCESS_H + +#include + +enum psp_platform_access_msg { + PSP_CMD_NONE = 0x0, +}; + +struct psp_req_buffer_hdr { + u32 payload_size; + u32 status; +} __packed; + +struct psp_request { + struct psp_req_buffer_hdr header; + void *buf; +} __packed; + +/** + * psp_send_platform_access_msg() - Send a message to control platform features + * + * This function is intended to be used by drivers outside of ccp to communicate + * with the platform. + * + * Returns: + * 0: success + * -%EBUSY: mailbox in recovery or in use + * -%ENODEV: driver not bound with PSP device + * -%ETIMEDOUT: request timed out + * -%EIO: unknown error (see kernel log) + */ +int psp_send_platform_access_msg(enum psp_platform_access_msg, struct psp_request *req); + +/** + * psp_check_platform_access_status() - Checks whether platform features is ready + * + * This function is intended to be used by drivers outside of ccp to determine + * if platform features has initialized. + * + * Returns: + * 0 platform features is ready + * -%ENODEV platform features is not ready or present + */ +int psp_check_platform_access_status(void); + +#endif /* __PSP_PLATFORM_ACCESS_H */ From patchwork Fri Mar 3 16:50:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 658557 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4F4CDC7EE2F for ; Fri, 3 Mar 2023 16:52:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231485AbjCCQwE (ORCPT ); Fri, 3 Mar 2023 11:52:04 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33702 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231408AbjCCQvp (ORCPT ); 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Fri, 3 Mar 2023 10:51:12 -0600 From: Mario Limonciello To: =?utf-8?b?SmFuIETEhWJyb8Wb?= , Grzegorz Bernacki , , , , Tom Lendacky , "John Allen" CC: Mario Limonciello , "David S. Miller" , , Subject: [PATCH v3 5/9] crypto: ccp: Enable platform access interface on client PSP parts Date: Fri, 3 Mar 2023 10:50:43 -0600 Message-ID: <20230303165050.2918-6-mario.limonciello@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230303165050.2918-1-mario.limonciello@amd.com> References: <20230303165050.2918-1-mario.limonciello@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT054:EE_|IA1PR12MB6188:EE_ X-MS-Office365-Filtering-Correlation-Id: 0827aafe-f93f-4609-d725-08db1c0780b0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: oTMZ+H8zcbbeTvIbpClFs1nODM/Pm/LE8RbctVzjMQ6pC1ZtpMXXR1FJ4UyMlsdmm0qgarRrf3II41TBTWkR91GCWkB/K1HA3XE9BnB2C6rks302GEwRtLq1vFie82bwTuwqvM3j+PXNTR0c+xanXbu770O9Bond9i1pez2YzWxUtwFPpygcgJzD3OILqqaCfOxsMWue3UMebNLxLpgtCke4QrqLVrqpmJWO6ZpQTbAQXdW1l6UWpA4loVN75UC2qX1muiZDCKoUdN+jALZTTRjBAsVHPAfr9/MSIv0H0WYwhR14LdxP4w5RpQbU9mV8tCMCLZkEuIUkdnxV+PdWV+ckIxECnKTNcGzxJ/ldd8+m690Xzw1OCfUXgZg22K6kgJrVIutvVtFQs66OsAQDGQLDCflMTdIcU8fhgP8xadTGz1uyafq/D3L4sv07r+iChm6Z0FDf6AiphqYCRcQ/xh4+aCOZ2FRuh1/yAIzqWSgJqHccYRU+bsG+TcRmaf3miFIESSdJ/pC+wdu7gq6Qrz0sFJEyBWBy4bKscXMm4x3TfK3PyRyBaqM8s+rUb2h/KJ/diYgsfujWctlUUUJWY1AgxnDdJGDQUXAi/0gfI0YLexm6tcflifNaamRc0FNM81al5W/K0z5B7TI2OZbt0J5Z0dx99bAsBvPAu44T17FBn6e3cf5wsRMic9fDeeQkLQ5HNaCtrYdVJStThBoYGvxnWbzKGMpA/MmUoDFFw3Q= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230025)(4636009)(39860400002)(376002)(396003)(136003)(346002)(451199018)(40470700004)(46966006)(36840700001)(86362001)(36756003)(82310400005)(8676002)(40460700003)(40480700001)(4326008)(70206006)(186003)(70586007)(336012)(41300700001)(8936002)(2616005)(16526019)(6636002)(54906003)(316002)(110136005)(478600001)(7696005)(6666004)(1076003)(26005)(5660300002)(82740400003)(356005)(81166007)(83380400001)(47076005)(426003)(36860700001)(44832011)(2906002)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Mar 2023 16:51:15.0916 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0827aafe-f93f-4609-d725-08db1c0780b0 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT054.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6188 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Client PSP parts support the platform access interface. Add the register offsets so that client parts will initialize this interface. Signed-off-by: Mario Limonciello --- drivers/crypto/ccp/sp-pci.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/crypto/ccp/sp-pci.c b/drivers/crypto/ccp/sp-pci.c index cde33b2ac71b..18aa902eb5ce 100644 --- a/drivers/crypto/ccp/sp-pci.c +++ b/drivers/crypto/ccp/sp-pci.c @@ -361,6 +361,12 @@ static const struct tee_vdata teev1 = { .ring_rptr_reg = 0x10554, /* C2PMSG_21 */ }; +static const struct platform_access_vdata pa_v1 = { + .cmdresp_reg = 0x10570, /* C2PMSG_28 */ + .cmdbuff_addr_lo_reg = 0x10574, /* C2PMSG_29 */ + .cmdbuff_addr_hi_reg = 0x10578, /* C2PMSG_30 */ +}; + static const struct psp_vdata pspv1 = { .sev = &sevv1, .feature_reg = 0x105fc, /* C2PMSG_63 */ @@ -377,6 +383,7 @@ static const struct psp_vdata pspv2 = { static const struct psp_vdata pspv3 = { .tee = &teev1, + .platform_access = &pa_v1, .feature_reg = 0x109fc, /* C2PMSG_63 */ .inten_reg = 0x10690, /* P2CMSG_INTEN */ .intsts_reg = 0x10694, /* P2CMSG_INTSTS */ From patchwork Fri Mar 3 16:50:45 2023 Content-Type: text/plain; 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Miller" , , Subject: [PATCH v3 7/9] crypto: ccp: Add support for ringing a platform doorbell Date: Fri, 3 Mar 2023 10:50:45 -0600 Message-ID: <20230303165050.2918-8-mario.limonciello@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230303165050.2918-1-mario.limonciello@amd.com> References: <20230303165050.2918-1-mario.limonciello@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT010:EE_|BY5PR12MB4129:EE_ X-MS-Office365-Filtering-Correlation-Id: 500244f8-5fba-43b8-09b1-08db1c0781c3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 8wcBofJz/qbVR9EmRPDxpv1E5ftVahdOBrCx3uAkeOkanIYZ/xm84dAGt8bXnJiNOvtStrvr10EVfqhHasY9XX5PzC4WEtuxDXOe/Q4NRCocbbJDYV3w6d28N6oHWmvYasa5xyOwVwAlcZzqUZ5hOuaMlRHrh65tst3jLqgD4z3cK0tXrllH3tln+AoWPrrj3EMagiccaEFbvn6qrChgF2C5RhH7n55/o7fxGtGhwBWMcRsXaLDQXdwXrQilqXIWcQfJoMy92hdgCzBaAezxEuUibHGKmKdK+wMIwuQtqAqgZGEbPY+E09zWVg/Sk3qtoKZvIFrt1HQEiy2XIz4GjkR8DoRf1K+/oyuOyypcIzVJasgS2bNHcQQ70GAJzcUSKWA5Xg8YJxpO/zgrTgeoDh8s0SrtfwHjZ2LFPmuierK1j+IfZmuOKRxdj972zQSVKVqrUxKMk5IDxZ0x8uJ7lgF3HyL5b2yj0iknH/rfmV5OiokJmfRCVXm3L70W42u/hDgmzZ4rYENAg1o14a8bdmSRahXPNIx5XopQEJzIEMhTNx6Rga6eYJM2oy9cC6UvA4eCY7YgCpmF0dKa6wHtNXuwKNhEyxdCn+j3k739BRmTApnK7O9QQOdubUGJN3463sc1ZDoVLFPNgTTTtea8LxCoQZZan32G3RUzgVQZ1lPtTH1SwbrYj2tz7uEqr5t+KISoz8cb8xJw1yWKY8juD5QTEP7JYhwCf/Uo8R2Ndpj5PsAbbFyxlRfcdcn7UPPc X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230025)(4636009)(136003)(346002)(376002)(39860400002)(396003)(451199018)(36840700001)(46966006)(40470700004)(2906002)(70586007)(82310400005)(70206006)(316002)(8676002)(966005)(44832011)(8936002)(40480700001)(36756003)(41300700001)(4326008)(2616005)(40460700003)(426003)(83380400001)(47076005)(336012)(186003)(6666004)(16526019)(7696005)(110136005)(54906003)(356005)(6636002)(478600001)(86362001)(1076003)(36860700001)(82740400003)(81166007)(26005)(5660300002)(36900700001)(134885004); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Mar 2023 16:51:16.8886 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 500244f8-5fba-43b8-09b1-08db1c0781c3 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT010.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4129 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Some platforms support using a doorbell to communicate. Export this feature for other drivers to utilize as well. Link: https://lore.kernel.org/linux-i2c/20220916131854.687371-3-jsd@semihalf.com/ Suggested-by: Jan Dabros Signed-off-by: Mario Limonciello --- v2->v3: * Squash register values in * Use command and button registers * Correct register values for incorrect ones previously shared * Use a unique mutex v1->v2: * New patch --- drivers/crypto/ccp/platform-access.c | 52 ++++++++++++++++++++++++++++ drivers/crypto/ccp/platform-access.h | 1 + drivers/crypto/ccp/sp-dev.h | 3 ++ drivers/crypto/ccp/sp-pci.c | 2 ++ include/linux/psp-platform-access.h | 15 ++++++++ include/linux/psp.h | 3 ++ 6 files changed, 76 insertions(+) diff --git a/drivers/crypto/ccp/platform-access.c b/drivers/crypto/ccp/platform-access.c index d7669a44dcfe..332e12637d48 100644 --- a/drivers/crypto/ccp/platform-access.c +++ b/drivers/crypto/ccp/platform-access.c @@ -132,6 +132,56 @@ int psp_send_platform_access_msg(enum psp_platform_access_msg msg, } EXPORT_SYMBOL_GPL(psp_send_platform_access_msg); +int psp_ring_platform_doorbell(enum psp_platform_access_msg msg) +{ + struct psp_device *psp = psp_get_master_device(); + struct psp_platform_access_device *pa_dev; + u32 __iomem *button, __iomem *cmd; + int ret, val; + + if (!psp || !psp->platform_access_data) + return -ENODEV; + + pa_dev = psp->platform_access_data; + button = psp->io_regs + pa_dev->vdata->doorbell_button_reg; + cmd = psp->io_regs + pa_dev->vdata->doorbell_cmd_reg; + + mutex_lock(&pa_dev->doorbell_mutex); + + if (check_recovery(cmd)) { + dev_dbg(psp->dev, "doorbell in recovery\n"); + ret = -EBUSY; + goto unlock; + } + + if (wait_cmd(cmd)) { + dev_dbg(psp->dev, "doorbell not done processing command\n"); + ret = -EBUSY; + goto unlock; + } + + iowrite32(FIELD_PREP(PSP_DRBL_MSG, msg), cmd); + iowrite32(PSP_DRBL_RING, button); + + if (wait_cmd(cmd)) { + ret = -ETIMEDOUT; + goto unlock; + } + + val = FIELD_GET(PSP_CMDRESP_STS, ioread32(cmd)); + if (val) { + ret = -EIO; + goto unlock; + } + + ret = 0; +unlock: + mutex_unlock(&pa_dev->doorbell_mutex); + + return ret; +} +EXPORT_SYMBOL_GPL(psp_ring_platform_doorbell); + void platform_access_dev_destroy(struct psp_device *psp) { struct psp_platform_access_device *pa_dev = psp->platform_access_data; @@ -140,6 +190,7 @@ void platform_access_dev_destroy(struct psp_device *psp) return; mutex_destroy(&pa_dev->mailbox_mutex); + mutex_destroy(&pa_dev->doorbell_mutex); psp->platform_access_data = NULL; } @@ -159,6 +210,7 @@ int platform_access_dev_init(struct psp_device *psp) pa_dev->vdata = (struct platform_access_vdata *)psp->vdata->platform_access; mutex_init(&pa_dev->mailbox_mutex); + mutex_init(&pa_dev->doorbell_mutex); dev_dbg(dev, "platform access enabled\n"); diff --git a/drivers/crypto/ccp/platform-access.h b/drivers/crypto/ccp/platform-access.h index c3a97893320d..a83f03beb869 100644 --- a/drivers/crypto/ccp/platform-access.h +++ b/drivers/crypto/ccp/platform-access.h @@ -24,6 +24,7 @@ struct psp_platform_access_device { struct platform_access_vdata *vdata; struct mutex mailbox_mutex; + struct mutex doorbell_mutex; void *platform_access_data; }; diff --git a/drivers/crypto/ccp/sp-dev.h b/drivers/crypto/ccp/sp-dev.h index 5ec6c219a731..1253a0217985 100644 --- a/drivers/crypto/ccp/sp-dev.h +++ b/drivers/crypto/ccp/sp-dev.h @@ -57,6 +57,9 @@ struct platform_access_vdata { const unsigned int cmdresp_reg; const unsigned int cmdbuff_addr_lo_reg; const unsigned int cmdbuff_addr_hi_reg; + const unsigned int doorbell_button_reg; + const unsigned int doorbell_cmd_reg; + }; struct psp_vdata { diff --git a/drivers/crypto/ccp/sp-pci.c b/drivers/crypto/ccp/sp-pci.c index 18aa902eb5ce..b5896f7af7ab 100644 --- a/drivers/crypto/ccp/sp-pci.c +++ b/drivers/crypto/ccp/sp-pci.c @@ -365,6 +365,8 @@ static const struct platform_access_vdata pa_v1 = { .cmdresp_reg = 0x10570, /* C2PMSG_28 */ .cmdbuff_addr_lo_reg = 0x10574, /* C2PMSG_29 */ .cmdbuff_addr_hi_reg = 0x10578, /* C2PMSG_30 */ + .doorbell_button_reg = 0x10a24, /* C2PMSG_73 */ + .doorbell_cmd_reg = 0x10a40, /* C2PMSG_80 */ }; static const struct psp_vdata pspv1 = { diff --git a/include/linux/psp-platform-access.h b/include/linux/psp-platform-access.h index f5a03cd11f10..1e1d0e077cec 100644 --- a/include/linux/psp-platform-access.h +++ b/include/linux/psp-platform-access.h @@ -35,6 +35,21 @@ struct psp_request { */ int psp_send_platform_access_msg(enum psp_platform_access_msg, struct psp_request *req); +/** + * psp_ring_platform_doorbell() - Ring platform doorbell + * + * This function is intended to be used by drivers outside of ccp to ring the + * platform doorbell with a message. + * + * Returns: + * 0: success + * -%EBUSY: mailbox in recovery or in use + * -%ENODEV: driver not bound with PSP device + * -%ETIMEDOUT: request timed out + * -%EIO: unknown error (see kernel log) + */ +int psp_ring_platform_doorbell(enum psp_platform_access_msg); + /** * psp_check_platform_access_status() - Checks whether platform features is ready * diff --git a/include/linux/psp.h b/include/linux/psp.h index d3424790a70e..92e60aeef21e 100644 --- a/include/linux/psp.h +++ b/include/linux/psp.h @@ -23,4 +23,7 @@ #define PSP_CMDRESP_RECOVERY BIT(30) #define PSP_CMDRESP_RESP BIT(31) +#define PSP_DRBL_MSG PSP_CMDRESP_CMD +#define PSP_DRBL_RING BIT(0) + #endif /* __PSP_H */