From patchwork Tue Feb 28 11:33:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 657929 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3AF0DC64ED6 for ; Tue, 28 Feb 2023 11:34:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231743AbjB1LeK (ORCPT ); Tue, 28 Feb 2023 06:34:10 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59464 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231717AbjB1Ld6 (ORCPT ); Tue, 28 Feb 2023 06:33:58 -0500 Received: from mail-lf1-x12e.google.com (mail-lf1-x12e.google.com [IPv6:2a00:1450:4864:20::12e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 735F22BEC4 for ; Tue, 28 Feb 2023 03:33:46 -0800 (PST) Received: by mail-lf1-x12e.google.com with SMTP id m7so12704311lfj.8 for ; Tue, 28 Feb 2023 03:33:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RHLuoMC1TsrcaoIJpAQH8uGPf0IEJuSQkho32eq1jak=; b=GlQiZ8CabeWT8jrPqKNDGhQpM8Uq31Ws0+f4ZyXWcRy7vD8d3/K23bHpx5+FEptJfT vt/w5PgxnkVercxXLm5DatJfoEqAhJ4D/VbHPNexMjfb6SWV87PxsLy8OsxPpgGpFlQS vqf02QbDvQj5VaSflNZHCMr23Dm4E6FJ+kJwHAsAyqQ1q2DuBCRKvI+0oWdUlz1xThQY OM9gvfQjzAxtZHCfAh7UExCbq6ZaM59w50W9DdCa1GFZNDpPZ+UD6eX4KDT8tssQ729q OGN6Dxfp9iYdtOdE1MiZ6Yr3ZqJqsi6f8cbiupcXIlioYtzR8W5Mt744BNb55sI3fMP3 Gh+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RHLuoMC1TsrcaoIJpAQH8uGPf0IEJuSQkho32eq1jak=; b=zpGxs4warORpTz2vlTfUKNDQ8y8qT3hXSgAf60OENRWyV+0PoNAWrokkzt5k0Zd6ci FyDNdI/SHX9MaCVjFVh+6RIZFZ+Wb+ZdXKdUvizJu0Yt01N5+BwaP0QzltuB51nBwi34 dyiR8v+GQkHioJCePYC2XdmUXlJjB9SbjvUUhdo19LQXjeibvWSi4ldV7D5x6PUQ/M1K PstV7XdTkXRUYvi8PykstoJ/VN98GQh8ND8AecRuJsP8d/Hxdp+GH4x06YuZ0OR9m6C3 ShsNhL3W6ECZRI1CWrG6hmStsriDzTVltLBIVLr3ATSexrTZ4BbiWS+jpBVdxyteIbXq TVYg== X-Gm-Message-State: AO0yUKVolLEvrramF2urdfcuUc/bECss63Nz+Nvmd3PYhemAEIjsBGX2 1PBlWQ4jJGe+bglmN2s6VPoo9w== X-Google-Smtp-Source: AK7set8A78h91xPnacTfbzD098aC+6UfOBQ+U0398uSjC3TwYKPt+A7f4jghzHejyctDUr5jJBkj8Q== X-Received: by 2002:ac2:5d2e:0:b0:4df:1d72:8e7d with SMTP id i14-20020ac25d2e000000b004df1d728e7dmr864937lfb.39.1677584024377; Tue, 28 Feb 2023 03:33:44 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id h20-20020ac25974000000b004dd0bbc89a1sm1288472lfp.244.2023.02.28.03.33.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Feb 2023 03:33:43 -0800 (PST) From: Dmitry Baryshkov To: David Airlie , Daniel Vetter , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin , Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten Cc: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= , dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org Subject: [PATCH 01/10] drm/i915/dsc: change DSC param tables to follow the DSC model Date: Tue, 28 Feb 2023 13:33:33 +0200 Message-Id: <20230228113342.2051425-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230228113342.2051425-1-dmitry.baryshkov@linaro.org> References: <20230228113342.2051425-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org After cross-checking DSC models (20150914, 20161212, 20210623) change values in rc_parameters tables to follow config files present inside the DSC model. Handle two places, where i915 tables diverged from the model, by patching the rc values in the code. Note: I left one case uncorrected, 8bpp/10bpc/range_max_qp[0], because the table in the VESA DSC 1.1 sets it to 4. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/i915/display/intel_vdsc.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index 207b2a648d32..d080741fd0b3 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -86,7 +86,7 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = { } }, /* 6BPP/14BPC */ - { 768, 15, 6144, 15, 25, 23, 27, { + { 768, 15, 6144, 15, 25, 23, 23, { { 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 }, { 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 }, { 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 }, @@ -115,6 +115,10 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = { }, /* 8BPP/10BPC */ { 512, 12, 6144, 7, 16, 15, 15, { + /* + * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however + * VESA DSC 1.1 Table E-5 sets it to 4. + */ { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 }, { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 }, { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 }, @@ -132,7 +136,7 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = { }, /* 8BPP/14BPC */ { 512, 12, 6144, 15, 24, 23, 23, { - { 0, 12, 0 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 }, + { 0, 12, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 }, { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 }, { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 }, { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 }, @@ -529,6 +533,16 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config) DSC_RANGE_BPG_OFFSET_MASK; } + if (DISPLAY_VER(dev_priv) < 13) { + if (compressed_bpp == 6 && + vdsc_cfg->bits_per_component == 8) + vdsc_cfg->rc_quant_incr_limit1 = 23; + + if (compressed_bpp == 8 && + vdsc_cfg->bits_per_component == 14) + vdsc_cfg->rc_range_params[0].range_bpg_offset = 0; + } + /* * BitsPerComponent value determines mux_word_size: * When BitsPerComponent is less than or 10bpc, muxWordSize will be equal to From patchwork Tue Feb 28 11:33:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 657928 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 26934C7EE36 for ; Tue, 28 Feb 2023 11:34:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231694AbjB1LeO (ORCPT ); Tue, 28 Feb 2023 06:34:14 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60314 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231724AbjB1LeF (ORCPT ); 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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id h20-20020ac25974000000b004dd0bbc89a1sm1288472lfp.244.2023.02.28.03.33.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Feb 2023 03:33:46 -0800 (PST) From: Dmitry Baryshkov To: David Airlie , Daniel Vetter , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin , Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten Cc: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= , dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org Subject: [PATCH 04/10] drm/i915/dsc: stop using interim structure for calculated params Date: Tue, 28 Feb 2023 13:33:36 +0200 Message-Id: <20230228113342.2051425-5-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230228113342.2051425-1-dmitry.baryshkov@linaro.org> References: <20230228113342.2051425-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Stop using an interim structure rc_parameters for storing calculated params and then setting drm_dsc_config using that structure. Instead put calculated params into the struct drm_dsc_config directly. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/i915/display/intel_vdsc.c | 89 +++++------------------ 1 file changed, 20 insertions(+), 69 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index d5a7e9494b23..1ee8d13c9d64 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -18,17 +18,6 @@ #include "intel_qp_tables.h" #include "intel_vdsc.h" -struct rc_parameters { - u16 initial_xmit_delay; - u8 first_line_bpg_offset; - u16 initial_offset; - u8 flatness_min_qp; - u8 flatness_max_qp; - u8 rc_quant_incr_limit0; - u8 rc_quant_incr_limit1; - struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES]; -}; - bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state) { const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); @@ -63,8 +52,7 @@ static bool is_pipe_dsc(struct intel_crtc *crtc, enum transcoder cpu_transcoder) } static void -calculate_rc_params(struct rc_parameters *rc, - struct drm_dsc_config *vdsc_cfg) +calculate_rc_params(struct drm_dsc_config *vdsc_cfg) { int bpc = vdsc_cfg->bits_per_component; int bpp = vdsc_cfg->bits_per_pixel >> 4; @@ -84,54 +72,54 @@ calculate_rc_params(struct rc_parameters *rc, u32 res, buf_i, bpp_i; if (vdsc_cfg->slice_height >= 8) - rc->first_line_bpg_offset = + vdsc_cfg->first_line_bpg_offset = 12 + DIV_ROUND_UP((9 * min(34, vdsc_cfg->slice_height - 8)), 100); else - rc->first_line_bpg_offset = 2 * (vdsc_cfg->slice_height - 1); + vdsc_cfg->first_line_bpg_offset = 2 * (vdsc_cfg->slice_height - 1); /* Our hw supports only 444 modes as of today */ if (bpp >= 12) - rc->initial_offset = 2048; + vdsc_cfg->initial_offset = 2048; else if (bpp >= 10) - rc->initial_offset = 5632 - DIV_ROUND_UP(((bpp - 10) * 3584), 2); + vdsc_cfg->initial_offset = 5632 - DIV_ROUND_UP(((bpp - 10) * 3584), 2); else if (bpp >= 8) - rc->initial_offset = 6144 - DIV_ROUND_UP(((bpp - 8) * 512), 2); + vdsc_cfg->initial_offset = 6144 - DIV_ROUND_UP(((bpp - 8) * 512), 2); else - rc->initial_offset = 6144; + vdsc_cfg->initial_offset = 6144; /* initial_xmit_delay = rc_model_size/2/compression_bpp */ - rc->initial_xmit_delay = DIV_ROUND_UP(DSC_RC_MODEL_SIZE_CONST, 2 * bpp); + vdsc_cfg->initial_xmit_delay = DIV_ROUND_UP(DSC_RC_MODEL_SIZE_CONST, 2 * bpp); - rc->flatness_min_qp = 3 + qp_bpc_modifier; - rc->flatness_max_qp = 12 + qp_bpc_modifier; + vdsc_cfg->flatness_min_qp = 3 + qp_bpc_modifier; + vdsc_cfg->flatness_max_qp = 12 + qp_bpc_modifier; - rc->rc_quant_incr_limit0 = 11 + qp_bpc_modifier; - rc->rc_quant_incr_limit1 = 11 + qp_bpc_modifier; + vdsc_cfg->rc_quant_incr_limit0 = 11 + qp_bpc_modifier; + vdsc_cfg->rc_quant_incr_limit1 = 11 + qp_bpc_modifier; bpp_i = (2 * (bpp - 6)); for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) { /* Read range_minqp and range_max_qp from qp tables */ - rc->rc_range_params[buf_i].range_min_qp = + vdsc_cfg->rc_range_params[buf_i].range_min_qp = intel_lookup_range_min_qp(bpc, buf_i, bpp_i); - rc->rc_range_params[buf_i].range_max_qp = + vdsc_cfg->rc_range_params[buf_i].range_max_qp = intel_lookup_range_max_qp(bpc, buf_i, bpp_i); /* Calculate range_bgp_offset */ if (bpp <= 6) { - rc->rc_range_params[buf_i].range_bpg_offset = ofs_und6[buf_i]; + vdsc_cfg->rc_range_params[buf_i].range_bpg_offset = ofs_und6[buf_i]; } else if (bpp <= 8) { res = DIV_ROUND_UP(((bpp - 6) * (ofs_und8[buf_i] - ofs_und6[buf_i])), 2); - rc->rc_range_params[buf_i].range_bpg_offset = + vdsc_cfg->rc_range_params[buf_i].range_bpg_offset = ofs_und6[buf_i] + res; } else if (bpp <= 12) { - rc->rc_range_params[buf_i].range_bpg_offset = + vdsc_cfg->rc_range_params[buf_i].range_bpg_offset = ofs_und8[buf_i]; } else if (bpp <= 15) { res = DIV_ROUND_UP(((bpp - 12) * (ofs_und15[buf_i] - ofs_und12[buf_i])), 3); - rc->rc_range_params[buf_i].range_bpg_offset = + vdsc_cfg->rc_range_params[buf_i].range_bpg_offset = ofs_und12[buf_i] + res; } else { - rc->rc_range_params[buf_i].range_bpg_offset = + vdsc_cfg->rc_range_params[buf_i].range_bpg_offset = ofs_und15[buf_i]; } } @@ -143,9 +131,6 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config) struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config; u16 compressed_bpp = pipe_config->dsc.compressed_bpp; - const struct rc_parameters *rc_params; - struct rc_parameters *rc = NULL; - u8 i = 0; int ret; vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay; @@ -169,43 +154,12 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config) * parameters */ if (DISPLAY_VER(dev_priv) >= 13) { - rc = kmalloc(sizeof(*rc), GFP_KERNEL); - if (!rc) - return -ENOMEM; - - calculate_rc_params(rc, vdsc_cfg); - rc_params = rc; + calculate_rc_params(vdsc_cfg); } else { ret = drm_dsc_setup_rc_params(vdsc_cfg); if (ret) return ret; - goto out; - } - - vdsc_cfg->first_line_bpg_offset = rc_params->first_line_bpg_offset; - vdsc_cfg->initial_xmit_delay = rc_params->initial_xmit_delay; - vdsc_cfg->initial_offset = rc_params->initial_offset; - vdsc_cfg->flatness_min_qp = rc_params->flatness_min_qp; - vdsc_cfg->flatness_max_qp = rc_params->flatness_max_qp; - vdsc_cfg->rc_quant_incr_limit0 = rc_params->rc_quant_incr_limit0; - vdsc_cfg->rc_quant_incr_limit1 = rc_params->rc_quant_incr_limit1; - - for (i = 0; i < DSC_NUM_BUF_RANGES; i++) { - vdsc_cfg->rc_range_params[i].range_min_qp = - rc_params->rc_range_params[i].range_min_qp; - vdsc_cfg->rc_range_params[i].range_max_qp = - rc_params->rc_range_params[i].range_max_qp; - /* - * Range BPG Offset uses 2's complement and is only a 6 bits. So - * mask it to get only 6 bits. - */ - vdsc_cfg->rc_range_params[i].range_bpg_offset = - rc_params->rc_range_params[i].range_bpg_offset & - DSC_RANGE_BPG_OFFSET_MASK; - } - - if (DISPLAY_VER(dev_priv) < 13) { if (compressed_bpp == 6 && vdsc_cfg->bits_per_component == 8) vdsc_cfg->rc_quant_incr_limit1 = 23; @@ -215,7 +169,6 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config) vdsc_cfg->rc_range_params[0].range_bpg_offset = 0; } -out: /* * BitsPerComponent value determines mux_word_size: * When BitsPerComponent is less than or 10bpc, muxWordSize will be equal to @@ -230,8 +183,6 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config) vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) / (vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset); - kfree(rc); - return 0; } From patchwork Tue Feb 28 11:33:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 657927 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 117FCC7EE2E for ; Tue, 28 Feb 2023 11:34:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231748AbjB1Le1 (ORCPT ); Tue, 28 Feb 2023 06:34:27 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60038 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231739AbjB1LeJ (ORCPT ); Tue, 28 Feb 2023 06:34:09 -0500 Received: from mail-lf1-x130.google.com (mail-lf1-x130.google.com [IPv6:2a00:1450:4864:20::130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AE250301B7 for ; Tue, 28 Feb 2023 03:33:49 -0800 (PST) Received: by mail-lf1-x130.google.com with SMTP id t11so12766826lfr.1 for ; Tue, 28 Feb 2023 03:33:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1V419a2+693FijZUUggU1L8f7XfNMxIn7m9KZRXZJ2I=; b=NEAjhimBgLthYf/pARVQSdYqj7CyX80epPYHzWY/EcpcFzJoz48lnK6sIQGsWCQEva 4Op4Md5H5AohMzjml5tPjvsWRckcX1j9HUkzVIXSTT5C2dadtY3T6mhIa5Yp0AIvX+BQ aDdOOQiby7b/aHkSbj7BXTs+tBhij4xY7+p5YTUQj5R4KK/c5nbR2lEba1D9i6RotOtz QBs1UPf7u4YtHx92yTNqio3fupPYvEQFy4/arBaHcHs3FJZV/erLh98IopC2FZg+/f10 3EG8xb+ldgqdEE7bWswgZ/mEgxvdB3Q/QSg9l+yT16C+yNbMcEB3Xn6aZY8Z0HuA2RO1 d+lA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1V419a2+693FijZUUggU1L8f7XfNMxIn7m9KZRXZJ2I=; b=yvcDzGriv3wJ95tELq+1GMgW1Kkp85yE8St81HuLVH3MgIXqAjKNZL4HA+ZV78Y8zL ps2nGqRLcfnGUcmSoyJq2fzWYvv1CaU2nRluwYYBFVbiNTR3vVoCxowxbI9uQsHHZWjc jQZ8pMtDu3IEc7rsy0Kvow0ZkPFpO4zTEmuaQfZTFOztCPmM8xsq2BnKDTWWc4g/3Fh0 Qs/gKkGle85DDyidar7ZSoR0vCLwr9rZ9SbtBczDdrQ9XmypB+hMImMfxAFuv/mKXu27 qKxJvnA5nwJK/1KlMU8Ouk49Rkqww2o7G1T19pmWaoFq4gUXypiN+/mBpRs2LQGaxl05 aDfQ== X-Gm-Message-State: AO0yUKUutYyg+LJJXnzBpmaYoWvabFZsxXYQtr1S8I/ECPXyosV+oJB9 P6ZKwq7ympOaEYdFWTojxYTVCQ== X-Google-Smtp-Source: AK7set85FgaOs1Qgd2X0h/9R5fqWgnikQJ8cJ7zgDeM/YvZApkZ+dDjFh3bgX0f3hZKEMBMMui6fug== X-Received: by 2002:ac2:598b:0:b0:4dd:99e1:4668 with SMTP id w11-20020ac2598b000000b004dd99e14668mr556812lfn.3.1677584027868; Tue, 28 Feb 2023 03:33:47 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id h20-20020ac25974000000b004dd0bbc89a1sm1288472lfp.244.2023.02.28.03.33.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Feb 2023 03:33:47 -0800 (PST) From: Dmitry Baryshkov To: David Airlie , Daniel Vetter , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin , Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten Cc: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= , dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org Subject: [PATCH 05/10] drm/display/dsc: use flat array for rc_parameters lookup Date: Tue, 28 Feb 2023 13:33:37 +0200 Message-Id: <20230228113342.2051425-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230228113342.2051425-1-dmitry.baryshkov@linaro.org> References: <20230228113342.2051425-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Next commits are going to add support for additional RC parameter lookup tables. These tables are going to use different bpp/bpc combinations, thus it makes little sense to keep the 2d array for RC parameters. Switch to using the flat array. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/display/drm_dsc_helper.c | 188 +++++++++++------------ 1 file changed, 88 insertions(+), 100 deletions(-) diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c index deaa84722bd4..a6d11f474656 100644 --- a/drivers/gpu/drm/display/drm_dsc_helper.c +++ b/drivers/gpu/drm/display/drm_dsc_helper.c @@ -307,24 +307,6 @@ void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg) } EXPORT_SYMBOL(drm_dsc_set_rc_buf_thresh); -enum ROW_INDEX_BPP { - ROW_INDEX_6BPP = 0, - ROW_INDEX_8BPP, - ROW_INDEX_10BPP, - ROW_INDEX_12BPP, - ROW_INDEX_15BPP, - MAX_ROW_INDEX -}; - -enum COLUMN_INDEX_BPC { - COLUMN_INDEX_8BPC = 0, - COLUMN_INDEX_10BPC, - COLUMN_INDEX_12BPC, - COLUMN_INDEX_14BPC, - COLUMN_INDEX_16BPC, - MAX_COLUMN_INDEX -}; - struct rc_parameters { u16 initial_xmit_delay; u8 first_line_bpg_offset; @@ -336,12 +318,20 @@ struct rc_parameters { struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES]; }; +struct rc_parameters_data { + u8 bpp; + u8 bpc; + struct rc_parameters params; +}; + +#define DSC_BPP(bpp) ((bpp) << 4) + /* * Selected Rate Control Related Parameter Recommended Values * from DSC_v1.11 spec & C Model release: DSC_model_20161212 */ -static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = { -{ +static const struct rc_parameters_data rc_parameters[] = { +{ DSC_BPP(6), 8, /* 6BPP/8BPC */ { 768, 15, 6144, 3, 13, 11, 11, { { 0, 4, 0 }, { 1, 6, -2 }, { 3, 8, -2 }, { 4, 8, -4 }, @@ -349,7 +339,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = { { 7, 11, -8 }, { 8, 12, -10 }, { 9, 12, -10 }, { 10, 12, -12 }, { 10, 12, -12 }, { 11, 12, -12 }, { 13, 14, -12 } } - }, + } +}, +{ DSC_BPP(6), 10, /* 6BPP/10BPC */ { 768, 15, 6144, 7, 17, 15, 15, { { 0, 8, 0 }, { 3, 10, -2 }, { 7, 12, -2 }, { 8, 12, -4 }, @@ -358,7 +350,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = { { 14, 16, -12 }, { 14, 16, -12 }, { 15, 16, -12 }, { 17, 18, -12 } } - }, + } +}, +{ DSC_BPP(6), 12, /* 6BPP/12BPC */ { 768, 15, 6144, 11, 21, 19, 19, { { 0, 12, 0 }, { 5, 14, -2 }, { 11, 16, -2 }, { 12, 16, -4 }, @@ -367,7 +361,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = { { 18, 20, -12 }, { 18, 20, -12 }, { 19, 20, -12 }, { 21, 22, -12 } } - }, + } +}, +{ DSC_BPP(6), 14, /* 6BPP/14BPC */ { 768, 15, 6144, 15, 25, 23, 23, { { 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 }, @@ -376,7 +372,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = { { 22, 24, -12 }, { 22, 24, -12 }, { 23, 24, -12 }, { 25, 26, -12 } } - }, + } +}, +{ DSC_BPP(6), 16, /* 6BPP/16BPC */ { 768, 15, 6144, 19, 29, 27, 27, { { 0, 20, 0 }, { 9, 22, -2 }, { 19, 24, -2 }, { 20, 24, -4 }, @@ -385,9 +383,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = { { 26, 28, -12 }, { 26, 28, -12 }, { 27, 28, -12 }, { 29, 30, -12 } } - }, + } }, -{ +{ DSC_BPP(8), 8, /* 8BPP/8BPC */ { 512, 12, 6144, 3, 12, 11, 11, { { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 }, @@ -395,7 +393,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = { { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 } } - }, + } +}, +{ DSC_BPP(8), 10, /* 8BPP/10BPC */ { 512, 12, 6144, 7, 16, 15, 15, { /* @@ -407,7 +407,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = { { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 }, { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 } } - }, + } +}, +{ DSC_BPP(8), 12, /* 8BPP/12BPC */ { 512, 12, 6144, 11, 20, 19, 19, { { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 }, @@ -416,7 +418,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = { { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 }, { 21, 23, -12 } } - }, + } +}, +{ DSC_BPP(8), 14, /* 8BPP/14BPC */ { 512, 12, 6144, 15, 24, 23, 23, { { 0, 12, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 }, @@ -425,7 +429,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = { { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 }, { 24, 25, -12 } } - }, + } +}, +{ DSC_BPP(8), 16, /* 8BPP/16BPC */ { 512, 12, 6144, 19, 28, 27, 27, { { 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 }, @@ -434,9 +440,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = { { 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 }, { 28, 29, -12 } } - }, + } }, -{ +{ DSC_BPP(10), 8, /* 10BPP/8BPC */ { 410, 15, 5632, 3, 12, 11, 11, { { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 }, @@ -444,7 +450,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = { { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 }, { 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 } } - }, + } +}, +{ DSC_BPP(10), 10, /* 10BPP/10BPC */ { 410, 15, 5632, 7, 16, 15, 15, { { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 }, @@ -452,7 +460,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = { { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 }, { 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 } } - }, + } +}, +{ DSC_BPP(10), 12, /* 10BPP/12BPC */ { 410, 15, 5632, 11, 20, 19, 19, { { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 }, @@ -461,7 +471,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = { { 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 }, { 19, 20, -12 } } - }, + } +}, +{ DSC_BPP(10), 14, /* 10BPP/14BPC */ { 410, 15, 5632, 15, 24, 23, 23, { { 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 }, @@ -470,7 +482,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = { { 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 }, { 23, 24, -12 } } - }, + } +}, +{ DSC_BPP(10), 16, /* 10BPP/16BPC */ { 410, 15, 5632, 19, 28, 27, 27, { { 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 }, @@ -479,9 +493,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = { { 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 }, { 27, 28, -12 } } - }, + } }, -{ +{ DSC_BPP(12), 8, /* 12BPP/8BPC */ { 341, 15, 2048, 3, 12, 11, 11, { { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 }, @@ -489,7 +503,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = { { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 } } - }, + } +}, +{ DSC_BPP(12), 10, /* 12BPP/10BPC */ { 341, 15, 2048, 7, 16, 15, 15, { { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 }, @@ -497,7 +513,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = { { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 }, { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 } } - }, + } +}, +{ DSC_BPP(12), 12, /* 12BPP/12BPC */ { 341, 15, 2048, 11, 20, 19, 19, { { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 }, @@ -506,7 +524,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = { { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 }, { 21, 23, -12 } } - }, + } +}, +{ DSC_BPP(12), 14, /* 12BPP/14BPC */ { 341, 15, 2048, 15, 24, 23, 23, { { 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 }, @@ -515,7 +535,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = { { 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 }, { 22, 23, -12 } } - }, + } +}, +{ DSC_BPP(12), 16, /* 12BPP/16BPC */ { 341, 15, 2048, 19, 28, 27, 27, { { 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 }, @@ -524,9 +546,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = { { 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 }, { 26, 27, -12 } } - }, + } }, -{ +{ DSC_BPP(15), 8, /* 15BPP/8BPC */ { 273, 15, 2048, 3, 12, 11, 11, { { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 }, @@ -534,7 +556,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = { { 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 }, { 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 } } - }, + } +}, +{ DSC_BPP(15), 10, /* 15BPP/10BPC */ { 273, 15, 2048, 7, 16, 15, 15, { { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 }, @@ -542,7 +566,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = { { 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 }, { 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 } } - }, + } +}, +{ DSC_BPP(15), 12, /* 15BPP/12BPC */ { 273, 15, 2048, 11, 20, 19, 19, { { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 }, @@ -551,7 +577,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = { { 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 }, { 16, 17, -12 } } - }, + } +}, +{ DSC_BPP(15), 14, /* 15BPP/14BPC */ { 273, 15, 2048, 15, 24, 23, 23, { { 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 }, @@ -560,7 +588,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = { { 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 }, { 20, 21, -12 } } - }, + } +}, +{ DSC_BPP(15), 16, /* 15BPP/16BPC */ { 273, 15, 2048, 19, 28, 27, 27, { { 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 }, @@ -570,59 +600,21 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = { { 24, 25, -12 } } } -} +}, +{ /* sentinel */ } }; -static int get_row_index_for_rc_params(u16 compressed_bpp) -{ - switch (compressed_bpp) { - case 6: - return ROW_INDEX_6BPP; - case 8: - return ROW_INDEX_8BPP; - case 10: - return ROW_INDEX_10BPP; - case 12: - return ROW_INDEX_12BPP; - case 15: - return ROW_INDEX_15BPP; - default: - return -EINVAL; - } -} - -static int get_column_index_for_rc_params(u8 bits_per_component) -{ - switch (bits_per_component) { - case 8: - return COLUMN_INDEX_8BPC; - case 10: - return COLUMN_INDEX_10BPC; - case 12: - return COLUMN_INDEX_12BPC; - case 14: - return COLUMN_INDEX_14BPC; - case 16: - return COLUMN_INDEX_16BPC; - default: - return -EINVAL; - } -} - -static const struct rc_parameters *get_rc_params(u16 compressed_bpp, +static const struct rc_parameters *get_rc_params(u16 dsc_bpp, u8 bits_per_component) { - int row_index, column_index; - - row_index = get_row_index_for_rc_params(compressed_bpp); - if (row_index < 0) - return NULL; + int i; - column_index = get_column_index_for_rc_params(bits_per_component); - if (column_index < 0) - return NULL; + for (i = 0; rc_parameters[i].bpp; i++) + if (rc_parameters[i].bpp == dsc_bpp && + rc_parameters[i].bpc == bits_per_component) + return &rc_parameters[i].params; - return &rc_parameters[row_index][column_index]; + return NULL; } /** @@ -636,11 +628,7 @@ int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg) const struct rc_parameters *rc_params; int i; - /* fractional BPP is not supported */ - if (vdsc_cfg->bits_per_pixel & 0xf) - return -EINVAL; - - rc_params = get_rc_params(vdsc_cfg->bits_per_pixel >> 4, + rc_params = get_rc_params(vdsc_cfg->bits_per_pixel, vdsc_cfg->bits_per_component); if (!rc_params) return -EINVAL; From patchwork Tue Feb 28 11:33:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 657926 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8A87BC64EC7 for ; Tue, 28 Feb 2023 11:34:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231720AbjB1Lea (ORCPT ); Tue, 28 Feb 2023 06:34:30 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60238 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231487AbjB1LeN (ORCPT ); Tue, 28 Feb 2023 06:34:13 -0500 Received: from mail-lf1-x130.google.com (mail-lf1-x130.google.com [IPv6:2a00:1450:4864:20::130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2A57D30191 for ; Tue, 28 Feb 2023 03:33:51 -0800 (PST) Received: by mail-lf1-x130.google.com with SMTP id s22so12709887lfi.9 for ; Tue, 28 Feb 2023 03:33:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wSIZDU9Jg/2Fu4qAh38NIaWYnR0lEE+twOi2NP/xMe0=; b=PnAiIz5fWMP+1y006x1EeT/Qwm4OHmdUE8UDBRmYFJLkLqTJYgB9YFJTCfBDGRlNd4 b7AWrnoEQkxlvoshB1ujfVje4TrAgVozJFKnTi+FWhMasGBWUT5ON15cWS8qNS9dCwOU I9H57VVrCjGujBwmmJUDh7JWkEBli3IYNvOXCYG2AM6fIRMBWHbUbOzFd94KiIN9bhzt lwhHSWj4VCeee+K6+x2ah8oj0yApqunXtC0HmhQe4/yPg8eUea3JCZfTODKj9sR6UEpM liU4kCY0mM94H8rlgJH38a/EnNdpZv0vPjZifCmQRJ5vduP8obWBw4Ur3wjlcTXn8Pmg HGBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wSIZDU9Jg/2Fu4qAh38NIaWYnR0lEE+twOi2NP/xMe0=; b=ry57P0xc3r4OMsC8UIY0SxBgyC47Ung4q7uTKNEHdcDwcAJOdFTVdj3VcR+aIDjmZi PaFJvQrp/IVDmoCBl+mlVxGcuzctmqXcz+n3bmPcxCGWa/jBuVaDkOu6nRESo+zgXxFd qBDEnzQ+gbY9ijJ3qguOE5ErJlbagck+g9XIVLRarMSkix8tU/LMnaKpO6V5GF4bs+om iKEJ5TksFkIq3i7QY07uet9kut0Ypju1iodkGjYnOR12UHwZLqil1AuK93U/k39avg2D 6W7QleH3WdMq0QGFtttP66Ds5bwWm9eFdhdk410FobqWsVFxgS9/vL8RhjMarQuiUzMY aPSA== X-Gm-Message-State: AO0yUKXM7Dzyg/Hd4s5/oIT/esjEk3do/CSYLFUe32w439wB24c9q80+ 71R5Msv/VSGMuXW694hkM7V+Ow== X-Google-Smtp-Source: AK7set/dVPeod/Y5g0V3qlSktTgR9klJIxxKsNCRFhi4Ez6EwJM3jqCnFflSDtAVMVV/pnpkGr/YIQ== X-Received: by 2002:ac2:4425:0:b0:4db:3e7e:51d3 with SMTP id w5-20020ac24425000000b004db3e7e51d3mr535365lfl.55.1677584029457; Tue, 28 Feb 2023 03:33:49 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id h20-20020ac25974000000b004dd0bbc89a1sm1288472lfp.244.2023.02.28.03.33.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Feb 2023 03:33:49 -0800 (PST) From: Dmitry Baryshkov To: David Airlie , Daniel Vetter , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin , Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten Cc: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= , dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org Subject: [PATCH 07/10] drm/display/dsc: include the rest of pre-SCR parameters Date: Tue, 28 Feb 2023 13:33:39 +0200 Message-Id: <20230228113342.2051425-8-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230228113342.2051425-1-dmitry.baryshkov@linaro.org> References: <20230228113342.2051425-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org DSC model contains pre-SCR RC parameters for other bpp/bpc combinations, include them here for completeness. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/display/drm_dsc_helper.c | 72 ++++++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c index 51794b40526a..1612536014ea 100644 --- a/drivers/gpu/drm/display/drm_dsc_helper.c +++ b/drivers/gpu/drm/display/drm_dsc_helper.c @@ -327,6 +327,16 @@ struct rc_parameters_data { #define DSC_BPP(bpp) ((bpp) << 4) static const struct rc_parameters_data rc_parameters_pre_scr[] = { +{ DSC_BPP(6), 8, + /* 6BPP/8BPC */ + { 683, 15, 6144, 3, 13, 11, 11, { + { 0, 2, 0 }, { 1, 4, -2 }, { 3, 6, -2 }, { 4, 6, -4 }, + { 5, 7, -6 }, { 5, 7, -6 }, { 6, 7, -6 }, { 6, 8, -8 }, + { 7, 9, -8 }, { 8, 10, -10 }, { 9, 11, -10 }, { 10, 12, -12 }, + { 10, 13, -12 }, { 12, 14, -12 }, { 15, 15, -12 } + } + } +}, { DSC_BPP(8), 8, /* 8BPP/8BPC */ { 512, 12, 6144, 3, 12, 11, 11, { @@ -362,6 +372,37 @@ static const struct rc_parameters_data rc_parameters_pre_scr[] = { } } }, +{ DSC_BPP(10), 8, + /* 10BPP/8BPC */ + { 410, 12, 5632, 3, 12, 11, 11, { + { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 }, + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 }, + { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 11, -10 }, + { 5, 12, -12 }, { 7, 13, -12 }, { 13, 15, -12 } + } + } +}, +{ DSC_BPP(10), 10, + /* 10BPP/10BPC */ + { 410, 12, 5632, 7, 16, 15, 15, { + { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 }, + { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 }, + { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 15, -10 }, + { 9, 16, -12 }, { 11, 17, -12 }, { 17, 19, -12 } + } + } +}, +{ DSC_BPP(10), 12, + /* 10BPP/12BPC */ + { 410, 12, 5632, 11, 20, 19, 19, { + { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 }, + { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 }, + { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 }, + { 13, 19, -10 }, { 13, 20, -12 }, { 15, 21, -12 }, + { 21, 23, -12 } + } + } +}, { DSC_BPP(12), 8, /* 12BPP/8BPC */ { 341, 15, 2048, 3, 12, 11, 11, { @@ -393,6 +434,37 @@ static const struct rc_parameters_data rc_parameters_pre_scr[] = { } } }, +{ DSC_BPP(15), 8, + /* 15BPP/8BPC */ + { 273, 15, 2048, 3, 12, 11, 11, { + { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 }, + { 1, 2, 2 }, { 1, 3, 0 }, { 1, 4, -2 }, { 2, 4, -4 }, + { 3, 4, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 5, 7, -10 }, + { 5, 8, -12 }, { 7, 13, -12 }, { 13, 15, -12 } + } + } +}, +{ DSC_BPP(15), 10, + /* 15BPP/10BPC */ + { 273, 15, 2048, 7, 16, 15, 15, { + { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 }, + { 5, 6, 2 }, { 5, 7, 0 }, { 5, 8, -2 }, { 6, 8, -4 }, + { 7, 8, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 9, 11, -10 }, + { 9, 12, -12 }, { 11, 17, -12 }, { 17, 19, -12 } + } + } +}, +{ DSC_BPP(15), 12, + /* 15BPP/12BPC */ + { 273, 15, 2048, 11, 20, 19, 19, { + { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 }, + { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 }, + { 11, 12, -6 }, { 11, 13, -8 }, { 12, 14, -10 }, + { 13, 15, -10 }, { 13, 16, -12 }, { 15, 21, -12 }, + { 21, 23, -12 } + } + } +}, { /* sentinel */ } }; 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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id h20-20020ac25974000000b004dd0bbc89a1sm1288472lfp.244.2023.02.28.03.33.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Feb 2023 03:33:51 -0800 (PST) From: Dmitry Baryshkov To: David Airlie , Daniel Vetter , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin , Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten Cc: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= , dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org Subject: [PATCH 10/10] drm/msm/dsi: use new helpers for DSC setup Date: Tue, 28 Feb 2023 13:33:42 +0200 Message-Id: <20230228113342.2051425-11-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230228113342.2051425-1-dmitry.baryshkov@linaro.org> References: <20230228113342.2051425-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Use new DRM DSC helpers to setup DSI DSC configuration. The initial_scale_value needs to be adjusted according to the standard, but this is a separate change. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dsi/dsi_host.c | 61 ++++-------------------------- 1 file changed, 8 insertions(+), 53 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index 18fa30e1e858..dda989727921 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -1735,28 +1735,9 @@ static int dsi_host_parse_lane_data(struct msm_dsi_host *msm_host, return -EINVAL; } -static u32 dsi_dsc_rc_buf_thresh[DSC_NUM_BUF_RANGES - 1] = { - 0x0e, 0x1c, 0x2a, 0x38, 0x46, 0x54, 0x62, - 0x69, 0x70, 0x77, 0x79, 0x7b, 0x7d, 0x7e -}; - -/* only 8bpc, 8bpp added */ -static char min_qp[DSC_NUM_BUF_RANGES] = { - 0, 0, 1, 1, 3, 3, 3, 3, 3, 3, 5, 5, 5, 7, 13 -}; - -static char max_qp[DSC_NUM_BUF_RANGES] = { - 4, 4, 5, 6, 7, 7, 7, 8, 9, 10, 11, 12, 13, 13, 15 -}; - -static char bpg_offset[DSC_NUM_BUF_RANGES] = { - 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12 -}; - static int dsi_populate_dsc_params(struct msm_dsi_host *msm_host, struct drm_dsc_config *dsc) { - int i; - u16 bpp = dsc->bits_per_pixel >> 4; + int ret; if (dsc->bits_per_pixel & 0xf) { DRM_DEV_ERROR(&msm_host->pdev->dev, "DSI does not support fractional bits_per_pixel\n"); @@ -1768,49 +1749,23 @@ static int dsi_populate_dsc_params(struct msm_dsi_host *msm_host, struct drm_dsc return -EOPNOTSUPP; } - dsc->rc_model_size = 8192; - dsc->first_line_bpg_offset = 12; - dsc->rc_edge_factor = 6; - dsc->rc_tgt_offset_high = 3; - dsc->rc_tgt_offset_low = 3; dsc->simple_422 = 0; dsc->convert_rgb = 1; dsc->vbr_enable = 0; - /* handle only bpp = bpc = 8 */ - for (i = 0; i < DSC_NUM_BUF_RANGES - 1 ; i++) - dsc->rc_buf_thresh[i] = dsi_dsc_rc_buf_thresh[i]; + drm_dsc_set_const_params(dsc); + drm_dsc_set_rc_buf_thresh(dsc); - for (i = 0; i < DSC_NUM_BUF_RANGES; i++) { - dsc->rc_range_params[i].range_min_qp = min_qp[i]; - dsc->rc_range_params[i].range_max_qp = max_qp[i]; - /* - * Range BPG Offset contains two's-complement signed values that fill - * 8 bits, yet the registers and DCS PPS field are only 6 bits wide. - */ - dsc->rc_range_params[i].range_bpg_offset = bpg_offset[i] & DSC_RANGE_BPG_OFFSET_MASK; + /* handle only bpp = bpc = 8, pre-SCR panels */ + ret = drm_dsc_setup_rc_params(dsc, DRM_DSC_1_1_PRE_SCR); + if (ret) { + DRM_DEV_ERROR(&msm_host->pdev->dev, "could not find DSC RC parameters\n"); + return ret; } - dsc->initial_offset = 6144; /* Not bpp 12 */ - if (bpp != 8) - dsc->initial_offset = 2048; /* bpp = 12 */ - - if (dsc->bits_per_component <= 10) - dsc->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC; - else - dsc->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC; - - dsc->initial_xmit_delay = 512; dsc->initial_scale_value = 32; - dsc->first_line_bpg_offset = 12; dsc->line_buf_depth = dsc->bits_per_component + 1; - /* bpc 8 */ - dsc->flatness_min_qp = 3; - dsc->flatness_max_qp = 12; - dsc->rc_quant_incr_limit0 = 11; - dsc->rc_quant_incr_limit1 = 11; - return drm_dsc_compute_rc_parameters(dsc); }