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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id p19-20020a1709028a9300b0019cec7d88c3sm5192651plo.236.2023.02.27.16.37.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Feb 2023 16:37:17 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 1/3] target/arm: Avoid splitting Zregs across lines in dump Date: Mon, 27 Feb 2023 14:37:11 -1000 Message-Id: <20230228003713.861168-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230228003713.861168-1-richard.henderson@linaro.org> References: <20230228003713.861168-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Allow the line length to extend to 548 columns. While annoyingly wide, it's still less confusing than the continuations we print. Also, the default VL used by Linux (and max for A64FX) uses only 140 columns. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.c | 36 ++++++++++++++---------------------- 1 file changed, 14 insertions(+), 22 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 5182ed0c91..f1f454e7a0 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -953,7 +953,7 @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; uint32_t psr = pstate_read(env); - int i; + int i, j; int el = arm_current_el(env); const char *ns_status; bool sve; @@ -1012,7 +1012,7 @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) } if (sve) { - int j, zcr_len = sve_vqm1_for_el(env, el); + int zcr_len = sve_vqm1_for_el(env, el); for (i = 0; i <= FFR_PRED_NUM; i++) { bool eol; @@ -1052,32 +1052,24 @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) } } - for (i = 0; i < 32; i++) { - if (zcr_len == 0) { + if (zcr_len == 0) { + /* + * With vl=16, there are only 37 columns per register, + * so output two registers per line. + */ + for (i = 0; i < 32; i++) { qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s", i, env->vfp.zregs[i].d[1], env->vfp.zregs[i].d[0], i & 1 ? "\n" : " "); - } else if (zcr_len == 1) { - qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 - ":%016" PRIx64 ":%016" PRIx64 "\n", - i, env->vfp.zregs[i].d[3], env->vfp.zregs[i].d[2], - env->vfp.zregs[i].d[1], env->vfp.zregs[i].d[0]); - } else { + } + } else { + for (i = 0; i < 32; i++) { + qemu_fprintf(f, "Z%02d=", i); for (j = zcr_len; j >= 0; j--) { - bool odd = (zcr_len - j) % 2 != 0; - if (j == zcr_len) { - qemu_fprintf(f, "Z%02d[%x-%x]=", i, j, j - 1); - } else if (!odd) { - if (j > 0) { - qemu_fprintf(f, " [%x-%x]=", j, j - 1); - } else { - qemu_fprintf(f, " [%x]=", j); - } - } qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s", env->vfp.zregs[i].d[j * 2 + 1], - env->vfp.zregs[i].d[j * 2], - odd || j == 0 ? "\n" : ":"); + env->vfp.zregs[i].d[j * 2 + 0], + j ? ":" : "\n"); } } } From patchwork Tue Feb 28 00:37:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 657460 Delivered-To: patch@linaro.org Received: by 2002:a05:6504:1b90:b0:222:2e2e:b2c3 with SMTP id e16csp3395055lty; Mon, 27 Feb 2023 16:37:52 -0800 (PST) X-Google-Smtp-Source: AK7set9BqG/gZw4/IPEfRdrwLXJLRaa78G78dwfTW7Eo4+j1WBnnf56gQBi7a13+4FA8bLBguXtN X-Received: by 2002:a05:622a:14:b0:3b9:e4cf:ce2d with SMTP id x20-20020a05622a001400b003b9e4cfce2dmr2538963qtw.16.1677544672249; Mon, 27 Feb 2023 16:37:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677544672; cv=none; d=google.com; s=arc-20160816; b=dwQVcAafwr0ZtOJ6T9Pf7RTyJHCKyupyao243sP7p/m1OkzOvhh5F59N1K9IEEIpJM ekB2+hHVj+NY/hyjZD3HMPVdK6OD9NxJy/2FKkapy4OHmzhbkdrykgQxF8dvbXp7l4OI sJg9Aa53BuqnLTc70INfl2dfn1zA7WCAD5zzzBDpbPP+o4Qo24Wv/PL3rGD73gfUKx6P ophHEPAd7nq1QeYsFVMgCZ036lQgrRG2E8sjEnR5/MLmGVnmvx4hRGIOtrQR8lp83wO4 tkAcodb4TSukrai5Me6TAEKpuNsNGc/uHoFuxmSlPu3v+Ywf1R/aAedGeajbjCNmQ+RS Rqpw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=ySb1mvjSXZ66e2yK3BcHGU3IqS6n9iUd4Z/aLHtfxkk=; b=g8iqmNvt+qCb+Rpl6ITX6EoApGGclICXa6M33J7vnatq7KYsrO1WWkZ2izI5s6PQ9S SoMK1GItK9q/mAtxXgMSvL00T4hmMINqZsBb+mzdaKgR3dLD7tJLZO19OQpMF/o7o1EX NdJhKWTkeQHdSFrCfw/F5fXi3Y8e3SOVYqsikprLcvSO/XjueDiFaG4vx6RGAr6rpHQP 5qO5n6ZtwGCMA3tHTRl6kPSQxpsgTINlqRzyaWvNzcvQJXfebJ2ZZnq3i2Hcn54jehVQ NJsihQMB5woRhhEb00S52MpWbaQed3VdjMlcRnCiTvGYl1pzVX6rPFQcgKwBzgSyZ4SP Kt3Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=YavU0Zk6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id p19-20020a1709028a9300b0019cec7d88c3sm5192651plo.236.2023.02.27.16.37.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Feb 2023 16:37:18 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 2/3] target/arm: Dump ZA[] when active Date: Mon, 27 Feb 2023 14:37:12 -1000 Message-Id: <20230228003713.861168-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230228003713.861168-1-richard.henderson@linaro.org> References: <20230228003713.861168-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Always print each matrix row whole, one per line, so that we get the entire matrix in the proper shape. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index f1f454e7a0..0e54e19b05 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1080,6 +1080,24 @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) i, q[1], q[0], (i & 1 ? "\n" : " ")); } } + + if (cpu_isar_feature(aa64_sme, cpu) && + FIELD_EX64(env->svcr, SVCR, ZA) && + sme_exception_el(env, el) == 0) { + int zcr_len = sve_vqm1_for_el_sm(env, el, true); + int svl = (zcr_len + 1) * 16; + int svl_lg10 = svl < 100 ? 2 : 3; + + for (i = 0; i < svl; i++) { + qemu_fprintf(f, "ZA[%0*d]=", svl_lg10, i); + for (j = zcr_len; j >= 0; --j) { + qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%c", + env->zarray[i].d[2 * j + 1], + env->zarray[i].d[2 * j], + j ? ':' : '\n'); + } + } + } } #else From patchwork Tue Feb 28 00:37:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 657463 Delivered-To: patch@linaro.org Received: by 2002:a05:6504:1b90:b0:222:2e2e:b2c3 with SMTP id e16csp3395207lty; Mon, 27 Feb 2023 16:38:15 -0800 (PST) X-Google-Smtp-Source: AK7set+QvT6Wej+FhD2C9pzwl7IEpMnvAn102lfhUoSpwUTOVERbVkq9mbDp+FbfiTGjLWYITg2q X-Received: by 2002:a05:6214:e6b:b0:570:bf45:d6f7 with SMTP id jz11-20020a0562140e6b00b00570bf45d6f7mr2091488qvb.45.1677544695523; Mon, 27 Feb 2023 16:38:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677544695; cv=none; d=google.com; s=arc-20160816; b=KsBbJdFQ0v4XFXqDAJLXku8c2hXtklVNifVQ9LpXQ77y5zvqv76IEwBHxXSpiG8oMo GVdlaJ9cSz1Y+lmqMhV/55nFeLkIfc1aDkQo+IcygLWxxTwjfFOyGgRs+2ohos/n25E+ G7yuauFUqSN+4Ju0oOjDgygpSOVhAd+nt/jRPQuFk8m4efMituNLYCtGYrSD4ZWNsGHT RxQixaz0EcvxCE7FnPm4H76FP8aC0i1IovuqELaa8Iy+gOFHbjgB34TtsYKhY3SJYLsv /vwKu/kvY3Bt/nbwkIKKEzeM6d0I2q9vwFumsd3cgken+xrjyhQIkh+m3p4JOD+ItwrD NZcg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=hB69UJs6DFGk5NVC6xvA04dBA1lHgG7I+VN9AFpQB6Q=; b=NkASgZVqjdkbie+FFgDFow+ThAgFGJda4I+PIfnJsySwkKFRiuD6ZtocD8uZ9IRFhA MPfBMWviYsUawWdmd0JSBNHoNBxX3HU0YAeLTm3v8Z1YKZHTMp6cZDFQ+8U2afdjqA60 Cm493SJMMCn0jFdIvSkKhVbd++tmDMx2FSIikAufzhbeQsvx6ESZK0+sWAPOtVD58m5P WZr16TMfv3qeno1d3BRZbUIBaC8CZ60zB4ThnKnkncedK2Nc+wd7nHmG5DeLNLCy/d9p XY3KDGbCutQLSRMdnAzSBu9bpdD1IW0tz2POy2SkP9xFJT8m4ch+C1IBHmrxIc02p751 +Auw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=M4nHd6R8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id p19-20020a1709028a9300b0019cec7d88c3sm5192651plo.236.2023.02.27.16.37.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Feb 2023 16:37:20 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 3/3] target/arm: Support reading ZA[] from gdbstub Date: Mon, 27 Feb 2023 14:37:13 -1000 Message-Id: <20230228003713.861168-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230228003713.861168-1-richard.henderson@linaro.org> References: <20230228003713.861168-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1043; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1043.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Mirror the existing support for SVE. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 1 + target/arm/internals.h | 3 ++ target/arm/gdbstub.c | 8 ++++ target/arm/gdbstub64.c | 88 ++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 100 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 6e97a256fb..9971280577 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -869,6 +869,7 @@ struct ArchCPU { DynamicGDBXMLInfo dyn_sysreg_xml; DynamicGDBXMLInfo dyn_svereg_xml; + DynamicGDBXMLInfo dyn_zareg_xml; DynamicGDBXMLInfo dyn_m_systemreg_xml; DynamicGDBXMLInfo dyn_m_secextreg_xml; diff --git a/target/arm/internals.h b/target/arm/internals.h index a03748aa10..a27e5b3f28 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1343,12 +1343,15 @@ static inline uint64_t pmu_counter_mask(CPUARMState *env) #ifdef TARGET_AARCH64 int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg); +int arm_gen_dynamic_zareg_xml(CPUState *cpu, int base_reg); int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg); int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg); int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg); int aarch64_gdb_set_fpu_reg(CPUARMState *env, uint8_t *buf, int reg); int aarch64_gdb_get_pauth_reg(CPUARMState *env, GByteArray *buf, int reg); int aarch64_gdb_set_pauth_reg(CPUARMState *env, uint8_t *buf, int reg); +int aarch64_gdb_get_za_reg(CPUARMState *env, GByteArray *buf, int reg); +int aarch64_gdb_set_za_reg(CPUARMState *env, uint8_t *buf, int reg); void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp); void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp); void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp); diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index 3f799f5d05..60a9ade732 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -488,6 +488,8 @@ const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) return cpu->dyn_sysreg_xml.desc; } else if (strcmp(xmlname, "sve-registers.xml") == 0) { return cpu->dyn_svereg_xml.desc; + } else if (strcmp(xmlname, "za-registers.xml") == 0) { + return cpu->dyn_zareg_xml.desc; } else if (strcmp(xmlname, "arm-m-system.xml") == 0) { return cpu->dyn_m_systemreg_xml.desc; #ifndef CONFIG_USER_ONLY @@ -524,6 +526,12 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) aarch64_gdb_set_pauth_reg, 4, "aarch64-pauth.xml", 0); } + if (cpu_isar_feature(aa64_sme, cpu)) { + int nreg = arm_gen_dynamic_zareg_xml(cs, cs->gdb_num_regs); + gdb_register_coprocessor(cs, aarch64_gdb_get_za_reg, + aarch64_gdb_set_za_reg, nreg, + "za-registers.xml", 0); + } #endif } else { if (arm_feature(env, ARM_FEATURE_NEON)) { diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index 3bee892fb7..9210d12c4e 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -244,6 +244,61 @@ int aarch64_gdb_set_pauth_reg(CPUARMState *env, uint8_t *buf, int reg) return 0; } +static int max_svq(ARMCPU *cpu) +{ + return 32 - clz32(cpu->sme_vq.map); +} + +int aarch64_gdb_get_za_reg(CPUARMState *env, GByteArray *buf, int reg) +{ + ARMCPU *cpu = env_archcpu(env); + int max_vq = max_svq(cpu); + int cur_vq = EX_TBFLAG_A64(env->hflags, SVL) + 1; + int i; + + if (reg >= max_vq * 16) { + return 0; + } + + /* If ZA is unset, or reg out of range, the contents are zero. */ + if (FIELD_EX64(env->svcr, SVCR, ZA) && reg < cur_vq * 16) { + for (i = 0; i < cur_vq; i++) { + gdb_get_reg128(buf, env->zarray[reg].d[i * 2 + 1], + env->zarray[reg].d[i * 2]); + } + } else { + cur_vq = 0; + } + + for (i = cur_vq; i < max_vq; i++) { + gdb_get_reg128(buf, 0, 0); + } + + return max_vq * 16; +} + +int aarch64_gdb_set_za_reg(CPUARMState *env, uint8_t *buf, int reg) +{ + ARMCPU *cpu = env_archcpu(env); + uint64_t *p = (uint64_t *) buf; + int max_vq = max_svq(cpu); + int cur_vq = EX_TBFLAG_A64(env->hflags, SVL) + 1; + int i; + + if (reg >= max_vq * 16) { + return 0; + } + + /* If ZA is unset, or reg out of range, the contents are zero. */ + if (FIELD_EX64(env->svcr, SVCR, ZA) && reg < cur_vq * 16) { + for (i = 0; i < cur_vq; i++) { + env->zarray[reg].d[i * 2 + 1] = *p++; + env->zarray[reg].d[i * 2 + 0] = *p++; + } + } + return max_vq * 16; +} + static void output_vector_union_type(GString *s, int reg_width, const char *name) { @@ -376,3 +431,36 @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg) info->num = base_reg - orig_base_reg; return info->num; } + +/* + * Generate the xml for SME, with matrix size set to the maximum + * for the cpu. Returns the number of registers generated. + */ +int arm_gen_dynamic_zareg_xml(CPUState *cs, int base_reg) +{ + ARMCPU *cpu = ARM_CPU(cs); + GString *s = g_string_new(NULL); + int vq = max_svq(cpu); + int row_count = vq * 16; + int row_width = vq * 128; + int i; + + g_string_printf(s, ""); + g_string_append_printf(s, ""); + g_string_append_printf(s, ""); + + output_vector_union_type(s, row_width, "zav"); + + for (i = 0; i < row_count; i++) { + g_string_append_printf(s, + "", + i, row_width, base_reg + i); + } + + g_string_append_printf(s, ""); + + cpu->dyn_zareg_xml.num = row_count; + cpu->dyn_zareg_xml.desc = g_string_free(s, false); + return row_count; +}