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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id c2-20020a6566c2000000b00503000f0492sm4441050pgw.14.2023.02.27.14.58.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Feb 2023 14:58:36 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH for-8.0 v4 1/4] target/arm: Handle m-profile in arm_is_secure Date: Mon, 27 Feb 2023 12:58:29 -1000 Message-Id: <20230227225832.816605-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227225832.816605-1-richard.henderson@linaro.org> References: <20230227225832.816605-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::644; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x644.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1421 Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 12b1082537..7a2f804aeb 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2426,6 +2426,9 @@ static inline bool arm_is_el3_or_mon(CPUARMState *env) /* Return true if the processor is in secure state */ static inline bool arm_is_secure(CPUARMState *env) { + if (arm_feature(env, ARM_FEATURE_M)) { + return env->v7m.secure; + } if (arm_is_el3_or_mon(env)) { return true; } From patchwork Mon Feb 27 22:58:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 657133 Delivered-To: patch@linaro.org Received: by 2002:adf:a3c6:0:0:0:0:0 with SMTP id m6csp2614747wrb; Mon, 27 Feb 2023 14:59:46 -0800 (PST) X-Google-Smtp-Source: AK7set957jo7LDPR76kEYoN8OHfKmY0KnADFR/4crN4g8VqBjnMmVd9PD+8ahSk8UbQWN0lb0OEP X-Received: by 2002:ad4:5ca2:0:b0:56e:c0df:8492 with SMTP id q2-20020ad45ca2000000b0056ec0df8492mr2149740qvh.31.1677538785821; Mon, 27 Feb 2023 14:59:45 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677538785; cv=none; d=google.com; s=arc-20160816; b=CrUSfFoOqdVzLQNIjko9kHmp0DtBTve98pvdHitxi9YNxnVBiqqmYT5I1ENsMAMSck mJmwqwj091Q7PnYFB/MH0iZp0IDF15OfWNn6m8owSz1y5uuxmGIrPI+u404OJseDAcHa uvCMWiBAjqTA49AhrnCExLBQI7yKPJ/h2UT071G+NhhYXY/LnqCVxToK9AKjpitk/LzB R7VCx2D5zeIGdmlwaBkVr/n6a6AGHklM4yuD+D57yWMpa6U6IizT9Q88nd+nrXTIjPXY 1eUmTN9rYwG6AdDgzMZlZvlDzMrIbIM1R1Jco64jcwipCClNP1k0SqLkBcwtMEelH1rG 8vyw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=J33WqVqAxFla+dpmD2MbLyNB18FeHqj+AFmY8xo8oOg=; b=NV2WVRlTLSkC3YHT+fjlf4KQ/plG9Lp1e7vQbCmhS6ti7IHTNh6fvCfGDxAfPAgTbR WqLS24lXGZAZS0ou5odIB8es4ZmZF0fE1XQeyWgF51BtEbiKatDOAbBb7GndRm6Onvtj f82ej2SyUENu2ZWCDXQh+0l7IwAFZAn5ddTNzQAeen2LCOi+xiIsimtImvukXJVTX1AV zENU0CdnoL9xla+Vv5bYAKpfJNQUie+hpKZJIxympibynM6d1EmCc1oJmA5gcqHFZ3cl ZWj1u7wJyvYNz9qsE35PTnkxu+pJ46jSGuHXMalHPSkk6D+mifhAU1jaesu5Cj2YG6DZ K34Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Q9Ddh4nA; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id c2-20020a6566c2000000b00503000f0492sm4441050pgw.14.2023.02.27.14.58.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Feb 2023 14:58:38 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH for-8.0 v4 2/4] target/arm: Stub arm_hcr_el2_eff for m-profile Date: Mon, 27 Feb 2023 12:58:30 -1000 Message-Id: <20230227225832.816605-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227225832.816605-1-richard.henderson@linaro.org> References: <20230227225832.816605-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org M-profile doesn't have HCR_EL2. While we could test features before each call, zero is a generally safe return value to disable the code in the caller. This test is required to avoid an assert in arm_is_secure_below_el3. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 14af7ba095..bd12efd392 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5788,6 +5788,9 @@ uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, bool secure) uint64_t arm_hcr_el2_eff(CPUARMState *env) { + if (arm_feature(env, ARM_FEATURE_M)) { + return 0; + } return arm_hcr_el2_eff_secstate(env, arm_is_secure_below_el3(env)); } From patchwork Mon Feb 27 22:58:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 657135 Delivered-To: patch@linaro.org Received: by 2002:adf:a3c6:0:0:0:0:0 with SMTP id m6csp2614860wrb; Mon, 27 Feb 2023 15:00:01 -0800 (PST) X-Google-Smtp-Source: AK7set+2TOqDE1BUsLyIdp8qlhH58mkCpm06ettJE89h4009eqs2wROv5fxhKF2IAKuJNA/OaR+d X-Received: by 2002:ac8:5acb:0:b0:3a6:8f7c:5936 with SMTP id d11-20020ac85acb000000b003a68f7c5936mr1717161qtd.25.1677538801072; Mon, 27 Feb 2023 15:00:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677538801; cv=none; d=google.com; s=arc-20160816; b=whsKCjg5pZ5puVVu23QrWn4HBhIxeDVw66dQX8u+8GJVzUnimFIPnJsYMpmGqnL541 YvQFJLbJnUm4VZLoIcwqWYf635k83FTMmYM0yjLuxwVdQ9f1HuOxsDicBAD+ZXQ7BuXX o01+wH9XhbiU5fs//8Qnh4zELCIocCjcdbg887HC2NFaxsxuSkal7ZNnx5VOe60XHOVK RMRROujuaGkRkiYr4pPSzAdioRiQnMSGF6zZIrnp5Twx6RmT+muRnptyV/5rmIyCuHLX olgMF31kOmMOrPiLFWD5IhBOTpPEpPw/+2Loxy//CNMK2GEY9w9CAmtcQVCa6TOoyEJq zymw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=pUw/Q9WV6uI2o5+wRzg6/DeRVdVBmeUlUspfEoqm0lE=; b=KqzBIagpMZVrQZsPhwU7Sn6JnLq3ics6sNl8BnaiJ/ljOKtfQu87SmPfGtl5r5yzA3 9AoDDTU0DQQYF2w6oEgkLdJhecH0wg6V3+bmm2aAxM2j/0GX4InNzOCG+VrYGxTwNtdQ ad8E2nbS7Y3zQrhz85+j9Tif/nYwkfRLI5L+HTfVFg81Xen1wPtONssvMJFPf8tm3/bb bL2UjsDhEltfO4KtgHW140G7HfuBDEIsynQcwgQqiL67HZmw9gkY7ONewYKXRUnk784Q uw4QK5qrGYuxFlG9qc1iFH9aqaIGOCTpuMEfDjcSkT8uYKD6n2SUULT5LCfzH4zUtr1z X3kA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vECubhlK; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id c2-20020a6566c2000000b00503000f0492sm4441050pgw.14.2023.02.27.14.58.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Feb 2023 14:58:40 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH for-8.0 v4 3/4] target/arm: Diagnose incorrect usage of arm_is_secure subroutines Date: Mon, 27 Feb 2023 12:58:31 -1000 Message-Id: <20230227225832.816605-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227225832.816605-1-richard.henderson@linaro.org> References: <20230227225832.816605-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In several places we use arm_is_secure_below_el3 and arm_is_el3_or_mon separately from arm_is_secure. These functions make no sense for m-profile, and would indicate prior incorrect feature testing. Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/arm/cpu.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 7a2f804aeb..cb4e405f04 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2389,7 +2389,8 @@ static inline int arm_feature(CPUARMState *env, int feature) void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp); #if !defined(CONFIG_USER_ONLY) -/* Return true if exception levels below EL3 are in secure state, +/* + * Return true if exception levels below EL3 are in secure state, * or would be following an exception return to that level. * Unlike arm_is_secure() (which is always a question about the * _current_ state of the CPU) this doesn't care about the current @@ -2397,6 +2398,7 @@ void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp); */ static inline bool arm_is_secure_below_el3(CPUARMState *env) { + assert(!arm_feature(env, ARM_FEATURE_M)); if (arm_feature(env, ARM_FEATURE_EL3)) { return !(env->cp15.scr_el3 & SCR_NS); } else { @@ -2410,6 +2412,7 @@ static inline bool arm_is_secure_below_el3(CPUARMState *env) /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ static inline bool arm_is_el3_or_mon(CPUARMState *env) { + assert(!arm_feature(env, ARM_FEATURE_M)); if (arm_feature(env, ARM_FEATURE_EL3)) { if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { /* CPU currently in AArch64 state and EL3 */ From patchwork Mon Feb 27 22:58:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 657136 Delivered-To: patch@linaro.org Received: by 2002:adf:a3c6:0:0:0:0:0 with SMTP id m6csp2614938wrb; Mon, 27 Feb 2023 15:00:12 -0800 (PST) X-Google-Smtp-Source: AK7set/iIB93+EKnyqroamvKDeljNqDVNBGs0OGN7rp7xsvaQveUHZybp4vTmCuisNA08o0JZDWG X-Received: by 2002:ac8:5885:0:b0:3bf:c355:9ad4 with SMTP id t5-20020ac85885000000b003bfc3559ad4mr1868581qta.34.1677538811819; Mon, 27 Feb 2023 15:00:11 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677538811; cv=none; d=google.com; s=arc-20160816; b=dhP1NfhfhUGFK7f4lb5jH5i9Mx9NPBMJgutJZHbsUv3g/6UA5dQwK7o6hQkN1ymiOQ M1yUD3Xm/hNq+/K5RCHJnahMji+ZCPcKmutiNP+W4Map685wOby4oPdm/cNdOg4rH62W 5xfHXifoieYquczODyPsvVkYBpX0YwWhr4Qxgl2JHYbtfoQTs8i5znl9u2aTKs1PyuBm VzKQFOvDaI+4d/pUi37Pg4w+SJolEMH8tnEbQcM1iWr8CUz+WcVmP+4qfwQFLrYL3QuS J9QsjfECnXD5fQW0pNWE22lojQHOJ5876Ib9lYOyrUaQ3VR/A2GPu9afP4xJQlkPouWq T0xw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=6o3dC89BjnRs5h0SAtcviZdfOy/i5kYTa1NGTzWCcT4=; b=J5K88IFSLvOaY0JJzcZqMW9Fb8hbCyPfE0DDW+5TNRIPwNRzoyC90trczNryAhoiFU iO1/ul3uIRn9ob9Tj8whhCr+j3bqaNLoKaBLqNal5sT9NeA4G33hFRB3oQPuzLuHJCyO qx6Dn17bueetxClMLG6B0tP2TX4wLla7oGr3s2H1c6zPL5HbI8ns8jCkRlTe2zf45Acd FkIUZ7OwXZLZcYcBfDFkNDCoxojaGztC3jX720JURemTMQETeTwUs/XP+zM9fwzk/5LH mSu13a6dOfq+jhjNEgJv5U8klvmeZeBCXe1fXofohvSn+A/hWCA/I7AwByznNMjy9Z/6 RLQQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=C5cPbyWf; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id c2-20020a6566c2000000b00503000f0492sm4441050pgw.14.2023.02.27.14.58.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Feb 2023 14:58:41 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH for-8.0 v4 4/4] target/arm: Rewrite check_s2_mmu_setup Date: Mon, 27 Feb 2023 12:58:32 -1000 Message-Id: <20230227225832.816605-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227225832.816605-1-richard.henderson@linaro.org> References: <20230227225832.816605-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::642; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x642.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Integrate neighboring code from get_phys_addr_lpae which computed starting level, as it is easier to validate when doing both at the same time. Mirror the checks at the start of AArch{64,32}.S2Walk, especially S2InvalidSL and S2InconsistentSL. This reverts 49ba115bb74, which was incorrect -- there is nothing in the ARM pseudocode that depends on TxSZ, i.e. outputsize; the pseudocode is consistent in referencing PAMax. Fixes: 49ba115bb74 ("target/arm: Pass outputsize down to check_s2_mmu_setup") Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/ptw.c | 173 ++++++++++++++++++++++++++--------------------- 1 file changed, 97 insertions(+), 76 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index be0cc6bc15..89cc7e2aff 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1081,70 +1081,119 @@ static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va, * check_s2_mmu_setup * @cpu: ARMCPU * @is_aa64: True if the translation regime is in AArch64 state - * @startlevel: Suggested starting level - * @inputsize: Bitsize of IPAs + * @tcr: VTCR_EL2 or VSTCR_EL2 + * @ds: Effective value of TCR.DS. + * @iasize: Bitsize of IPAs * @stride: Page-table stride (See the ARM ARM) * - * Returns true if the suggested S2 translation parameters are OK and - * false otherwise. + * Decode the starting level of the S2 lookup, returning INT_MIN if + * the configuration is invalid. */ -static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level, - int inputsize, int stride, int outputsize) +static int check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, uint64_t tcr, + bool ds, int iasize, int stride) { - const int grainsize = stride + 3; - int startsizecheck; - - /* - * Negative levels are usually not allowed... - * Except for FEAT_LPA2, 4k page table, 52-bit address space, which - * begins with level -1. Note that previous feature tests will have - * eliminated this combination if it is not enabled. - */ - if (level < (inputsize == 52 && stride == 9 ? -1 : 0)) { - return false; - } - - startsizecheck = inputsize - ((3 - level) * stride + grainsize); - if (startsizecheck < 1 || startsizecheck > stride + 4) { - return false; - } + int sl0, sl2, startlevel, granulebits, levels; + int s1_min_iasize, s1_max_iasize; + sl0 = extract32(tcr, 6, 2); if (is_aa64) { + /* + * AArch64.S2InvalidTxSZ: While we checked tsz_oob near the top of + * get_phys_addr_lpae, that used aa64_va_parameters which apply + * to aarch64. If Stage1 is aarch32, the min_txsz is larger. + * See AArch64.S2MinTxSZ, where min_tsz is 24, translated to + * inputsize is 64 - 24 = 40. + */ + if (iasize < 40 && !arm_el_is_aa64(&cpu->env, 1)) { + goto fail; + } + + /* + * AArch64.S2InvalidSL: Interpretation of SL depends on the page size, + * so interleave AArch64.S2StartLevel. + */ switch (stride) { - case 13: /* 64KB Pages. */ - if (level == 0 || (level == 1 && outputsize <= 42)) { - return false; + case 9: /* 4KB */ + /* SL2 is RES0 unless DS=1 & 4KB granule. */ + sl2 = extract64(tcr, 33, 1); + if (ds && sl2) { + if (sl0 != 0) { + goto fail; + } + startlevel = -1; + } else { + startlevel = 2 - sl0; + switch (sl0) { + case 2: + if (arm_pamax(cpu) < 44) { + goto fail; + } + break; + case 3: + if (!cpu_isar_feature(aa64_st, cpu)) { + goto fail; + } + startlevel = 3; + break; + } } break; - case 11: /* 16KB Pages. */ - if (level == 0 || (level == 1 && outputsize <= 40)) { - return false; + case 11: /* 16KB */ + switch (sl0) { + case 2: + if (arm_pamax(cpu) < 42) { + goto fail; + } + break; + case 3: + if (!ds) { + goto fail; + } + break; } + startlevel = 3 - sl0; break; - case 9: /* 4KB Pages. */ - if (level == 0 && outputsize <= 42) { - return false; + case 13: /* 64KB */ + switch (sl0) { + case 2: + if (arm_pamax(cpu) < 44) { + goto fail; + } + break; + case 3: + goto fail; } + startlevel = 3 - sl0; break; default: g_assert_not_reached(); } - - /* Inputsize checks. */ - if (inputsize > outputsize && - (arm_el_is_aa64(&cpu->env, 1) || inputsize > 40)) { - /* This is CONSTRAINED UNPREDICTABLE and we choose to fault. */ - return false; - } } else { - /* AArch32 only supports 4KB pages. Assert on that. */ + /* + * Things are simpler for AArch32 EL2, with only 4k pages. + * There is no separate S2InvalidSL function, but AArch32.S2Walk + * begins with walkparms.sl0 in {'1x'}. + */ assert(stride == 9); - - if (level == 0) { - return false; + if (sl0 >= 2) { + goto fail; } + startlevel = 2 - sl0; } - return true; + + /* AArch{64,32}.S2InconsistentSL are functionally equivalent. */ + levels = 3 - startlevel; + granulebits = stride + 3; + + s1_min_iasize = levels * stride + granulebits + 1; + s1_max_iasize = s1_min_iasize + (stride - 1) + 4; + + if (iasize >= s1_min_iasize && iasize <= s1_max_iasize) { + return startlevel; + } + + fail: + return INT_MIN; } /** @@ -1300,38 +1349,10 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, */ level = 4 - (inputsize - 4) / stride; } else { - /* - * For stage 2 translations the starting level is specified by the - * VTCR_EL2.SL0 field (whose interpretation depends on the page size) - */ - uint32_t sl0 = extract32(tcr, 6, 2); - uint32_t sl2 = extract64(tcr, 33, 1); - int32_t startlevel; - bool ok; - - /* SL2 is RES0 unless DS=1 & 4kb granule. */ - if (param.ds && stride == 9 && sl2) { - if (sl0 != 0) { - level = 0; - goto do_translation_fault; - } - startlevel = -1; - } else if (!aarch64 || stride == 9) { - /* AArch32 or 4KB pages */ - startlevel = 2 - sl0; - - if (cpu_isar_feature(aa64_st, cpu)) { - startlevel &= 3; - } - } else { - /* 16KB or 64KB pages */ - startlevel = 3 - sl0; - } - - /* Check that the starting level is valid. */ - ok = check_s2_mmu_setup(cpu, aarch64, startlevel, - inputsize, stride, outputsize); - if (!ok) { + int startlevel = check_s2_mmu_setup(cpu, aarch64, tcr, param.ds, + inputsize, stride); + if (startlevel == INT_MIN) { + level = 0; goto do_translation_fault; } level = startlevel;